[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE2 / sbclb.s
blob1126523bdebdcfd9eb1e8900d099c99b0354eefd
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
8 // RUN: | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
10 // RUN: | llvm-objdump -d --mattr=-sve2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 sbclb z0.s, z1.s, z31.s
13 // CHECK-INST: sbclb z0.s, z1.s, z31.s
14 // CHECK-ENCODING: [0x20,0xd0,0x9f,0x45]
15 // CHECK-ERROR: instruction requires: sve2 or sme
16 // CHECK-UNKNOWN: 459fd020 <unknown>
18 sbclb z0.d, z1.d, z31.d
19 // CHECK-INST: sbclb z0.d, z1.d, z31.d
20 // CHECK-ENCODING: [0x20,0xd0,0xdf,0x45]
21 // CHECK-ERROR: instruction requires: sve2 or sme
22 // CHECK-UNKNOWN: 45dfd020 <unknown>
25 // --------------------------------------------------------------------------//
26 // Test compatibility with MOVPRFX instruction.
28 movprfx z0, z7
29 // CHECK-INST: movprfx z0, z7
30 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
31 // CHECK-ERROR: instruction requires: sve or sme
32 // CHECK-UNKNOWN: 0420bce0 <unknown>
34 sbclb z0.d, z1.d, z31.d
35 // CHECK-INST: sbclb z0.d, z1.d, z31.d
36 // CHECK-ENCODING: [0x20,0xd0,0xdf,0x45]
37 // CHECK-ERROR: instruction requires: sve2 or sme
38 // CHECK-UNKNOWN: 45dfd020 <unknown>