[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE2 / sqshlu.s
blob05bafae20738e990a5bca365bd7c7886ca5639ad
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
8 // RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
10 // RUN: | llvm-objdump --no-print-imm-hex -d --mattr=-sve2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 sqshlu z0.b, p0/m, z0.b, #0
13 // CHECK-INST: sqshlu z0.b, p0/m, z0.b, #0
14 // CHECK-ENCODING: [0x00,0x81,0x0f,0x04]
15 // CHECK-ERROR: instruction requires: sve2 or sme
16 // CHECK-UNKNOWN: 040f8100 <unknown>
18 sqshlu z31.b, p0/m, z31.b, #7
19 // CHECK-INST: sqshlu z31.b, p0/m, z31.b, #7
20 // CHECK-ENCODING: [0xff,0x81,0x0f,0x04]
21 // CHECK-ERROR: instruction requires: sve2 or sme
22 // CHECK-UNKNOWN: 040f81ff <unknown>
24 sqshlu z0.h, p0/m, z0.h, #0
25 // CHECK-INST: sqshlu z0.h, p0/m, z0.h, #0
26 // CHECK-ENCODING: [0x00,0x82,0x0f,0x04]
27 // CHECK-ERROR: instruction requires: sve2 or sme
28 // CHECK-UNKNOWN: 040f8200 <unknown>
30 sqshlu z31.h, p0/m, z31.h, #15
31 // CHECK-INST: sqshlu z31.h, p0/m, z31.h, #15
32 // CHECK-ENCODING: [0xff,0x83,0x0f,0x04]
33 // CHECK-ERROR: instruction requires: sve2 or sme
34 // CHECK-UNKNOWN: 040f83ff <unknown>
36 sqshlu z0.s, p0/m, z0.s, #0
37 // CHECK-INST: sqshlu z0.s, p0/m, z0.s, #0
38 // CHECK-ENCODING: [0x00,0x80,0x4f,0x04]
39 // CHECK-ERROR: instruction requires: sve2 or sme
40 // CHECK-UNKNOWN: 044f8000 <unknown>
42 sqshlu z31.s, p0/m, z31.s, #31
43 // CHECK-INST: sqshlu z31.s, p0/m, z31.s, #31
44 // CHECK-ENCODING: [0xff,0x83,0x4f,0x04]
45 // CHECK-ERROR: instruction requires: sve2 or sme
46 // CHECK-UNKNOWN: 044f83ff <unknown>
48 sqshlu z0.d, p0/m, z0.d, #0
49 // CHECK-INST: sqshlu z0.d, p0/m, z0.d, #0
50 // CHECK-ENCODING: [0x00,0x80,0x8f,0x04]
51 // CHECK-ERROR: instruction requires: sve2 or sme
52 // CHECK-UNKNOWN: 048f8000 <unknown>
54 sqshlu z31.d, p0/m, z31.d, #63
55 // CHECK-INST: sqshlu z31.d, p0/m, z31.d, #63
56 // CHECK-ENCODING: [0xff,0x83,0xcf,0x04]
57 // CHECK-ERROR: instruction requires: sve2 or sme
58 // CHECK-UNKNOWN: 04cf83ff <unknown>
60 // --------------------------------------------------------------------------//
61 // Test compatibility with MOVPRFX instruction.
63 movprfx z31.d, p0/z, z6.d
64 // CHECK-INST: movprfx z31.d, p0/z, z6.d
65 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
66 // CHECK-ERROR: instruction requires: sve or sme
67 // CHECK-UNKNOWN: 04d020df <unknown>
69 sqshlu z31.d, p0/m, z31.d, #63
70 // CHECK-INST: sqshlu z31.d, p0/m, z31.d, #63
71 // CHECK-ENCODING: [0xff,0x83,0xcf,0x04]
72 // CHECK-ERROR: instruction requires: sve2 or sme
73 // CHECK-UNKNOWN: 04cf83ff <unknown>
75 movprfx z31, z6
76 // CHECK-INST: movprfx z31, z6
77 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
78 // CHECK-ERROR: instruction requires: sve or sme
79 // CHECK-UNKNOWN: 0420bcdf <unknown>
81 sqshlu z31.d, p0/m, z31.d, #63
82 // CHECK-INST: sqshlu z31.d, p0/m, z31.d, #63
83 // CHECK-ENCODING: [0xff,0x83,0xcf,0x04]
84 // CHECK-ERROR: instruction requires: sve2 or sme
85 // CHECK-UNKNOWN: 04cf83ff <unknown>