[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE2 / umulh.s
blobe13a4d7b8bf7eda81ad7983f605109beba68610f
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
8 // RUN: | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
10 // RUN: | llvm-objdump -d --mattr=-sve2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 umulh z0.b, z1.b, z2.b
13 // CHECK-INST: umulh z0.b, z1.b, z2.b
14 // CHECK-ENCODING: [0x20,0x6c,0x22,0x04]
15 // CHECK-ERROR: instruction requires: sve2 or sme
16 // CHECK-UNKNOWN: 04226c20 <unknown>
18 umulh z0.h, z1.h, z2.h
19 // CHECK-INST: umulh z0.h, z1.h, z2.h
20 // CHECK-ENCODING: [0x20,0x6c,0x62,0x04]
21 // CHECK-ERROR: instruction requires: sve2 or sme
22 // CHECK-UNKNOWN: 04626c20 <unknown>
24 umulh z29.s, z30.s, z31.s
25 // CHECK-INST: umulh z29.s, z30.s, z31.s
26 // CHECK-ENCODING: [0xdd,0x6f,0xbf,0x04]
27 // CHECK-ERROR: instruction requires: sve2 or sme
28 // CHECK-UNKNOWN: 04bf6fdd <unknown>
30 umulh z31.d, z31.d, z31.d
31 // CHECK-INST: umulh z31.d, z31.d, z31.d
32 // CHECK-ENCODING: [0xff,0x6f,0xff,0x04]
33 // CHECK-ERROR: instruction requires: sve2 or sme
34 // CHECK-UNKNOWN: 04ff6fff <unknown>