[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE2 / uqxtnt.s
blobab83a129b0c187789d2bb8d8476db91b813ae45d
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
8 // RUN: | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
10 // RUN: | llvm-objdump -d --mattr=-sve2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
13 uqxtnt z0.b, z31.h
14 // CHECK-INST: uqxtnt z0.b, z31.h
15 // CHECK-ENCODING: [0xe0,0x4f,0x28,0x45]
16 // CHECK-ERROR: instruction requires: sve2 or sme
17 // CHECK-UNKNOWN: 45284fe0 <unknown>
19 uqxtnt z0.h, z31.s
20 // CHECK-INST: uqxtnt z0.h, z31.s
21 // CHECK-ENCODING: [0xe0,0x4f,0x30,0x45]
22 // CHECK-ERROR: instruction requires: sve2 or sme
23 // CHECK-UNKNOWN: 45304fe0 <unknown>
25 uqxtnt z0.s, z31.d
26 // CHECK-INST: uqxtnt z0.s, z31.d
27 // CHECK-ENCODING: [0xe0,0x4f,0x60,0x45]
28 // CHECK-ERROR: instruction requires: sve2 or sme
29 // CHECK-UNKNOWN: 45604fe0 <unknown>