[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE2 / whilewr.s
blobf2808171bab5861e81879c0c22775025ecfec069
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
8 // RUN: | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
10 // RUN: | llvm-objdump -d --mattr=-sve2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 whilewr p15.b, x30, x30
13 // CHECK-INST: whilewr p15.b, x30, x30
14 // CHECK-ENCODING: [0xcf,0x33,0x3e,0x25]
15 // CHECK-ERROR: instruction requires: sve2 or sme
16 // CHECK-UNKNOWN: 253e33cf <unknown>
18 whilewr p15.h, x30, x30
19 // CHECK-INST: whilewr p15.h, x30, x30
20 // CHECK-ENCODING: [0xcf,0x33,0x7e,0x25]
21 // CHECK-ERROR: instruction requires: sve2 or sme
22 // CHECK-UNKNOWN: 257e33cf <unknown>
24 whilewr p15.s, x30, x30
25 // CHECK-INST: whilewr p15.s, x30, x30
26 // CHECK-ENCODING: [0xcf,0x33,0xbe,0x25]
27 // CHECK-ERROR: instruction requires: sve2 or sme
28 // CHECK-UNKNOWN: 25be33cf <unknown>
30 whilewr p15.d, x30, x30
31 // CHECK-INST: whilewr p15.d, x30, x30
32 // CHECK-ENCODING: [0xcf,0x33,0xfe,0x25]
33 // CHECK-ERROR: instruction requires: sve2 or sme
34 // CHECK-UNKNOWN: 25fe33cf <unknown>