[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE2 / xar.s
blob2ee6e6abafbe22d378d1af87456bda3c1d689e3a
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
8 // RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
10 // RUN: | llvm-objdump --no-print-imm-hex -d --mattr=-sve2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
12 xar z0.b, z0.b, z1.b, #1
13 // CHECK-INST: xar z0.b, z0.b, z1.b, #1
14 // CHECK-ENCODING: [0x20,0x34,0x2f,0x04]
15 // CHECK-ERROR: instruction requires: sve2 or sme
16 // CHECK-UNKNOWN: 042f3420 <unknown>
18 xar z31.b, z31.b, z30.b, #8
19 // CHECK-INST: xar z31.b, z31.b, z30.b, #8
20 // CHECK-ENCODING: [0xdf,0x37,0x28,0x04]
21 // CHECK-ERROR: instruction requires: sve2 or sme
22 // CHECK-UNKNOWN: 042837df <unknown>
24 xar z0.h, z0.h, z1.h, #1
25 // CHECK-INST: xar z0.h, z0.h, z1.h, #1
26 // CHECK-ENCODING: [0x20,0x34,0x3f,0x04]
27 // CHECK-ERROR: instruction requires: sve2 or sme
28 // CHECK-UNKNOWN: 043f3420 <unknown>
30 xar z31.h, z31.h, z30.h, #16
31 // CHECK-INST: xar z31.h, z31.h, z30.h, #16
32 // CHECK-ENCODING: [0xdf,0x37,0x30,0x04]
33 // CHECK-ERROR: instruction requires: sve2 or sme
34 // CHECK-UNKNOWN: 043037df <unknown>
36 xar z0.s, z0.s, z1.s, #1
37 // CHECK-INST: xar z0.s, z0.s, z1.s, #1
38 // CHECK-ENCODING: [0x20,0x34,0x7f,0x04]
39 // CHECK-ERROR: instruction requires: sve2 or sme
40 // CHECK-UNKNOWN: 047f3420 <unknown>
42 xar z31.s, z31.s, z30.s, #32
43 // CHECK-INST: xar z31.s, z31.s, z30.s, #32
44 // CHECK-ENCODING: [0xdf,0x37,0x60,0x04]
45 // CHECK-ERROR: instruction requires: sve2 or sme
46 // CHECK-UNKNOWN: 046037df <unknown>
48 xar z0.d, z0.d, z1.d, #1
49 // CHECK-INST: xar z0.d, z0.d, z1.d, #1
50 // CHECK-ENCODING: [0x20,0x34,0xff,0x04]
51 // CHECK-ERROR: instruction requires: sve2 or sme
52 // CHECK-UNKNOWN: 04ff3420 <unknown>
54 xar z31.d, z31.d, z30.d, #64
55 // CHECK-INST: xar z31.d, z31.d, z30.d, #64
56 // CHECK-ENCODING: [0xdf,0x37,0xa0,0x04]
57 // CHECK-ERROR: instruction requires: sve2 or sme
58 // CHECK-UNKNOWN: 04a037df <unknown>
61 // --------------------------------------------------------------------------//
62 // Test compatibility with MOVPRFX instruction.
64 movprfx z31, z7
65 // CHECK-INST: movprfx z31, z7
66 // CHECK-ENCODING: [0xff,0xbc,0x20,0x04]
67 // CHECK-ERROR: instruction requires: sve or sme
68 // CHECK-UNKNOWN: 0420bcff <unknown>
70 xar z31.d, z31.d, z30.d, #64
71 // CHECK-INST: xar z31.d, z31.d, z30.d, #64
72 // CHECK-ENCODING: [0xdf,0x37,0xa0,0x04]
73 // CHECK-ERROR: instruction requires: sve2 or sme
74 // CHECK-UNKNOWN: 04a037df <unknown>