llvm/test/MC/AArch64/SVE2p1/bfmls-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 2>&1 < %s | FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // Invalid vector lane index
   5
   6 bfmls z0.h, z0.h, z0.h[8]
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
   8 // CHECK-NEXT: bfmls z0.h, z0.h, z0.h[8]
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 bfmls z0.h, z0.h, z0.h[-1]
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
  13 // CHECK-NEXT: bfmls z0.h, z0.h, z0.h[-1]
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16 bfmls z0.h, z0.h, z8.h[2]
  17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z7.h
  18 // CHECK-NEXT: bfmls z0.h, z0.h, z8.h[2]
  19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  20
  21 // --------------------------------------------------------------------------//
  22 // Invalid vector suffix
  23
  24 bfmls z0.h, z0.s, z0.s[0]
  25 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  26 // CHECK-NEXT: bfmls z0.h, z0.s, z0.s[0]
  27 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  28
  29 bfmls z23.s, z23.h, z13.h
  30 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  31 // CHECK-NEXT: bfmls z23.s, z23.h, z13.h
  32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  33
  34 // --------------------------------------------------------------------------//
  35 // Invalid use of movprfx
  36
  37 movprfx z23.h, p1/m, z31.h
  38 bfmls z23.h, z12.h, z0.h[0]
  39 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
  40 // CHECK-NEXT: bfmls z23.h, z12.h, z0.h[0]
  41 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: