[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE2p1 / fdot.s
blob9005e1f7f0eb2401c6a47b0694aa2592dc3095ef
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
8 // RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
10 // RUN: | llvm-objdump -d --mattr=-sme2,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
11 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
12 // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
13 // RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
14 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
16 movprfx z23, z31
17 fdot z23.s, z13.h, z8.h // 01100100-00101000-10000001-10110111
18 // CHECK-INST: movprfx z23, z31
19 // CHECK-INST: fdot z23.s, z13.h, z8.h
20 // CHECK-ENCODING: [0xb7,0x81,0x28,0x64]
21 // CHECK-ERROR: instruction requires: sme2 or sve2p1
22 // CHECK-UNKNOWN: 642881b7 <unknown>
24 fdot z0.s, z0.h, z0.h // 01100100-00100000-10000000-00000000
25 // CHECK-INST: fdot z0.s, z0.h, z0.h
26 // CHECK-ENCODING: [0x00,0x80,0x20,0x64]
27 // CHECK-ERROR: instruction requires: sme2 or sve2p1
28 // CHECK-UNKNOWN: 64208000 <unknown>
30 fdot z21.s, z10.h, z21.h // 01100100-00110101-10000001-01010101
31 // CHECK-INST: fdot z21.s, z10.h, z21.h
32 // CHECK-ENCODING: [0x55,0x81,0x35,0x64]
33 // CHECK-ERROR: instruction requires: sme2 or sve2p1
34 // CHECK-UNKNOWN: 64358155 <unknown>
36 fdot z23.s, z13.h, z8.h // 01100100-00101000-10000001-10110111
37 // CHECK-INST: fdot z23.s, z13.h, z8.h
38 // CHECK-ENCODING: [0xb7,0x81,0x28,0x64]
39 // CHECK-ERROR: instruction requires: sme2 or sve2p1
40 // CHECK-UNKNOWN: 642881b7 <unknown>
42 fdot z31.s, z31.h, z31.h // 01100100-00111111-10000011-11111111
43 // CHECK-INST: fdot z31.s, z31.h, z31.h
44 // CHECK-ENCODING: [0xff,0x83,0x3f,0x64]
45 // CHECK-ERROR: instruction requires: sme2 or sve2p1
46 // CHECK-UNKNOWN: 643f83ff <unknown>
48 movprfx z23, z31
49 fdot z23.s, z13.h, z0.h[1] // 01100100-00101000-01000001-10110111
50 // CHECK-INST: movprfx z23, z31
51 // CHECK-INST: fdot z23.s, z13.h, z0.h[1]
52 // CHECK-ENCODING: [0xb7,0x41,0x28,0x64]
53 // CHECK-ERROR: instruction requires: sme2 or sve2p1
54 // CHECK-UNKNOWN: 642841b7 <unknown>
56 fdot z0.s, z0.h, z0.h[0] // 01100100-00100000-01000000-00000000
57 // CHECK-INST: fdot z0.s, z0.h, z0.h[0]
58 // CHECK-ENCODING: [0x00,0x40,0x20,0x64]
59 // CHECK-ERROR: instruction requires: sme2 or sve2p1
60 // CHECK-UNKNOWN: 64204000 <unknown>
62 fdot z21.s, z10.h, z5.h[2] // 01100100-00110101-01000001-01010101
63 // CHECK-INST: fdot z21.s, z10.h, z5.h[2]
64 // CHECK-ENCODING: [0x55,0x41,0x35,0x64]
65 // CHECK-ERROR: instruction requires: sme2 or sve2p1
66 // CHECK-UNKNOWN: 64354155 <unknown>
68 fdot z23.s, z13.h, z0.h[1] // 01100100-00101000-01000001-10110111
69 // CHECK-INST: fdot z23.s, z13.h, z0.h[1]
70 // CHECK-ENCODING: [0xb7,0x41,0x28,0x64]
71 // CHECK-ERROR: instruction requires: sme2 or sve2p1
72 // CHECK-UNKNOWN: 642841b7 <unknown>
74 fdot z31.s, z31.h, z7.h[3] // 01100100-00111111-01000011-11111111
75 // CHECK-INST: fdot z31.s, z31.h, z7.h[3]
76 // CHECK-ENCODING: [0xff,0x43,0x3f,0x64]
77 // CHECK-ERROR: instruction requires: sme2 or sve2p1
78 // CHECK-UNKNOWN: 643f43ff <unknown>