[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE2p1 / stnt1d-diagnostics.s
bloba0a8af06df63ed4b23f892debe56ae81b26cb3a4
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
3 // --------------------------------------------------------------------------//
4 // Invalid vector list
6 stnt1d {z0.d-z2.d}, pn8, [x0, x0, lsl #3]
7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
8 // CHECK-NEXT: stnt1d {z0.d-z2.d}, pn8, [x0, x0, lsl #3]
9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
11 stnt1d {z1.d-z4.d}, pn8, [x0, x0, lsl #3]
12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
13 // CHECK-NEXT: stnt1d {z1.d-z4.d}, pn8, [x0, x0, lsl #3]
14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
16 stnt1d {z7.d-z8.d}, pn8, [x0, x0, lsl #3]
17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
18 // CHECK-NEXT: stnt1d {z7.d-z8.d}, pn8, [x0, x0, lsl #3]
19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
21 // --------------------------------------------------------------------------//
22 // Invalid predicate-as-counter register
24 stnt1d {z0.d-z1.d}, pn7, [x0, x0, lsl #3]
25 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15
26 // CHECK-NEXT: stnt1d {z0.d-z1.d}, pn7, [x0, x0, lsl #3]
27 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
29 stnt1d {z0.d-z1.d}, pn8.d, [x13, #-8, mul vl]
30 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15
31 // CHECK-NEXT: stnt1d {z0.d-z1.d}, pn8.d, [x13, #-8, mul vl]
32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
34 // --------------------------------------------------------------------------//
35 // Invalid immediate range
37 stnt1d {z0.d-z3.d}, pn8, [x0, #-9, mul vl]
38 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]
39 // CHECK-NEXT: stnt1d {z0.d-z3.d}, pn8, [x0, #-9, mul vl]
40 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
42 stnt1d {z0.d-z3.d}, pn8, [x0, #-36, mul vl]
43 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]
44 // CHECK-NEXT: stnt1d {z0.d-z3.d}, pn8, [x0, #-36, mul vl]
45 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
47 stnt1d {z0.d-z3.d}, pn8, [x0, #32, mul vl]
48 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]
49 // CHECK-NEXT: stnt1d {z0.d-z3.d}, pn8, [x0, #32, mul vl]
50 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: