[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / SVE2p1 / tblq.s
blob33eaf82bc7d3590c85ce13f76f83c8fcc7870ba3
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
4 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
8 // RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
10 // RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
11 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
12 // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
13 // RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
14 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
17 tblq z0.h, {z0.h}, z0.h // 01000100-01000000-11111000-00000000
18 // CHECK-INST: tblq z0.h, { z0.h }, z0.h
19 // CHECK-ENCODING: [0x00,0xf8,0x40,0x44]
20 // CHECK-ERROR: instruction requires: sme2p1 or sve2p1
21 // CHECK-UNKNOWN: 4440f800 <unknown>
23 tblq z21.h, {z10.h}, z21.h // 01000100-01010101-11111001-01010101
24 // CHECK-INST: tblq z21.h, { z10.h }, z21.h
25 // CHECK-ENCODING: [0x55,0xf9,0x55,0x44]
26 // CHECK-ERROR: instruction requires: sme2p1 or sve2p1
27 // CHECK-UNKNOWN: 4455f955 <unknown>
29 tblq z23.h, {z13.h}, z8.h // 01000100-01001000-11111001-10110111
30 // CHECK-INST: tblq z23.h, { z13.h }, z8.h
31 // CHECK-ENCODING: [0xb7,0xf9,0x48,0x44]
32 // CHECK-ERROR: instruction requires: sme2p1 or sve2p1
33 // CHECK-UNKNOWN: 4448f9b7 <unknown>
35 tblq z31.h, {z31.h}, z31.h // 01000100-01011111-11111011-11111111
36 // CHECK-INST: tblq z31.h, { z31.h }, z31.h
37 // CHECK-ENCODING: [0xff,0xfb,0x5f,0x44]
38 // CHECK-ERROR: instruction requires: sme2p1 or sve2p1
39 // CHECK-UNKNOWN: 445ffbff <unknown>
42 tblq z0.s, {z0.s}, z0.s // 01000100-10000000-11111000-00000000
43 // CHECK-INST: tblq z0.s, { z0.s }, z0.s
44 // CHECK-ENCODING: [0x00,0xf8,0x80,0x44]
45 // CHECK-ERROR: instruction requires: sme2p1 or sve2p1
46 // CHECK-UNKNOWN: 4480f800 <unknown>
48 tblq z21.s, {z10.s}, z21.s // 01000100-10010101-11111001-01010101
49 // CHECK-INST: tblq z21.s, { z10.s }, z21.s
50 // CHECK-ENCODING: [0x55,0xf9,0x95,0x44]
51 // CHECK-ERROR: instruction requires: sme2p1 or sve2p1
52 // CHECK-UNKNOWN: 4495f955 <unknown>
54 tblq z23.s, {z13.s}, z8.s // 01000100-10001000-11111001-10110111
55 // CHECK-INST: tblq z23.s, { z13.s }, z8.s
56 // CHECK-ENCODING: [0xb7,0xf9,0x88,0x44]
57 // CHECK-ERROR: instruction requires: sme2p1 or sve2p1
58 // CHECK-UNKNOWN: 4488f9b7 <unknown>
60 tblq z31.s, {z31.s}, z31.s // 01000100-10011111-11111011-11111111
61 // CHECK-INST: tblq z31.s, { z31.s }, z31.s
62 // CHECK-ENCODING: [0xff,0xfb,0x9f,0x44]
63 // CHECK-ERROR: instruction requires: sme2p1 or sve2p1
64 // CHECK-UNKNOWN: 449ffbff <unknown>
67 tblq z0.d, {z0.d}, z0.d // 01000100-11000000-11111000-00000000
68 // CHECK-INST: tblq z0.d, { z0.d }, z0.d
69 // CHECK-ENCODING: [0x00,0xf8,0xc0,0x44]
70 // CHECK-ERROR: instruction requires: sme2p1 or sve2p1
71 // CHECK-UNKNOWN: 44c0f800 <unknown>
73 tblq z21.d, {z10.d}, z21.d // 01000100-11010101-11111001-01010101
74 // CHECK-INST: tblq z21.d, { z10.d }, z21.d
75 // CHECK-ENCODING: [0x55,0xf9,0xd5,0x44]
76 // CHECK-ERROR: instruction requires: sme2p1 or sve2p1
77 // CHECK-UNKNOWN: 44d5f955 <unknown>
79 tblq z23.d, {z13.d}, z8.d // 01000100-11001000-11111001-10110111
80 // CHECK-INST: tblq z23.d, { z13.d }, z8.d
81 // CHECK-ENCODING: [0xb7,0xf9,0xc8,0x44]
82 // CHECK-ERROR: instruction requires: sme2p1 or sve2p1
83 // CHECK-UNKNOWN: 44c8f9b7 <unknown>
85 tblq z31.d, {z31.d}, z31.d // 01000100-11011111-11111011-11111111
86 // CHECK-INST: tblq z31.d, { z31.d }, z31.d
87 // CHECK-ENCODING: [0xff,0xfb,0xdf,0x44]
88 // CHECK-ERROR: instruction requires: sme2p1 or sve2p1
89 // CHECK-UNKNOWN: 44dffbff <unknown>
92 tblq z0.b, {z0.b}, z0.b // 01000100-00000000-11111000-00000000
93 // CHECK-INST: tblq z0.b, { z0.b }, z0.b
94 // CHECK-ENCODING: [0x00,0xf8,0x00,0x44]
95 // CHECK-ERROR: instruction requires: sme2p1 or sve2p1
96 // CHECK-UNKNOWN: 4400f800 <unknown>
98 tblq z21.b, {z10.b}, z21.b // 01000100-00010101-11111001-01010101
99 // CHECK-INST: tblq z21.b, { z10.b }, z21.b
100 // CHECK-ENCODING: [0x55,0xf9,0x15,0x44]
101 // CHECK-ERROR: instruction requires: sme2p1 or sve2p1
102 // CHECK-UNKNOWN: 4415f955 <unknown>
104 tblq z23.b, {z13.b}, z8.b // 01000100-00001000-11111001-10110111
105 // CHECK-INST: tblq z23.b, { z13.b }, z8.b
106 // CHECK-ENCODING: [0xb7,0xf9,0x08,0x44]
107 // CHECK-ERROR: instruction requires: sme2p1 or sve2p1
108 // CHECK-UNKNOWN: 4408f9b7 <unknown>
110 tblq z31.b, {z31.b}, z31.b // 01000100-00011111-11111011-11111111
111 // CHECK-INST: tblq z31.b, { z31.b }, z31.b
112 // CHECK-ENCODING: [0xff,0xfb,0x1f,0x44]
113 // CHECK-ERROR: instruction requires: sme2p1 or sve2p1
114 // CHECK-UNKNOWN: 441ffbff <unknown>