[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / coff-relocations-branch26.s
blob4cd47032309cae820a15836eff1730cc9fad2d07
1 // RUN: llvm-mc -triple aarch64-unknown-windows-msvc -filetype obj %s -o - | llvm-objdump -D -r - | FileCheck %s
2 // RUN: not llvm-mc -triple aarch64-unknown-windows-msvc -filetype obj --defsym ERR=1 %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=ERR
4 .text
5 main:
6 nop
7 b .Ltarget
8 b .Lother_target
10 // A privte label target in the same section
11 .def .Ltarget
12 .scl 3
13 .type 32
14 .endef
15 .p2align 2
16 .Ltarget:
17 ret
19 // A privte label target in another section
20 .section "other"
21 nop
22 nop
23 nop
24 nop
25 nop
26 nop
27 nop
28 nop
29 .def .Lother_target
30 .scl 3
31 .type 32
32 .endef
33 .p2align 2
34 .Lother_target:
35 ret
37 // Check that both branches have a relocation with a zero offset.
39 // CHECK: 0000000000000000 <main>:
40 // CHECK: 0: d503201f nop
41 // CHECK: 4: 14000000 b 0x4 <main+0x4>
42 // CHECK: 0000000000000004: IMAGE_REL_ARM64_BRANCH26 .Ltarget
43 // CHECK: 8: 14000000 b 0x8 <main+0x8>
44 // CHECK: 0000000000000008: IMAGE_REL_ARM64_BRANCH26 .Lother_target
45 // CHECK: 000000000000000c <.Ltarget>:
46 // CHECK: c: d65f03c0 ret
47 // CHECK: 0000000000000000 <other>:
48 // CHECK: 0: d503201f nop
49 // CHECK: 4: d503201f nop
50 // CHECK: 8: d503201f nop
51 // CHECK: c: d503201f nop
52 // CHECK: 10: d503201f nop
53 // CHECK: 14: d503201f nop
54 // CHECK: 18: d503201f nop
55 // CHECK: 1c: d503201f nop
56 // CHECK: 0000000000000020 <.Lother_target>:
57 // CHECK: 20: d65f03c0 ret
59 .ifdef ERR
60 .section "err"
61 err:
62 nop
63 b .Lerr_target+4
64 // ERR: [[#@LINE-1]]:5: error: cannot perform a PC-relative fixup with a non-zero symbol offset
66 .def .Lerr_target
67 .scl 3
68 .type 32
69 .p2align 2
70 .endef
71 .Lerr_target:
72 nop
73 nop
74 ret
75 .endif