[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / AArch64 / coff-relocations.s
blobfb67a21992c6df3d0c49cf16c4def5f7348ee3e3
1 // RUN: llvm-mc -triple aarch64-windows -filetype obj -o %t.obj %s
2 // RUN: llvm-readobj -r %t.obj | FileCheck %s
3 // RUN: llvm-objdump --no-print-imm-hex -d %t.obj | FileCheck %s --check-prefix=DISASM
4 // RUN: llvm-objdump -s %t.obj | FileCheck %s --check-prefix=DATA
6 // IMAGE_REL_ARM64_ADDR32
7 .Linfo_foo:
8 .asciz "foo"
9 .long foo
11 // IMAGE_REL_ARM64_ADDR32NB
12 .long func@IMGREL
14 // IMAGE_REL_ARM64_ADDR64
15 .globl struc
16 struc:
17 .quad arr
19 // IMAGE_REL_ARM64_BRANCH26
20 b target
22 // IMAGE_REL_ARM64_PAGEBASE_REL21
23 adrp x0, foo
25 // IMAGE_REL_ARM64_PAGEOFFSET_12A
26 add x0, x0, :lo12:foo
28 // IMAGE_REL_ARM64_PAGEOFFSET_12L
29 ldr x0, [x0, :lo12:foo]
31 // IMAGE_REL_ARM64_PAGEBASE_REL21, even if the symbol offset is known
32 adrp x0, bar
33 bar:
35 // IMAGE_REL_ARM64_SECREL
36 .secrel32 .Linfo_bar
37 .Linfo_bar:
39 // IMAGE_REL_ARM64_SECTION
40 .secidx func
42 .align 2
43 adrp x0, baz + 0x12345
44 baz:
45 add x0, x0, :lo12:foo + 0x12345
46 ldrb w0, [x0, :lo12:foo + 0x12345]
47 ldr x0, [x0, :lo12:foo + 0x12348]
49 // IMAGE_REL_ARM64_SECREL_LOW12A
50 add x0, x0, :secrel_lo12:foo
51 // IMAGE_REL_ARM64_SECREL_HIGH12A
52 add x0, x0, :secrel_hi12:foo
53 // IMAGE_REL_ARM64_SECREL_LOW12L
54 ldr x0, [x0, :secrel_lo12:foo]
56 // IMAGE_REL_ARM64_REL21
57 adr x0, foo + 0x12345
59 // IMAGE_REL_ARM64_BRANCH19
60 bne target
62 // IMAGE_REL_ARM64_BRANCH14
63 tbz x0, #0, target
65 .section .rdata, "dr"
66 .Ltable:
67 .word .Linfo_bar - .Ltable
68 .word .Linfo_foo - .Ltable
70 // As an extension, we allow 64-bit label differences. They lower to
71 // IMAGE_REL_ARM64_REL32 because IMAGE_REL_ARM64_REL64 does not exist.
72 .xword .Linfo_foo - .Ltable
74 // CHECK: Format: COFF-ARM64
75 // CHECK: Arch: aarch64
76 // CHECK: AddressSize: 64bit
77 // CHECK: Relocations [
78 // CHECK: Section (1) .text {
79 // CHECK: 0x4 IMAGE_REL_ARM64_ADDR32 foo
80 // CHECK: 0x8 IMAGE_REL_ARM64_ADDR32NB func
81 // CHECK: 0xC IMAGE_REL_ARM64_ADDR64 arr
82 // CHECK: 0x14 IMAGE_REL_ARM64_BRANCH26 target
83 // CHECK: 0x18 IMAGE_REL_ARM64_PAGEBASE_REL21 foo
84 // CHECK: 0x1C IMAGE_REL_ARM64_PAGEOFFSET_12A foo
85 // CHECK: 0x20 IMAGE_REL_ARM64_PAGEOFFSET_12L foo
86 // CHECK: 0x24 IMAGE_REL_ARM64_PAGEBASE_REL21 bar
87 // CHECK: 0x28 IMAGE_REL_ARM64_SECREL .text
88 // CHECK: 0x2C IMAGE_REL_ARM64_SECTION func
89 // CHECK: 0x30 IMAGE_REL_ARM64_PAGEBASE_REL21 baz
90 // CHECK: 0x34 IMAGE_REL_ARM64_PAGEOFFSET_12A foo
91 // CHECK: 0x38 IMAGE_REL_ARM64_PAGEOFFSET_12L foo
92 // CHECK: 0x3C IMAGE_REL_ARM64_PAGEOFFSET_12L foo
93 // CHECK: 0x40 IMAGE_REL_ARM64_SECREL_LOW12A foo
94 // CHECK: 0x44 IMAGE_REL_ARM64_SECREL_HIGH12A foo
95 // CHECK: 0x48 IMAGE_REL_ARM64_SECREL_LOW12L foo
96 // CHECK: 0x4C IMAGE_REL_ARM64_REL21 foo
97 // CHECK: 0x50 IMAGE_REL_ARM64_BRANCH19 target
98 // CHECK: 0x54 IMAGE_REL_ARM64_BRANCH14 target
99 // CHECK: }
100 // CHECK: Section (4) .rdata {
101 // CHECK: 0x0 IMAGE_REL_ARM64_REL32 .text
102 // CHECK: 0x4 IMAGE_REL_ARM64_REL32 .text
103 // CHECK: 0x8 IMAGE_REL_ARM64_REL32 .text
104 // CHECK: }
105 // CHECK: ]
107 // DISASM: 30: b0091a20 adrp x0, 0x12345000
108 // DISASM: 34: 910d1400 add x0, x0, #837
109 // DISASM: 38: 394d1400 ldrb w0, [x0, #837]
110 // DISASM: 3c: f941a400 ldr x0, [x0, #840]
111 // DISASM: 40: 91000000 add x0, x0, #0
112 // DISASM: 44: 91400000 add x0, x0, #0, lsl #12
113 // DISASM: 48: f9400000 ldr x0, [x0]
114 // DISASM: 4c: 30091a20 adr x0, 0x12391
116 // DATA: Contents of section .rdata:
117 // DATA-NEXT: 0000 30000000 08000000