1 // RUN
: not llvm-mc
-triple
=amdgcn
-mcpu
=bonaire
%s
2>&1 | FileCheck
%s
--implicit-check-
not=error
: --strict-whitespace
3 //==============================================================================
4 // cache policy is
not supported for SMRD instructions
6 s_load_dword s1
, s
[2:3], 0xfc glc slc
7 // CHECK
: :[[@LINE-
1]]:{{[0-9]+}}: error
: cache policy is
not supported for SMRD instructions
8 // CHECK-NEXT
:{{^
}}s_load_dword s1
, s
[2:3], 0xfc glc slc
11 s_load_dword s1
, s
[2:3], 0xfc slc
12 // CHECK
: :[[@LINE-
1]]:{{[0-9]+}}: error
: cache policy is
not supported for SMRD instructions
13 // CHECK-NEXT
:{{^
}}s_load_dword s1
, s
[2:3], 0xfc slc
16 //==============================================================================
17 // d16 modifier is
not supported on this GPU
19 image_gather4 v
[5:6], v1
, s
[8:15], s
[12:15] dmask
:0x1 d16
20 // CHECK
: :[[@LINE-
1]]:{{[0-9]+}}: error
: d16 modifier is
not supported on this GPU
21 // CHECK-NEXT
:{{^
}}image_gather4 v
[5:6], v1
, s
[8:15], s
[12:15] dmask
:0x1 d16
24 //==============================================================================
25 // integer clamping is
not supported on this GPU
27 v_add_co_u32 v84
, s
[4:5], v13
, v31 clamp
28 // CHECK
: :[[@LINE-
1]]:{{[0-9]+}}: error
: integer clamping is
not supported on this GPU
29 // CHECK-NEXT
:{{^
}}v_add_co_u32 v84
, s
[4:5], v13
, v31 clamp
32 //==============================================================================
33 // literal operands are
not supported
35 v_and_b32_e64 v0
, 0.159154943091895317852646485335, v1
36 // CHECK
: :[[@LINE-
1]]:{{[0-9]+}}: error
: literal operands are
not supported
37 // CHECK-NEXT
:{{^
}}v_and_b32_e64 v0
, 0.159154943091895317852646485335, v1
40 //==============================================================================
41 // cache policy is
not supported for SMRD instructions
43 s_load_dword s5
, s
[2:3], glc
44 // CHECK
: :[[@LINE-
1]]:{{[0-9]+}}: error
: cache policy is
not supported for SMRD instructions
45 // CHECK-NEXT
:{{^
}}s_load_dword s5
, s
[2:3], glc