llvm/test/MC/AMDGPU/sop1-err.s

   1 // RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck -check-prefix=GCN --implicit-check-not=error: %s
   2 // RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=GCN --implicit-check-not=error: %s
   3 // RUN: not llvm-mc -triple=amdgcn -mcpu=tonga %s 2>&1 | FileCheck --check-prefixes=GCN,VI --implicit-check-not=error: %s
   4
   5 s_mov_b32 v1, s2
   6 // GCN: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
   7
   8 s_mov_b32 s1, v0
   9 // GCN: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  10
  11 s_mov_b32 s[1:2], s0
  12 // GCN: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register alignment
  13
  14 s_mov_b32 s0, s[1:2]
  15 // GCN: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register alignment
  16
  17 s_mov_b32 s220, s0
  18 // GCN: :[[@LINE-1]]:{{[0-9]+}}: error: register index is out of range
  19
  20 s_mov_b32 s0, s220
  21 // GCN: :[[@LINE-1]]:{{[0-9]+}}: error: register index is out of range
  22
  23 s_mov_b64 s1, s[0:1]
  24 // GCN: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  25
  26 s_mov_b64 s[0:1], s1
  27 // GCN: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  28
  29 // FIXME: This shoudl probably say failed to parse.
  30 s_mov_b32 s
  31 // GCN: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  32 // Out of range register
  33
  34 s_mov_b32 s102, 1
  35 // VI: :[[@LINE-1]]:{{[0-9]+}}: error: register not available on this GPU
  36
  37 s_mov_b32 s103, 1
  38 // VI: :[[@LINE-1]]:{{[0-9]+}}: error: register not available on this GPU
  39
  40 s_mov_b64 s[102:103], -1
  41 // VI: :[[@LINE-1]]:{{[0-9]+}}: error: register not available on this GPU
  42
  43 s_setpc_b64 0
  44 // GCN: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction