[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / MC / Hexagon / sysregs.s
blob3a11d6b5abe07040701f4c625352aab154238718
1 # RUN: llvm-mc -triple=hexagon -filetype=asm %s | FileCheck %s
4 r1:0=s75:74
5 # CHECK: r1:0 = s75:74
6 r1:0=s73:72
7 # CHECK: r1:0 = s73:72
8 r1:0=s71:70
9 # CHECK: r1:0 = s71:70
10 r1:0=s69:68
11 # CHECK: r1:0 = s69:68
12 r1:0=s67:66
13 # CHECK: r1:0 = s67:66
14 r1:0=s65:64
15 # CHECK: r1:0 = s65:64
16 r1:0=s63:62
17 # CHECK: r1:0 = s63:62
18 r1:0=s61:60
19 # CHECK: r1:0 = s61:60
20 r1:0=s53:52
21 # CHECK: r1:0 = s53:52
22 r1:0=s51:50
23 # CHECK: r1:0 = s51:50
24 r1:0=s49:48
25 # CHECK: r1:0 = s49:48
26 r1:0=s47:46
27 # CHECK: r1:0 = s47:46
28 r1:0=s45:44
29 # CHECK: r1:0 = s45:44
30 r1:0=s43:42
31 # CHECK: r1:0 = s43:42
32 r1:0=s41:40
33 # CHECK: r1:0 = s41:40
34 r1:0=s39:38
35 # CHECK: r1:0 = s39:38
36 r1:0=s37:36
37 # CHECK: r1:0 = s37:36
38 r1:0=s31:30
39 # CHECK: r1:0 = s31:30
40 r1:0=c1:0
41 # CHECK: r1:0 = c1:0
42 r1:0=s35:34
43 # CHECK: r1:0 = s35:34
44 r1:0=s33:32
45 # CHECK: r1:0 = s33:32
46 r1:0=s31:30
47 # CHECK: r1:0 = s31:30
48 r1:0=s29:28
49 # CHECK: r1:0 = s29:28
50 r1:0=s27:26
51 # CHECK: r1:0 = s27:26
52 r1:0=s21:20
53 # CHECK: r1:0 = s21:20
54 r1:0=s19:18
55 # CHECK: r1:0 = s19:18
56 r1:0=s17:16
57 # CHECK: r1:0 = s17:16
58 r1:0=s9:8
59 # CHECK: r1:0 = s9:8
60 r1:0=s7:6
61 # CHECK: r1:0 = s7:6
62 r1:0=s5:4
63 # CHECK: r1:0 = s5:4
64 r1:0=s3:2
65 # CHECK: r1:0 = s3:2
66 r1=s54
67 # CHECK: r1 = s54
68 r0=s59
69 # CHECK: r0 = s59
70 r0=s44
71 # CHECK: r0 = s44
72 r0=s45
73 # CHECK: r0 = s45
74 r0=s46
75 # CHECK: r0 = s46
76 r0=s47
77 # CHECK: r0 = s47
79 r0=s56
80 # CHECK: r0 = s56
82 r1:0=pcycle
83 # CHECK: r1:0 = s31:30