[AMDGPU] Add True16 register classes.
[llvm-project.git] / llvm / test / Transforms / Inline / WebAssembly / inline-target-features.ll
blob5b8eabc717d8a58b9bd553c288cb0659743da553
1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2 ; RUN: opt < %s -mtriple=wasm32-unknown-unknown -S -passes=inline | FileCheck %s
4 ; Check that having functions can be inlined into callers only when
5 ; they have a subset of the caller's features.
7 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
8 target triple = "wasm32-unknown-unknown"
10 declare void @foo()
12 define internal void @uses_simd() #0 {
13 ; CHECK-LABEL: @uses_simd(
14 ; CHECK-NEXT:    tail call void @foo()
15 ; CHECK-NEXT:    ret void
17   tail call void @foo()
18   ret void
21 define void @many_features() #1 {
22 ; CHECK-LABEL: @many_features(
23 ; CHECK-NEXT:    tail call void @foo()
24 ; CHECK-NEXT:    ret void
26   tail call fastcc void @uses_simd()
27   ret void
30 define void @few_features() #2 {
31 ; CHECK-LABEL: @few_features(
32 ; CHECK-NEXT:    tail call fastcc void @uses_simd()
33 ; CHECK-NEXT:    ret void
35   tail call fastcc void @uses_simd()
36   ret void
39 attributes #0 = { "target-cpu"="mvp" "target-features"="+simd128"}
40 attributes #1 = { "target-cpu"="bleeding-edge" "target-features"="+simd128" }
41 attributes #2 = { "target-cpu"="mvp" "target-features"="+multivalue" }