llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td

   1 //==- RISCVSchedSiFiveP600.td - SiFiveP600 Scheduling Defs ---*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 //===----------------------------------------------------------------------===//
  10
  11 /// c is true if mx has the worst case behavior compared to LMULs in MxList.
  12 /// On the SiFiveP600, the worst case LMUL is the Largest LMUL
  13 /// and the worst case sew is the smallest SEW for that LMUL.
  14 class SiFiveP600IsWorstCaseMX<string mx, list<string> MxList> {
  15   string LLMUL = LargestLMUL<MxList>.r;
  16   bit c = !eq(mx, LLMUL);
  17 }
  18
  19 class SiFiveP600IsWorstCaseMXSEW<string mx, int sew, list<string> MxList, bit isF = 0> {
  20   string LLMUL = LargestLMUL<MxList>.r;
  21   int SSEW = SmallestSEW<mx, isF>.r;
  22   bit c = !and(!eq(mx, LLMUL), !eq(sew, SSEW));
  23 }
  24
  25 // 1 Micro-Op per cycle.
  26 class SiFiveP600GetLMulCycles<string mx> {
  27   int c = !cond(
  28     !eq(mx, "M1") : 1,
  29     !eq(mx, "M2") : 2,
  30     !eq(mx, "M4") : 4,
  31     !eq(mx, "M8") : 8,
  32     !eq(mx, "MF2") : 1,
  33     !eq(mx, "MF4") : 1,
  34     !eq(mx, "MF8") : 1
  35   );
  36 }
  37
  38 // Latency for segmented loads and stores are calculated as vl * nf.
  39 class SiFiveP600GetCyclesSegmented<string mx, int sew, int nf> {
  40   defvar VLEN = 128;
  41   defvar VLUpperBound = !cond(
  42     !eq(mx, "M1") : !div(VLEN, sew),
  43     !eq(mx, "M2") : !div(!mul(VLEN, 2), sew),
  44     !eq(mx, "M4") : !div(!mul(VLEN, 4), sew),
  45     !eq(mx, "M8") : !div(!mul(VLEN, 8), sew),
  46     !eq(mx, "MF2") : !div(!div(VLEN, 2), sew),
  47     !eq(mx, "MF4") : !div(!div(VLEN, 4), sew),
  48     !eq(mx, "MF8") : !div(!div(VLEN, 8), sew),
  49   );
  50   int c = !mul(VLUpperBound, nf);
  51 }
  52
  53 // SiFiveP600 machine model for scheduling and other instruction cost heuristics.
  54 def SiFiveP600Model : SchedMachineModel {
  55   let IssueWidth = 4;         // 4 micro-ops are dispatched per cycle.
  56   let MicroOpBufferSize = 160; // Max micro-ops that can be buffered.
  57   let LoadLatency = 4;        // Cycles for loads to access the cache.
  58   let MispredictPenalty = 9;  // Extra cycles for a mispredicted branch.
  59   let PostRAScheduler = true;
  60   let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
  61                              HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
  62                              HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
  63                              HasVendorXSfvqmaccqoq];
  64   let CompleteModel = false;
  65 }
  66
  67 let SchedModel = SiFiveP600Model in {
  68
  69 def SiFiveP600IEXQ0       : ProcResource<1>;
  70 def SiFiveP600IEXQ1       : ProcResource<1>;
  71 def SiFiveP600IEXQ2       : ProcResource<1>;
  72 def SiFiveP600IEXQ3       : ProcResource<1>;
  73 def SiFiveP600FEXQ0       : ProcResource<1>;
  74 def SiFiveP600FEXQ1       : ProcResource<1>;
  75
  76 // Two Load/Store ports that can issue either two loads, two stores, or one load
  77 // and one store (P550 has one load and one separate store pipe).
  78 def SiFiveP600LDST       : ProcResource<2>;
  79
  80 // 4-wide pipeline with 4 ALU pipes.
  81 def SiFiveP600IntArith    : ProcResGroup<[SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3]>;
  82 defvar SiFiveP600SYS      = SiFiveP600IEXQ0;
  83 defvar SiFiveP600CMOV     = SiFiveP600IEXQ0;
  84 defvar SiFiveP600MulI2F   = SiFiveP600IEXQ1;
  85 def SiFiveP600Branch      : ProcResGroup<[SiFiveP600IEXQ2, SiFiveP600IEXQ3]>;
  86 def SiFiveP600Div         : ProcResource<1>;
  87
  88 def SiFiveP600FloatArith  : ProcResGroup<[SiFiveP600FEXQ0, SiFiveP600FEXQ1]>;
  89 defvar SiFiveP600F2I      = SiFiveP600FEXQ0;
  90 def SiFiveP600FloatDiv    : ProcResource<1>;
  91
  92 // Vector pipeline
  93 // VEXQ0 handle Mask, Simple Slide instructions,
  94 // VEXQ1 handle Complex Slide, Permutation, Reductions, Divide instructions.
  95 // Other vector instructions can be done in VEXQ0 and VEXQ1.
  96 def SiFiveP600VEXQ0        : ProcResource<1>;
  97 def SiFiveP600VEXQ1        : ProcResource<1>;
  98 def SiFiveP600VectorArith  : ProcResGroup<[SiFiveP600VEXQ0, SiFiveP600VEXQ1]>;
  99 def SiFiveP600VLD          : ProcResource<1>;
 100 def SiFiveP600VST          : ProcResource<1>;
 101 def SiFiveP600VDiv         : ProcResource<1>;
 102 def SiFiveP600VFloatDiv    : ProcResource<1>;
 103
 104 // Integer arithmetic and logic
 105 def : WriteRes<WriteIALU, [SiFiveP600IntArith]>;
 106 def : WriteRes<WriteIALU32, [SiFiveP600IntArith]>;
 107 def : WriteRes<WriteShiftImm, [SiFiveP600IntArith]>;
 108 def : WriteRes<WriteShiftImm32, [SiFiveP600IntArith]>;
 109 def : WriteRes<WriteShiftReg, [SiFiveP600IntArith]>;
 110 def : WriteRes<WriteShiftReg32, [SiFiveP600IntArith]>;
 111 // Branching
 112 def : WriteRes<WriteJmp, [SiFiveP600Branch]>;
 113 def : WriteRes<WriteJal, [SiFiveP600Branch]>;
 114 def : WriteRes<WriteJalr, [SiFiveP600Branch]>;
 115
 116 // CMOV
 117 def P600WriteCMOV : SchedWriteRes<[SiFiveP600Branch, SiFiveP600CMOV]> {
 118   let Latency = 2;
 119   let NumMicroOps = 2;
 120 }
 121 def : InstRW<[P600WriteCMOV], (instrs PseudoCCMOVGPRNoX0)>;
 122
 123 let Latency = 3 in {
 124 // Integer multiplication
 125 def : WriteRes<WriteIMul, [SiFiveP600MulI2F]>;
 126 def : WriteRes<WriteIMul32, [SiFiveP600MulI2F]>;
 127 // cpop[w] look exactly like multiply.
 128 def : WriteRes<WriteCPOP, [SiFiveP600MulI2F]>;
 129 def : WriteRes<WriteCPOP32, [SiFiveP600MulI2F]>;
 130 }
 131
 132 // Integer division
 133 def : WriteRes<WriteIDiv, [SiFiveP600MulI2F, SiFiveP600Div]> {
 134   let Latency = 35;
 135   let ReleaseAtCycles = [1, 34];
 136 }
 137 def : WriteRes<WriteIDiv32,  [SiFiveP600MulI2F, SiFiveP600Div]> {
 138   let Latency = 20;
 139   let ReleaseAtCycles = [1, 19];
 140 }
 141
 142 // Integer remainder
 143 def : WriteRes<WriteIRem, [SiFiveP600MulI2F, SiFiveP600Div]> {
 144   let Latency = 35;
 145   let ReleaseAtCycles = [1, 34];
 146 }
 147 def : WriteRes<WriteIRem32, [SiFiveP600MulI2F, SiFiveP600Div]> {
 148   let Latency = 20;
 149   let ReleaseAtCycles = [1, 19];
 150 }
 151
 152 // Bitmanip
 153 def : WriteRes<WriteRotateImm, [SiFiveP600IntArith]>;
 154 def : WriteRes<WriteRotateImm32, [SiFiveP600IntArith]>;
 155 def : WriteRes<WriteRotateReg, [SiFiveP600IntArith]>;
 156 def : WriteRes<WriteRotateReg32, [SiFiveP600IntArith]>;
 157
 158 def : WriteRes<WriteCLZ, [SiFiveP600IntArith]>;
 159 def : WriteRes<WriteCLZ32, [SiFiveP600IntArith]>;
 160 def : WriteRes<WriteCTZ, [SiFiveP600IntArith]>;
 161 def : WriteRes<WriteCTZ32, [SiFiveP600IntArith]>;
 162
 163 def : WriteRes<WriteORCB, [SiFiveP600IntArith]>;
 164 def : WriteRes<WriteIMinMax, [SiFiveP600IntArith]>;
 165
 166 def : WriteRes<WriteREV8, [SiFiveP600IntArith]>;
 167
 168 def : WriteRes<WriteSHXADD, [SiFiveP600IntArith]>;
 169 def : WriteRes<WriteSHXADD32, [SiFiveP600IntArith]>;
 170
 171 def : WriteRes<WriteSingleBit, [SiFiveP600IntArith]>;
 172 def : WriteRes<WriteSingleBitImm, [SiFiveP600IntArith]>;
 173 def : WriteRes<WriteBEXT, [SiFiveP600IntArith]>;
 174 def : WriteRes<WriteBEXTI, [SiFiveP600IntArith]>;
 175
 176 // Memory
 177 def : WriteRes<WriteSTB, [SiFiveP600LDST]>;
 178 def : WriteRes<WriteSTH, [SiFiveP600LDST]>;
 179 def : WriteRes<WriteSTW, [SiFiveP600LDST]>;
 180 def : WriteRes<WriteSTD, [SiFiveP600LDST]>;
 181 def : WriteRes<WriteFST16, [SiFiveP600LDST]>;
 182 def : WriteRes<WriteFST32, [SiFiveP600LDST]>;
 183 def : WriteRes<WriteFST64, [SiFiveP600LDST]>;
 184
 185 let Latency = 4 in {
 186 def : WriteRes<WriteLDB, [SiFiveP600LDST]>;
 187 def : WriteRes<WriteLDH, [SiFiveP600LDST]>;
 188 }
 189 let Latency = 4 in {
 190 def : WriteRes<WriteLDW, [SiFiveP600LDST]>;
 191 def : WriteRes<WriteLDD, [SiFiveP600LDST]>;
 192 }
 193
 194 let Latency = 6 in {
 195 def : WriteRes<WriteFLD16, [SiFiveP600LDST]>;
 196 def : WriteRes<WriteFLD32, [SiFiveP600LDST]>;
 197 def : WriteRes<WriteFLD64, [SiFiveP600LDST]>;
 198 }
 199
 200 // Atomic memory
 201 let Latency = 3 in {
 202 def : WriteRes<WriteAtomicSTW, [SiFiveP600LDST]>;
 203 def : WriteRes<WriteAtomicSTD, [SiFiveP600LDST]>;
 204 def : WriteRes<WriteAtomicW, [SiFiveP600LDST]>;
 205 def : WriteRes<WriteAtomicD, [SiFiveP600LDST]>;
 206 def : WriteRes<WriteAtomicLDW, [SiFiveP600LDST]>;
 207 def : WriteRes<WriteAtomicLDD, [SiFiveP600LDST]>;
 208 }
 209
 210 // Floating point
 211 let Latency = 2 in {
 212 def : WriteRes<WriteFAdd16, [SiFiveP600FloatArith]>;
 213 def : WriteRes<WriteFAdd32, [SiFiveP600FloatArith]>;
 214 def : WriteRes<WriteFAdd64, [SiFiveP600FloatArith]>;
 215 }
 216 let Latency = 3 in {
 217 def : WriteRes<WriteFMul16, [SiFiveP600FloatArith]>;
 218 def : WriteRes<WriteFMul32, [SiFiveP600FloatArith]>;
 219 def : WriteRes<WriteFMul64, [SiFiveP600FloatArith]>;
 220 }
 221 let Latency = 4 in {
 222 def : WriteRes<WriteFMA16, [SiFiveP600FloatArith]>;
 223 def : WriteRes<WriteFMA32, [SiFiveP600FloatArith]>;
 224 def : WriteRes<WriteFMA64, [SiFiveP600FloatArith]>;
 225 }
 226
 227 let Latency = 2 in {
 228 def : WriteRes<WriteFSGNJ16, [SiFiveP600FloatArith]>;
 229 def : WriteRes<WriteFSGNJ32, [SiFiveP600FloatArith]>;
 230 def : WriteRes<WriteFSGNJ64, [SiFiveP600FloatArith]>;
 231
 232 def : WriteRes<WriteFMinMax16, [SiFiveP600FloatArith]>;
 233 def : WriteRes<WriteFMinMax32, [SiFiveP600FloatArith]>;
 234 def : WriteRes<WriteFMinMax64, [SiFiveP600FloatArith]>;
 235 }
 236
 237 // Half precision.
 238 def : WriteRes<WriteFDiv16, [SiFiveP600FEXQ1, SiFiveP600FloatDiv]> {
 239   let Latency = 4;
 240   let ReleaseAtCycles = [1, 4];
 241 }
 242 def : WriteRes<WriteFSqrt16, [SiFiveP600FEXQ1, SiFiveP600FloatDiv]> {
 243   let Latency = 18;
 244   let ReleaseAtCycles = [1, 17];
 245 }
 246
 247 // Single precision.
 248 def : WriteRes<WriteFDiv32, [SiFiveP600FEXQ1, SiFiveP600FloatDiv]> {
 249   let Latency = 6;
 250   let ReleaseAtCycles = [1, 6];
 251 }
 252 def : WriteRes<WriteFSqrt32, [SiFiveP600FEXQ1, SiFiveP600FloatDiv]> {
 253   let Latency = 18;
 254   let ReleaseAtCycles = [1, 17];
 255 }
 256
 257 // Double precision
 258 def : WriteRes<WriteFDiv64, [SiFiveP600FEXQ1, SiFiveP600FloatDiv]> {
 259   let Latency = 11;
 260   let ReleaseAtCycles = [1, 11];
 261 }
 262 def : WriteRes<WriteFSqrt64, [SiFiveP600FEXQ1, SiFiveP600FloatDiv]> {
 263   let Latency = 33;
 264   let ReleaseAtCycles = [1, 32];
 265 }
 266
 267 // Conversions
 268 let Latency = 2 in {
 269 def : WriteRes<WriteFCvtI32ToF16, [SiFiveP600MulI2F]>;
 270 def : WriteRes<WriteFCvtI32ToF32, [SiFiveP600MulI2F]>;
 271 def : WriteRes<WriteFCvtI32ToF64, [SiFiveP600MulI2F]>;
 272 def : WriteRes<WriteFCvtI64ToF16, [SiFiveP600MulI2F]>;
 273 def : WriteRes<WriteFCvtI64ToF32, [SiFiveP600MulI2F]>;
 274 def : WriteRes<WriteFCvtI64ToF64, [SiFiveP600MulI2F]>;
 275 def : WriteRes<WriteFCvtF16ToI32, [SiFiveP600F2I]>;
 276 def : WriteRes<WriteFCvtF16ToI64, [SiFiveP600F2I]>;
 277 def : WriteRes<WriteFCvtF16ToF32, [SiFiveP600FloatArith]>;
 278 def : WriteRes<WriteFCvtF16ToF64, [SiFiveP600FloatArith]>;
 279 def : WriteRes<WriteFCvtF32ToI32, [SiFiveP600F2I]>;
 280 def : WriteRes<WriteFCvtF32ToI64, [SiFiveP600F2I]>;
 281 def : WriteRes<WriteFCvtF32ToF16, [SiFiveP600FloatArith]>;
 282 def : WriteRes<WriteFCvtF32ToF64, [SiFiveP600FloatArith]>;
 283 def : WriteRes<WriteFCvtF64ToI32, [SiFiveP600F2I]>;
 284 def : WriteRes<WriteFCvtF64ToI64, [SiFiveP600F2I]>;
 285 def : WriteRes<WriteFCvtF64ToF16, [SiFiveP600FloatArith]>;
 286 def : WriteRes<WriteFCvtF64ToF32, [SiFiveP600FloatArith]>;
 287
 288 def : WriteRes<WriteFClass16, [SiFiveP600F2I]>;
 289 def : WriteRes<WriteFClass32, [SiFiveP600F2I]>;
 290 def : WriteRes<WriteFClass64, [SiFiveP600F2I]>;
 291 def : WriteRes<WriteFCmp16, [SiFiveP600F2I]>;
 292 def : WriteRes<WriteFCmp32, [SiFiveP600F2I]>;
 293 def : WriteRes<WriteFCmp64, [SiFiveP600F2I]>;
 294 def : WriteRes<WriteFMovI16ToF16, [SiFiveP600MulI2F]>;
 295 def : WriteRes<WriteFMovF16ToI16, [SiFiveP600F2I]>;
 296 def : WriteRes<WriteFMovI32ToF32, [SiFiveP600MulI2F]>;
 297 def : WriteRes<WriteFMovF32ToI32, [SiFiveP600F2I]>;
 298 def : WriteRes<WriteFMovI64ToF64, [SiFiveP600MulI2F]>;
 299 def : WriteRes<WriteFMovF64ToI64, [SiFiveP600F2I]>;
 300 }
 301
 302 // 6. Configuration-Setting Instructions
 303 def : WriteRes<WriteVSETVLI, [SiFiveP600SYS]>;
 304 def : WriteRes<WriteVSETIVLI, [SiFiveP600SYS]>;
 305 def : WriteRes<WriteVSETVL, [SiFiveP600SYS]>;
 306
 307 // 7. Vector Loads and Stores
 308 // FIXME: This unit is still being improved, currently
 309 // it is based on stage numbers. Estimates are optimistic,
 310 // latency may be longer.
 311 foreach mx = SchedMxList in {
 312   defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
 313   defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
 314   let Latency = 8, ReleaseAtCycles = [LMulLat] in {
 315     defm "" : LMULWriteResMX<"WriteVLDE",    [SiFiveP600VLD], mx, IsWorstCase>;
 316     defm "" : LMULWriteResMX<"WriteVLDM",    [SiFiveP600VLD], mx, IsWorstCase>;
 317     defm "" : LMULWriteResMX<"WriteVLDFF",   [SiFiveP600VLD], mx, IsWorstCase>;
 318   }
 319   let Latency = 12, ReleaseAtCycles = [LMulLat] in {
 320     defm "" : LMULWriteResMX<"WriteVLDS8",   [SiFiveP600VLD], mx, IsWorstCase>;
 321     defm "" : LMULWriteResMX<"WriteVLDS16",  [SiFiveP600VLD], mx, IsWorstCase>;
 322     defm "" : LMULWriteResMX<"WriteVLDS32",  [SiFiveP600VLD], mx, IsWorstCase>;
 323     defm "" : LMULWriteResMX<"WriteVLDS64",  [SiFiveP600VLD], mx, IsWorstCase>;
 324   }
 325   let Latency = 12, ReleaseAtCycles = [LMulLat] in {
 326     defm "" : LMULWriteResMX<"WriteVLDUX8",  [SiFiveP600VLD], mx, IsWorstCase>;
 327     defm "" : LMULWriteResMX<"WriteVLDUX16", [SiFiveP600VLD], mx, IsWorstCase>;
 328     defm "" : LMULWriteResMX<"WriteVLDUX32", [SiFiveP600VLD], mx, IsWorstCase>;
 329     defm "" : LMULWriteResMX<"WriteVLDUX64", [SiFiveP600VLD], mx, IsWorstCase>;
 330     defm "" : LMULWriteResMX<"WriteVLDOX8",  [SiFiveP600VLD], mx, IsWorstCase>;
 331     defm "" : LMULWriteResMX<"WriteVLDOX16", [SiFiveP600VLD], mx, IsWorstCase>;
 332     defm "" : LMULWriteResMX<"WriteVLDOX32", [SiFiveP600VLD], mx, IsWorstCase>;
 333     defm "" : LMULWriteResMX<"WriteVLDOX64", [SiFiveP600VLD], mx, IsWorstCase>;
 334   }
 335 }
 336
 337 foreach mx = SchedMxList in {
 338   defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
 339   defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
 340   let Latency = 8, ReleaseAtCycles = [LMulLat] in {
 341     defm "" : LMULWriteResMX<"WriteVSTE",    [SiFiveP600VST], mx, IsWorstCase>;
 342     defm "" : LMULWriteResMX<"WriteVSTM",    [SiFiveP600VST], mx, IsWorstCase>;
 343   }
 344   let Latency = 12, ReleaseAtCycles = [LMulLat] in {
 345     defm "" : LMULWriteResMX<"WriteVSTS8",   [SiFiveP600VST], mx, IsWorstCase>;
 346     defm "" : LMULWriteResMX<"WriteVSTS16",  [SiFiveP600VST], mx, IsWorstCase>;
 347     defm "" : LMULWriteResMX<"WriteVSTS32",  [SiFiveP600VST], mx, IsWorstCase>;
 348     defm "" : LMULWriteResMX<"WriteVSTS64",  [SiFiveP600VST], mx, IsWorstCase>;
 349   }
 350   let Latency = 12, ReleaseAtCycles = [LMulLat] in {
 351     defm "" : LMULWriteResMX<"WriteVSTUX8",  [SiFiveP600VST], mx, IsWorstCase>;
 352     defm "" : LMULWriteResMX<"WriteVSTUX16", [SiFiveP600VST], mx, IsWorstCase>;
 353     defm "" : LMULWriteResMX<"WriteVSTUX32", [SiFiveP600VST], mx, IsWorstCase>;
 354     defm "" : LMULWriteResMX<"WriteVSTUX64", [SiFiveP600VST], mx, IsWorstCase>;
 355     defm "" : LMULWriteResMX<"WriteVSTOX8",  [SiFiveP600VST], mx, IsWorstCase>;
 356     defm "" : LMULWriteResMX<"WriteVSTOX16", [SiFiveP600VST], mx, IsWorstCase>;
 357     defm "" : LMULWriteResMX<"WriteVSTOX32", [SiFiveP600VST], mx, IsWorstCase>;
 358     defm "" : LMULWriteResMX<"WriteVSTOX64", [SiFiveP600VST], mx, IsWorstCase>;
 359   }
 360 }
 361
 362 foreach mx = SchedMxList in {
 363   foreach nf=2-8 in {
 364     foreach eew = [8, 16, 32, 64] in {
 365       defvar LMulLat = SiFiveP600GetCyclesSegmented<mx, eew, nf>.c;
 366       defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
 367       let Latency = !add(12, LMulLat), ReleaseAtCycles = [!add(12, LMulLat)] in {
 368         defm "" : LMULWriteResMX<"WriteVLSEG" # nf # "e" # eew,   [SiFiveP600VLD], mx, IsWorstCase>;
 369         defm "" : LMULWriteResMX<"WriteVLSEGFF" # nf # "e" # eew, [SiFiveP600VLD], mx, IsWorstCase>;
 370         defm "" : LMULWriteResMX<"WriteVLSSEG" # nf # "e" # eew,  [SiFiveP600VLD], mx, IsWorstCase>;
 371         defm "" : LMULWriteResMX<"WriteVLUXSEG" # nf # "e" # eew, [SiFiveP600VLD], mx, IsWorstCase>;
 372         defm "" : LMULWriteResMX<"WriteVLOXSEG" # nf # "e" # eew, [SiFiveP600VLD], mx, IsWorstCase>;
 373       }
 374       let Latency = !add(1, LMulLat), ReleaseAtCycles = [!add(12, LMulLat)] in {
 375         defm "" : LMULWriteResMX<"WriteVSSEG" # nf # "e" # eew,   [SiFiveP600VST], mx, IsWorstCase>;
 376         defm "" : LMULWriteResMX<"WriteVSSSEG" # nf # "e" # eew,  [SiFiveP600VST], mx, IsWorstCase>;
 377         defm "" : LMULWriteResMX<"WriteVSUXSEG" # nf # "e" # eew, [SiFiveP600VST], mx, IsWorstCase>;
 378         defm "" : LMULWriteResMX<"WriteVSOXSEG" # nf # "e" # eew, [SiFiveP600VST], mx, IsWorstCase>;
 379       }
 380     }
 381   }
 382 }
 383
 384 // Whole register move/load/store
 385 foreach LMul = [1, 2, 4, 8] in {
 386   let Latency = 8, ReleaseAtCycles = [LMul] in {
 387     def : WriteRes<!cast<SchedWrite>("WriteVLD" # LMul # "R"), [SiFiveP600VLD]>;
 388     def : WriteRes<!cast<SchedWrite>("WriteVST" # LMul # "R"), [SiFiveP600VST]>;
 389   }
 390   let Latency = LMul, ReleaseAtCycles = [LMul] in {
 391     def : WriteRes<!cast<SchedWrite>("WriteVMov" # LMul # "V"), [SiFiveP600VectorArith]>;
 392   }
 393 }
 394
 395 // 11. Vector Integer Arithmetic Instructions
 396 foreach mx = SchedMxList in {
 397   defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
 398   defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
 399   let Latency = 1, ReleaseAtCycles = [LMulLat] in {
 400     defm "" : LMULWriteResMX<"WriteVIALUV",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 401     defm "" : LMULWriteResMX<"WriteVIALUX",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 402     defm "" : LMULWriteResMX<"WriteVIALUI",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 403     defm "" : LMULWriteResMX<"WriteVExtV",    [SiFiveP600VectorArith], mx, IsWorstCase>;
 404     defm "" : LMULWriteResMX<"WriteVICALUV",  [SiFiveP600VectorArith], mx, IsWorstCase>;
 405     defm "" : LMULWriteResMX<"WriteVICALUX",  [SiFiveP600VectorArith], mx, IsWorstCase>;
 406     defm "" : LMULWriteResMX<"WriteVICALUI",  [SiFiveP600VectorArith], mx, IsWorstCase>;
 407     defm "" : LMULWriteResMX<"WriteVICmpV",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 408     defm "" : LMULWriteResMX<"WriteVICmpX",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 409     defm "" : LMULWriteResMX<"WriteVICmpI",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 410     defm "" : LMULWriteResMX<"WriteVIMergeV", [SiFiveP600VectorArith], mx, IsWorstCase>;
 411     defm "" : LMULWriteResMX<"WriteVIMergeX", [SiFiveP600VectorArith], mx, IsWorstCase>;
 412     defm "" : LMULWriteResMX<"WriteVIMergeI", [SiFiveP600VectorArith], mx, IsWorstCase>;
 413     defm "" : LMULWriteResMX<"WriteVIMovV",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 414     defm "" : LMULWriteResMX<"WriteVIMovX",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 415     defm "" : LMULWriteResMX<"WriteVIMovI",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 416   }
 417   let Latency = 6, ReleaseAtCycles = [LMulLat] in {
 418     defm "" : LMULWriteResMX<"WriteVShiftV",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 419     defm "" : LMULWriteResMX<"WriteVShiftX",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 420     defm "" : LMULWriteResMX<"WriteVShiftI",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 421     defm "" : LMULWriteResMX<"WriteVIMinMaxV", [SiFiveP600VectorArith], mx, IsWorstCase>;
 422     defm "" : LMULWriteResMX<"WriteVIMinMaxX", [SiFiveP600VectorArith], mx, IsWorstCase>;
 423     defm "" : LMULWriteResMX<"WriteVIMulV",    [SiFiveP600VectorArith], mx, IsWorstCase>;
 424     defm "" : LMULWriteResMX<"WriteVIMulX",    [SiFiveP600VectorArith], mx, IsWorstCase>;
 425     defm "" : LMULWriteResMX<"WriteVIMulAddV", [SiFiveP600VectorArith], mx, IsWorstCase>;
 426     defm "" : LMULWriteResMX<"WriteVIMulAddX", [SiFiveP600VectorArith], mx, IsWorstCase>;
 427   }
 428 }
 429 // Widening
 430 foreach mx = SchedMxListW in {
 431   defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
 432   defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxListW>.c;
 433   let Latency = 6, ReleaseAtCycles = [LMulLat] in {
 434     defm "" : LMULWriteResMX<"WriteVIWALUV",    [SiFiveP600VectorArith], mx, IsWorstCase>;
 435     defm "" : LMULWriteResMX<"WriteVIWALUX",    [SiFiveP600VectorArith], mx, IsWorstCase>;
 436     defm "" : LMULWriteResMX<"WriteVIWALUI",    [SiFiveP600VectorArith], mx, IsWorstCase>;
 437     defm "" : LMULWriteResMX<"WriteVIWMulV",    [SiFiveP600VectorArith], mx, IsWorstCase>;
 438     defm "" : LMULWriteResMX<"WriteVIWMulX",    [SiFiveP600VectorArith], mx, IsWorstCase>;
 439     defm "" : LMULWriteResMX<"WriteVIWMulAddV", [SiFiveP600VectorArith], mx, IsWorstCase>;
 440     defm "" : LMULWriteResMX<"WriteVIWMulAddX", [SiFiveP600VectorArith], mx, IsWorstCase>;
 441   }
 442 }
 443
 444 // Worst case needs 64 cycles if SEW is equal to 64.
 445 foreach mx = SchedMxList in {
 446   foreach sew = SchedSEWSet<mx>.val in {
 447     defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
 448     defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
 449     let Latency = 64, ReleaseAtCycles = [LMulLat, !mul(63, LMulLat)] in {
 450       defm "" : LMULSEWWriteResMXSEW<"WriteVIDivV", [SiFiveP600VEXQ1, SiFiveP600VDiv], mx, sew, IsWorstCase>;
 451       defm "" : LMULSEWWriteResMXSEW<"WriteVIDivX", [SiFiveP600VEXQ1, SiFiveP600VDiv], mx, sew, IsWorstCase>;
 452     }
 453   }
 454 }
 455
 456 // Narrowing Shift and Clips
 457 foreach mx = SchedMxListW in {
 458   defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
 459   defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxListW>.c;
 460   let Latency = 2, ReleaseAtCycles = [LMulLat] in {
 461     defm "" : LMULWriteResMX<"WriteVNShiftV", [SiFiveP600VectorArith], mx, IsWorstCase>;
 462     defm "" : LMULWriteResMX<"WriteVNShiftX", [SiFiveP600VectorArith], mx, IsWorstCase>;
 463     defm "" : LMULWriteResMX<"WriteVNShiftI", [SiFiveP600VectorArith], mx, IsWorstCase>;
 464     defm "" : LMULWriteResMX<"WriteVNClipV",  [SiFiveP600VectorArith], mx, IsWorstCase>;
 465     defm "" : LMULWriteResMX<"WriteVNClipX",  [SiFiveP600VectorArith], mx, IsWorstCase>;
 466     defm "" : LMULWriteResMX<"WriteVNClipI",  [SiFiveP600VectorArith], mx, IsWorstCase>;
 467   }
 468 }
 469
 470 // 12. Vector Fixed-Point Arithmetic Instructions
 471 foreach mx = SchedMxList in {
 472   defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
 473   defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
 474   let Latency = 6, ReleaseAtCycles = [LMulLat] in {
 475     defm "" : LMULWriteResMX<"WriteVSALUV",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 476     defm "" : LMULWriteResMX<"WriteVSALUX",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 477     defm "" : LMULWriteResMX<"WriteVSALUI",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 478     defm "" : LMULWriteResMX<"WriteVAALUV",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 479     defm "" : LMULWriteResMX<"WriteVAALUX",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 480     defm "" : LMULWriteResMX<"WriteVSMulV",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 481     defm "" : LMULWriteResMX<"WriteVSMulX",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 482     defm "" : LMULWriteResMX<"WriteVSShiftV", [SiFiveP600VectorArith], mx, IsWorstCase>;
 483     defm "" : LMULWriteResMX<"WriteVSShiftX", [SiFiveP600VectorArith], mx, IsWorstCase>;
 484     defm "" : LMULWriteResMX<"WriteVSShiftI", [SiFiveP600VectorArith], mx, IsWorstCase>;
 485   }
 486 }
 487
 488 // 13. Vector Floating-Point Instructions
 489 foreach mx = SchedMxListF in {
 490   foreach sew = SchedSEWSet<mx, isF=1>.val in {
 491     defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
 492     defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
 493     let Latency = 6, ReleaseAtCycles = [LMulLat] in {
 494       defm "" : LMULSEWWriteResMXSEW<"WriteVFALUV",  [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
 495       defm "" : LMULSEWWriteResMXSEW<"WriteVFALUF",  [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
 496       defm "" : LMULSEWWriteResMXSEW<"WriteVFMulV",  [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
 497       defm "" : LMULSEWWriteResMXSEW<"WriteVFMulF",  [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
 498       defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
 499       defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddF", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
 500     }
 501     let Latency = 2, ReleaseAtCycles = [LMulLat] in
 502     defm "" : LMULSEWWriteResMXSEW<"WriteVFRecpV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
 503     let Latency = 3, ReleaseAtCycles = [LMulLat] in
 504     defm "" : LMULSEWWriteResMXSEW<"WriteVFCvtIToFV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
 505   }
 506 }
 507 foreach mx = SchedMxListF in {
 508   foreach sew = SchedSEWSet<mx, isF=1>.val in {
 509     defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
 510     defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxList, isF=1>.c;
 511     let Latency = 1, ReleaseAtCycles = [LMulLat] in {
 512       defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
 513       defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxF", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
 514       defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjV",   [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
 515       defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjF",   [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
 516     }
 517   }
 518 }
 519 foreach mx = SchedMxList in {
 520   defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
 521   defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
 522   let Latency = 3, ReleaseAtCycles = [LMulLat] in
 523   defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [SiFiveP600VectorArith], mx, IsWorstCase>;
 524   let Latency = 2, ReleaseAtCycles = [LMulLat] in {
 525     defm "" : LMULWriteResMX<"WriteVFCmpV",  [SiFiveP600VectorArith], mx, IsWorstCase>;
 526     defm "" : LMULWriteResMX<"WriteVFCmpF",  [SiFiveP600VectorArith], mx, IsWorstCase>;
 527   }
 528   let Latency = 1, ReleaseAtCycles = [LMulLat] in {
 529     defm "" : LMULWriteResMX<"WriteVFClassV",  [SiFiveP600VectorArith], mx, IsWorstCase>;
 530     defm "" : LMULWriteResMX<"WriteVFMergeV",  [SiFiveP600VectorArith], mx, IsWorstCase>;
 531     defm "" : LMULWriteResMX<"WriteVFMovV",    [SiFiveP600VectorArith], mx, IsWorstCase>;
 532   }
 533 }
 534
 535 // Widening
 536 foreach mx = SchedMxListW in {
 537   foreach sew = SchedSEWSet<mx, isF=0, isWidening=1>.val in {
 538     defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
 539     defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxListW>.c;
 540     let Latency = 3, ReleaseAtCycles = [LMulLat] in
 541     defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtIToFV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
 542   }
 543 }
 544 foreach mx = SchedMxListFW in {
 545   defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
 546   defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxListFW>.c;
 547   let Latency = 6, ReleaseAtCycles = [LMulLat] in
 548   defm "" : LMULWriteResMX<"WriteVFWCvtFToIV", [SiFiveP600VectorArith], mx, IsWorstCase>;
 549 }
 550 foreach mx = SchedMxListFW in {
 551   foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
 552     defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
 553     defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
 554     let Latency = 6, ReleaseAtCycles = [LMulLat] in {
 555       defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
 556       defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUF", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
 557       defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
 558       defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulF", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
 559       defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
 560       defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddF", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
 561       defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtFToFV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
 562     }
 563   }
 564 }
 565 // Narrowing
 566 foreach mx = SchedMxListW in {
 567   defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
 568   defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxListW>.c;
 569   let Latency = 3, ReleaseAtCycles = [LMulLat] in {
 570     defm "" : LMULWriteResMX<"WriteVFNCvtFToIV", [SiFiveP600VectorArith], mx, IsWorstCase>;
 571   }
 572 }
 573 foreach mx = SchedMxListFW in {
 574   foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
 575     defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
 576     defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
 577     let Latency = 3, ReleaseAtCycles = [LMulLat] in {
 578       defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtIToFV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
 579       defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtFToFV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
 580     }
 581   }
 582 }
 583
 584 // Worst case needs 76 cycles if SEW is equal to 64.
 585 foreach mx = SchedMxListF in {
 586   foreach sew = SchedSEWSet<mx, 1>.val in {
 587     defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
 588     defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
 589     let Latency = 76, ReleaseAtCycles = [LMulLat, !mul(76, LMulLat)] in {
 590       defm "" : LMULSEWWriteResMXSEW<"WriteVFDivV",  [SiFiveP600VEXQ1, SiFiveP600VFloatDiv], mx, sew, IsWorstCase>;
 591       defm "" : LMULSEWWriteResMXSEW<"WriteVFDivF",  [SiFiveP600VEXQ1, SiFiveP600VFloatDiv], mx, sew, IsWorstCase>;
 592       defm "" : LMULSEWWriteResMXSEW<"WriteVFSqrtV", [SiFiveP600VEXQ1, SiFiveP600VFloatDiv], mx, sew, IsWorstCase>;
 593     }
 594   }
 595 }
 596
 597 // 14. Vector Reduction Operations
 598 foreach mx = SchedMxList in {
 599   foreach sew = SchedSEWSet<mx>.val in {
 600     defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
 601     defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
 602     let Latency = !add(2, !mul(2, LMulLat)), ReleaseAtCycles = [LMulLat] in {
 603       defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [SiFiveP600VEXQ1],
 604                                      mx, sew, IsWorstCase>;
 605       defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [SiFiveP600VEXQ1],
 606                                      mx, sew, IsWorstCase>;
 607     }
 608   }
 609 }
 610
 611 foreach mx = SchedMxListWRed in {
 612   foreach sew = SchedSEWSet<mx, 0, 1>.val in {
 613     defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
 614     defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxListWRed>.c;
 615     let Latency = !add(2, !mul(2, LMulLat)), ReleaseAtCycles = [LMulLat] in {
 616       defm "" : LMULSEWWriteResMXSEW<"WriteVIWRedV_From", [SiFiveP600VEXQ1],
 617                                      mx, sew, IsWorstCase>;
 618     }
 619   }
 620 }
 621
 622 foreach mx = SchedMxListF in {
 623   foreach sew = SchedSEWSet<mx, 1>.val in {
 624     defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
 625     defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
 626     let Latency = !add(6, !mul(6, LMulLat)), ReleaseAtCycles = [LMulLat] in {
 627       defm "" : LMULSEWWriteResMXSEW<"WriteVFRedV_From", [SiFiveP600VEXQ1],
 628                                      mx, sew, IsWorstCase>;
 629       defm "" : LMULSEWWriteResMXSEW<"WriteVFRedMinMaxV_From",
 630                                      [SiFiveP600VEXQ1], mx, sew, IsWorstCase>;
 631       defm "" : LMULSEWWriteResMXSEW<"WriteVFRedOV_From", [SiFiveP600VEXQ1],
 632                                      mx, sew, IsWorstCase>;
 633     }
 634   }
 635 }
 636
 637 foreach mx = SchedMxListFWRed in {
 638   foreach sew = SchedSEWSet<mx, 1, 1>.val in {
 639     defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
 640     defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxListFWRed, 1>.c;
 641     let Latency = !add(6, !mul(6, LMulLat)), ReleaseAtCycles = [LMulLat] in {
 642       defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedV_From",  [SiFiveP600VEXQ1],
 643                                      mx, sew, IsWorstCase>;
 644       defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedOV_From", [SiFiveP600VEXQ1],
 645                                      mx, sew, IsWorstCase>;
 646     }
 647   }
 648 }
 649
 650 // 15. Vector Mask Instructions
 651 foreach mx = SchedMxList in {
 652   defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
 653   let Latency = 1, ReleaseAtCycles = [1] in {
 654     defm "" : LMULWriteResMX<"WriteVMALUV", [SiFiveP600VEXQ0], mx, IsWorstCase>;
 655     defm "" : LMULWriteResMX<"WriteVMPopV", [SiFiveP600VEXQ0], mx, IsWorstCase>;
 656     defm "" : LMULWriteResMX<"WriteVMFFSV", [SiFiveP600VEXQ0], mx, IsWorstCase>;
 657     defm "" : LMULWriteResMX<"WriteVMSFSV", [SiFiveP600VEXQ0], mx, IsWorstCase>;
 658   }
 659   defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
 660   let Latency = 1, ReleaseAtCycles = [LMulLat] in {
 661     defm "" : LMULWriteResMX<"WriteVIotaV", [SiFiveP600VEXQ0], mx, IsWorstCase>;
 662     defm "" : LMULWriteResMX<"WriteVIdxV", [SiFiveP600VEXQ0], mx, IsWorstCase>;
 663   }
 664 }
 665
 666 // 16. Vector Permutation Instructions
 667 // Simple Slide
 668 foreach mx = SchedMxList in {
 669   defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
 670   defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
 671   let Latency = 2, ReleaseAtCycles = [LMulLat] in {
 672     defm "" : LMULWriteResMX<"WriteVISlideI",  [SiFiveP600VEXQ0], mx, IsWorstCase>;
 673   }
 674   let Latency = 1, ReleaseAtCycles = [LMulLat] in {
 675     defm "" : LMULWriteResMX<"WriteVISlide1X", [SiFiveP600VEXQ0], mx, IsWorstCase>;
 676     defm "" : LMULWriteResMX<"WriteVFSlide1F", [SiFiveP600VEXQ0], mx, IsWorstCase>;
 677   }
 678 }
 679 foreach mx = ["MF8", "MF4", "MF2", "M1"] in {
 680   defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
 681   let Latency = 2, ReleaseAtCycles = [1] in {
 682     defm "" : LMULWriteResMX<"WriteVISlideX", [SiFiveP600VEXQ0], mx, IsWorstCase>;
 683   }
 684 }
 685
 686 // Complex Slide
 687 foreach mx = ["M8", "M4", "M2"] in {
 688   defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
 689   defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
 690   let Latency = !add(4, LMulLat), ReleaseAtCycles = [LMulLat] in {
 691     defm "" : LMULWriteResMX<"WriteVISlideX", [SiFiveP600VEXQ1], mx, IsWorstCase>;
 692   }
 693 }
 694
 695 let Latency = 2, ReleaseAtCycles = [1] in {
 696   def : WriteRes<WriteVMovSX, [SiFiveP600VectorArith]>;
 697   def : WriteRes<WriteVMovXS, [SiFiveP600VectorArith]>;
 698 }
 699 let Latency = 6, ReleaseAtCycles = [1] in {
 700   def : WriteRes<WriteVMovSF, [SiFiveP600VectorArith]>;
 701   def : WriteRes<WriteVMovFS, [SiFiveP600VectorArith]>;
 702 }
 703
 704 // Simple Gather and Compress
 705 foreach mx = ["MF8", "MF4", "MF2", "M1"] in {
 706   defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
 707   let Latency = 3, ReleaseAtCycles = [1] in {
 708     defm "" : LMULWriteResMX<"WriteVRGatherVX", [SiFiveP600VEXQ1], mx, IsWorstCase>;
 709   }
 710 }
 711
 712 foreach mx = ["MF8", "MF4", "MF2", "M1"] in {
 713   foreach sew = SchedSEWSet<mx>.val in {
 714     defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
 715     let Latency = 3, ReleaseAtCycles = [1] in {
 716       defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [SiFiveP600VEXQ1], mx, sew, IsWorstCase>;
 717       defm "" : LMULSEWWriteResMXSEW<"WriteVCompressV", [SiFiveP600VEXQ1], mx, sew, IsWorstCase>;
 718     }
 719   }
 720 }
 721
 722 // Complex Gather and Compress
 723 foreach mx = ["M2", "M4", "M8"] in {
 724   defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
 725   defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
 726   let Latency = 6, ReleaseAtCycles = [LMulLat] in {
 727     defm "" : LMULWriteResMX<"WriteVRGatherVX", [SiFiveP600VEXQ1], mx, IsWorstCase>;
 728   }
 729 }
 730
 731 foreach mx = ["M2", "M4", "M8"] in {
 732   foreach sew = SchedSEWSet<mx>.val in {
 733     defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
 734     defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
 735     let Latency = 6, ReleaseAtCycles = [LMulLat] in {
 736       defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [SiFiveP600VEXQ1], mx, sew, IsWorstCase>;
 737       defm "" : LMULSEWWriteResMXSEW<"WriteVCompressV", [SiFiveP600VEXQ1], mx, sew, IsWorstCase>;
 738     }
 739   }
 740 }
 741
 742 // Simple Vrgather.vi
 743 foreach mx = SchedMxList in {
 744   defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
 745   defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
 746   let Latency = 3, ReleaseAtCycles = [LMulLat] in {
 747     defm "" : LMULWriteResMX<"WriteVRGatherVI", [SiFiveP600VEXQ1], mx, IsWorstCase>;
 748   }
 749 }
 750
 751 // Vector Crypto
 752 foreach mx = SchedMxList in {
 753   defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
 754   defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
 755   // Zvbb
 756   let Latency = 2, ReleaseAtCycles = [LMulLat] in {
 757     defm "" : LMULWriteResMX<"WriteVBREVV",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 758     defm "" : LMULWriteResMX<"WriteVCLZV",    [SiFiveP600VectorArith], mx, IsWorstCase>;
 759     defm "" : LMULWriteResMX<"WriteVCPOPV",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 760     defm "" : LMULWriteResMX<"WriteVCTZV",    [SiFiveP600VectorArith], mx, IsWorstCase>;
 761     defm "" : LMULWriteResMX<"WriteVWSLLV",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 762     defm "" : LMULWriteResMX<"WriteVWSLLX",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 763     defm "" : LMULWriteResMX<"WriteVWSLLI",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 764   }
 765   // Zvbc
 766   let Latency = 2, ReleaseAtCycles = [LMulLat] in {
 767     defm "" : LMULWriteResMX<"WriteVCLMULV", [SiFiveP600VectorArith], mx, IsWorstCase>;
 768     defm "" : LMULWriteResMX<"WriteVCLMULX", [SiFiveP600VectorArith], mx, IsWorstCase>;
 769   }
 770   // Zvkb
 771   // VANDN uses WriteVIALU[V|X|I]
 772   let Latency = 2, ReleaseAtCycles = [LMulLat] in {
 773     defm "" : LMULWriteResMX<"WriteVBREV8V",  [SiFiveP600VectorArith], mx, IsWorstCase>;
 774     defm "" : LMULWriteResMX<"WriteVREV8V",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 775     defm "" : LMULWriteResMX<"WriteVRotV",    [SiFiveP600VectorArith], mx, IsWorstCase>;
 776     defm "" : LMULWriteResMX<"WriteVRotX",    [SiFiveP600VectorArith], mx, IsWorstCase>;
 777     defm "" : LMULWriteResMX<"WriteVRotI",    [SiFiveP600VectorArith], mx, IsWorstCase>;
 778   }
 779   // Zvkg
 780   let Latency = 2, ReleaseAtCycles = [LMulLat] in {
 781     defm "" : LMULWriteResMX<"WriteVGHSHV",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 782     defm "" : LMULWriteResMX<"WriteVGMULV",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 783   }
 784   // ZvknhaOrZvknhb
 785   let Latency = 3, ReleaseAtCycles = [LMulLat] in {
 786     defm "" : LMULWriteResMX<"WriteVSHA2CHV", [SiFiveP600VectorArith], mx, IsWorstCase>;
 787     defm "" : LMULWriteResMX<"WriteVSHA2CLV", [SiFiveP600VectorArith], mx, IsWorstCase>;
 788     defm "" : LMULWriteResMX<"WriteVSHA2MSV", [SiFiveP600VectorArith], mx, IsWorstCase>;
 789   }
 790   // Zvkned
 791   let Latency = 2, ReleaseAtCycles = [LMulLat] in {
 792     defm "" : LMULWriteResMX<"WriteVAESMVV",  [SiFiveP600VectorArith], mx, IsWorstCase>;
 793     defm "" : LMULWriteResMX<"WriteVAESKF1V", [SiFiveP600VectorArith], mx, IsWorstCase>;
 794     defm "" : LMULWriteResMX<"WriteVAESKF2V", [SiFiveP600VectorArith], mx, IsWorstCase>;
 795   }
 796   let Latency = 1, ReleaseAtCycles = [LMulLat] in
 797   defm "" : LMULWriteResMX<"WriteVAESZV",   [SiFiveP600VectorArith], mx, IsWorstCase>;
 798   // Zvksed
 799   let Latency = 3, ReleaseAtCycles = [LMulLat] in {
 800     defm "" : LMULWriteResMX<"WriteVSM4KV",   [SiFiveP600VEXQ0], mx, IsWorstCase>;
 801     defm "" : LMULWriteResMX<"WriteVSM4RV",   [SiFiveP600VEXQ0], mx, IsWorstCase>;
 802     defm "" : LMULWriteResMX<"WriteVSM3CV",   [SiFiveP600VEXQ0], mx, IsWorstCase>;
 803     defm "" : LMULWriteResMX<"WriteVSM3MEV",  [SiFiveP600VEXQ0], mx, IsWorstCase>;
 804   }
 805 }
 806
 807 // Others
 808 def : WriteRes<WriteCSR, [SiFiveP600SYS]>;
 809 def : WriteRes<WriteNop, []>;
 810 def : WriteRes<WriteRdVLENB, [SiFiveP600SYS]>;
 811
 812 // FIXME: This could be better modeled by looking at the regclasses of the operands.
 813 def : InstRW<[WriteIALU, ReadIALU], (instrs COPY)>;
 814
 815 //===----------------------------------------------------------------------===//
 816 // Bypass and advance
 817 def : ReadAdvance<ReadJmp, 0>;
 818 def : ReadAdvance<ReadJalr, 0>;
 819 def : ReadAdvance<ReadCSR, 0>;
 820 def : ReadAdvance<ReadStoreData, 0>;
 821 def : ReadAdvance<ReadMemBase, 0>;
 822 def : ReadAdvance<ReadIALU, 0>;
 823 def : ReadAdvance<ReadIALU32, 0>;
 824 def : ReadAdvance<ReadShiftImm, 0>;
 825 def : ReadAdvance<ReadShiftImm32, 0>;
 826 def : ReadAdvance<ReadShiftReg, 0>;
 827 def : ReadAdvance<ReadShiftReg32, 0>;
 828 def : ReadAdvance<ReadIDiv, 0>;
 829 def : ReadAdvance<ReadIDiv32, 0>;
 830 def : ReadAdvance<ReadIRem, 0>;
 831 def : ReadAdvance<ReadIRem32, 0>;
 832 def : ReadAdvance<ReadIMul, 0>;
 833 def : ReadAdvance<ReadIMul32, 0>;
 834 def : ReadAdvance<ReadAtomicWA, 0>;
 835 def : ReadAdvance<ReadAtomicWD, 0>;
 836 def : ReadAdvance<ReadAtomicDA, 0>;
 837 def : ReadAdvance<ReadAtomicDD, 0>;
 838 def : ReadAdvance<ReadAtomicLDW, 0>;
 839 def : ReadAdvance<ReadAtomicLDD, 0>;
 840 def : ReadAdvance<ReadAtomicSTW, 0>;
 841 def : ReadAdvance<ReadAtomicSTD, 0>;
 842 def : ReadAdvance<ReadFStoreData, 0>;
 843 def : ReadAdvance<ReadFMemBase, 0>;
 844 def : ReadAdvance<ReadFAdd16, 0>;
 845 def : ReadAdvance<ReadFAdd32, 0>;
 846 def : ReadAdvance<ReadFAdd64, 0>;
 847 def : ReadAdvance<ReadFMul16, 0>;
 848 def : ReadAdvance<ReadFMA16, 0>;
 849 def : ReadAdvance<ReadFMA16Addend, 0>;
 850 def : ReadAdvance<ReadFMul32, 0>;
 851 def : ReadAdvance<ReadFMA32, 0>;
 852 def : ReadAdvance<ReadFMA32Addend, 0>;
 853 def : ReadAdvance<ReadFMul64, 0>;
 854 def : ReadAdvance<ReadFMA64, 0>;
 855 def : ReadAdvance<ReadFMA64Addend, 0>;
 856 def : ReadAdvance<ReadFDiv16, 0>;
 857 def : ReadAdvance<ReadFDiv32, 0>;
 858 def : ReadAdvance<ReadFDiv64, 0>;
 859 def : ReadAdvance<ReadFSqrt16, 0>;
 860 def : ReadAdvance<ReadFSqrt32, 0>;
 861 def : ReadAdvance<ReadFSqrt64, 0>;
 862 def : ReadAdvance<ReadFCmp16, 0>;
 863 def : ReadAdvance<ReadFCmp32, 0>;
 864 def : ReadAdvance<ReadFCmp64, 0>;
 865 def : ReadAdvance<ReadFSGNJ16, 0>;
 866 def : ReadAdvance<ReadFSGNJ32, 0>;
 867 def : ReadAdvance<ReadFSGNJ64, 0>;
 868 def : ReadAdvance<ReadFMinMax16, 0>;
 869 def : ReadAdvance<ReadFMinMax32, 0>;
 870 def : ReadAdvance<ReadFMinMax64, 0>;
 871 def : ReadAdvance<ReadFCvtF16ToI32, 0>;
 872 def : ReadAdvance<ReadFCvtF16ToI64, 0>;
 873 def : ReadAdvance<ReadFCvtF32ToI32, 0>;
 874 def : ReadAdvance<ReadFCvtF32ToI64, 0>;
 875 def : ReadAdvance<ReadFCvtF64ToI32, 0>;
 876 def : ReadAdvance<ReadFCvtF64ToI64, 0>;
 877 def : ReadAdvance<ReadFCvtI32ToF16, 0>;
 878 def : ReadAdvance<ReadFCvtI32ToF32, 0>;
 879 def : ReadAdvance<ReadFCvtI32ToF64, 0>;
 880 def : ReadAdvance<ReadFCvtI64ToF16, 0>;
 881 def : ReadAdvance<ReadFCvtI64ToF32, 0>;
 882 def : ReadAdvance<ReadFCvtI64ToF64, 0>;
 883 def : ReadAdvance<ReadFCvtF32ToF64, 0>;
 884 def : ReadAdvance<ReadFCvtF64ToF32, 0>;
 885 def : ReadAdvance<ReadFCvtF16ToF32, 0>;
 886 def : ReadAdvance<ReadFCvtF32ToF16, 0>;
 887 def : ReadAdvance<ReadFCvtF16ToF64, 0>;
 888 def : ReadAdvance<ReadFCvtF64ToF16, 0>;
 889 def : ReadAdvance<ReadFMovF16ToI16, 0>;
 890 def : ReadAdvance<ReadFMovI16ToF16, 0>;
 891 def : ReadAdvance<ReadFMovF32ToI32, 0>;
 892 def : ReadAdvance<ReadFMovI32ToF32, 0>;
 893 def : ReadAdvance<ReadFMovF64ToI64, 0>;
 894 def : ReadAdvance<ReadFMovI64ToF64, 0>;
 895 def : ReadAdvance<ReadFClass16, 0>;
 896 def : ReadAdvance<ReadFClass32, 0>;
 897 def : ReadAdvance<ReadFClass64, 0>;
 898
 899 // Bitmanip
 900 def : ReadAdvance<ReadRotateImm, 0>;
 901 def : ReadAdvance<ReadRotateImm32, 0>;
 902 def : ReadAdvance<ReadRotateReg, 0>;
 903 def : ReadAdvance<ReadRotateReg32, 0>;
 904 def : ReadAdvance<ReadCLZ, 0>;
 905 def : ReadAdvance<ReadCLZ32, 0>;
 906 def : ReadAdvance<ReadCTZ, 0>;
 907 def : ReadAdvance<ReadCTZ32, 0>;
 908 def : ReadAdvance<ReadCPOP, 0>;
 909 def : ReadAdvance<ReadCPOP32, 0>;
 910 def : ReadAdvance<ReadORCB, 0>;
 911 def : ReadAdvance<ReadIMinMax, 0>;
 912 def : ReadAdvance<ReadREV8, 0>;
 913 def : ReadAdvance<ReadSHXADD, 0>;
 914 def : ReadAdvance<ReadSHXADD32, 0>;
 915 def : ReadAdvance<ReadSingleBit, 0>;
 916 def : ReadAdvance<ReadSingleBitImm, 0>;
 917
 918 // 6. Configuration-Setting Instructions
 919 def : ReadAdvance<ReadVSETVLI, 0>;
 920 def : ReadAdvance<ReadVSETVL, 0>;
 921
 922 // 7. Vector Loads and Stores
 923 def : ReadAdvance<ReadVLDX, 0>;
 924 def : ReadAdvance<ReadVSTX, 0>;
 925 defm "" : LMULReadAdvance<"ReadVSTEV", 0>;
 926 defm "" : LMULReadAdvance<"ReadVSTM", 0>;
 927 def : ReadAdvance<ReadVLDSX, 0>;
 928 def : ReadAdvance<ReadVSTSX, 0>;
 929 defm "" : LMULReadAdvance<"ReadVSTS8V", 0>;
 930 defm "" : LMULReadAdvance<"ReadVSTS16V", 0>;
 931 defm "" : LMULReadAdvance<"ReadVSTS32V", 0>;
 932 defm "" : LMULReadAdvance<"ReadVSTS64V", 0>;
 933 defm "" : LMULReadAdvance<"ReadVLDUXV", 0>;
 934 defm "" : LMULReadAdvance<"ReadVLDOXV", 0>;
 935 defm "" : LMULReadAdvance<"ReadVSTUX8", 0>;
 936 defm "" : LMULReadAdvance<"ReadVSTUX16", 0>;
 937 defm "" : LMULReadAdvance<"ReadVSTUX32", 0>;
 938 defm "" : LMULReadAdvance<"ReadVSTUX64", 0>;
 939 defm "" : LMULReadAdvance<"ReadVSTUXV", 0>;
 940 defm "" : LMULReadAdvance<"ReadVSTUX8V", 0>;
 941 defm "" : LMULReadAdvance<"ReadVSTUX16V", 0>;
 942 defm "" : LMULReadAdvance<"ReadVSTUX32V", 0>;
 943 defm "" : LMULReadAdvance<"ReadVSTUX64V", 0>;
 944 defm "" : LMULReadAdvance<"ReadVSTOX8", 0>;
 945 defm "" : LMULReadAdvance<"ReadVSTOX16", 0>;
 946 defm "" : LMULReadAdvance<"ReadVSTOX32", 0>;
 947 defm "" : LMULReadAdvance<"ReadVSTOX64", 0>;
 948 defm "" : LMULReadAdvance<"ReadVSTOXV", 0>;
 949 defm "" : LMULReadAdvance<"ReadVSTOX8V", 0>;
 950 defm "" : LMULReadAdvance<"ReadVSTOX16V", 0>;
 951 defm "" : LMULReadAdvance<"ReadVSTOX32V", 0>;
 952 defm "" : LMULReadAdvance<"ReadVSTOX64V", 0>;
 953 // LMUL Aware
 954 def : ReadAdvance<ReadVST1R, 0>;
 955 def : ReadAdvance<ReadVST2R, 0>;
 956 def : ReadAdvance<ReadVST4R, 0>;
 957 def : ReadAdvance<ReadVST8R, 0>;
 958
 959 // 12. Vector Integer Arithmetic Instructions
 960 defm : LMULReadAdvance<"ReadVIALUV", 0>;
 961 defm : LMULReadAdvance<"ReadVIALUX", 0>;
 962 defm : LMULReadAdvanceW<"ReadVIWALUV", 0>;
 963 defm : LMULReadAdvanceW<"ReadVIWALUX", 0>;
 964 defm : LMULReadAdvance<"ReadVExtV", 0>;
 965 defm : LMULReadAdvance<"ReadVICALUV", 0>;
 966 defm : LMULReadAdvance<"ReadVICALUX", 0>;
 967 defm : LMULReadAdvance<"ReadVShiftV", 0>;
 968 defm : LMULReadAdvance<"ReadVShiftX", 0>;
 969 defm : LMULReadAdvanceW<"ReadVNShiftV", 0>;
 970 defm : LMULReadAdvanceW<"ReadVNShiftX", 0>;
 971 defm : LMULReadAdvance<"ReadVICmpV", 0>;
 972 defm : LMULReadAdvance<"ReadVICmpX", 0>;
 973 defm : LMULReadAdvance<"ReadVIMinMaxV", 0>;
 974 defm : LMULReadAdvance<"ReadVIMinMaxX", 0>;
 975 defm : LMULReadAdvance<"ReadVIMulV", 0>;
 976 defm : LMULReadAdvance<"ReadVIMulX", 0>;
 977 defm : LMULSEWReadAdvance<"ReadVIDivV", 0>;
 978 defm : LMULSEWReadAdvance<"ReadVIDivX", 0>;
 979 defm : LMULReadAdvanceW<"ReadVIWMulV", 0>;
 980 defm : LMULReadAdvanceW<"ReadVIWMulX", 0>;
 981 defm : LMULReadAdvance<"ReadVIMulAddV", 0>;
 982 defm : LMULReadAdvance<"ReadVIMulAddX", 0>;
 983 defm : LMULReadAdvanceW<"ReadVIWMulAddV", 0>;
 984 defm : LMULReadAdvanceW<"ReadVIWMulAddX", 0>;
 985 defm : LMULReadAdvance<"ReadVIMergeV", 0>;
 986 defm : LMULReadAdvance<"ReadVIMergeX", 0>;
 987 defm : LMULReadAdvance<"ReadVIMovV", 0>;
 988 defm : LMULReadAdvance<"ReadVIMovX", 0>;
 989
 990 // 13. Vector Fixed-Point Arithmetic Instructions
 991 defm "" : LMULReadAdvance<"ReadVSALUV", 0>;
 992 defm "" : LMULReadAdvance<"ReadVSALUX", 0>;
 993 defm "" : LMULReadAdvance<"ReadVAALUV", 0>;
 994 defm "" : LMULReadAdvance<"ReadVAALUX", 0>;
 995 defm "" : LMULReadAdvance<"ReadVSMulV", 0>;
 996 defm "" : LMULReadAdvance<"ReadVSMulX", 0>;
 997 defm "" : LMULReadAdvance<"ReadVSShiftV", 0>;
 998 defm "" : LMULReadAdvance<"ReadVSShiftX", 0>;
 999 defm "" : LMULReadAdvanceW<"ReadVNClipV", 0>;
1000 defm "" : LMULReadAdvanceW<"ReadVNClipX", 0>;
1001
1002 // 14. Vector Floating-Point Instructions
1003 defm "" : LMULSEWReadAdvanceF<"ReadVFALUV", 0>;
1004 defm "" : LMULSEWReadAdvanceF<"ReadVFALUF", 0>;
1005 defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUV", 0>;
1006 defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUF", 0>;
1007 defm "" : LMULSEWReadAdvanceF<"ReadVFMulV", 0>;
1008 defm "" : LMULSEWReadAdvanceF<"ReadVFMulF", 0>;
1009 defm "" : LMULSEWReadAdvanceF<"ReadVFDivV", 0>;
1010 defm "" : LMULSEWReadAdvanceF<"ReadVFDivF", 0>;
1011 defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulV", 0>;
1012 defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulF", 0>;
1013 defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddV", 0>;
1014 defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddF", 0>;
1015 defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddV", 0>;
1016 defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddF", 0>;
1017 defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>;
1018 defm "" : LMULSEWReadAdvance<"ReadVFRecpV", 0>;
1019 defm "" : LMULReadAdvance<"ReadVFCmpV", 0>;
1020 defm "" : LMULReadAdvance<"ReadVFCmpF", 0>;
1021 defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxV", 0>;
1022 defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxF", 0>;
1023 defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjV", 0>;
1024 defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjF", 0>;
1025 defm "" : LMULReadAdvance<"ReadVFClassV", 0>;
1026 defm "" : LMULReadAdvance<"ReadVFMergeV", 0>;
1027 defm "" : LMULReadAdvance<"ReadVFMergeF", 0>;
1028 defm "" : LMULReadAdvance<"ReadVFMovF", 0>;
1029 defm "" : LMULSEWReadAdvanceF<"ReadVFCvtIToFV", 0>;
1030 defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;
1031 defm "" : LMULSEWReadAdvanceW<"ReadVFWCvtIToFV", 0>;
1032 defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;
1033 defm "" : LMULSEWReadAdvanceFW<"ReadVFWCvtFToFV", 0>;
1034 defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtIToFV", 0>;
1035 defm "" : LMULReadAdvanceW<"ReadVFNCvtFToIV", 0>;
1036 defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtFToFV", 0>;
1037
1038 // 15. Vector Reduction Operations
1039 def : ReadAdvance<ReadVIRedV, 0>;
1040 def : ReadAdvance<ReadVIRedV0, 0>;
1041 def : ReadAdvance<ReadVIWRedV, 0>;
1042 def : ReadAdvance<ReadVIWRedV0, 0>;
1043 def : ReadAdvance<ReadVFRedV, 0>;
1044 def : ReadAdvance<ReadVFRedV0, 0>;
1045 def : ReadAdvance<ReadVFRedOV, 0>;
1046 def : ReadAdvance<ReadVFRedOV0, 0>;
1047 def : ReadAdvance<ReadVFWRedV, 0>;
1048 def : ReadAdvance<ReadVFWRedV0, 0>;
1049 def : ReadAdvance<ReadVFWRedOV, 0>;
1050 def : ReadAdvance<ReadVFWRedOV0, 0>;
1051
1052 // 16. Vector Mask Instructions
1053 defm "" : LMULReadAdvance<"ReadVMALUV", 0>;
1054 defm "" : LMULReadAdvance<"ReadVMPopV", 0>;
1055 defm "" : LMULReadAdvance<"ReadVMFFSV", 0>;
1056 defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;
1057 defm "" : LMULReadAdvance<"ReadVIotaV", 0>;
1058
1059 // 17. Vector Permutation Instructions
1060 def : ReadAdvance<ReadVMovXS, 0>;
1061 def : ReadAdvance<ReadVMovSX_V, 0>;
1062 def : ReadAdvance<ReadVMovSX_X, 0>;
1063 def : ReadAdvance<ReadVMovFS, 0>;
1064 def : ReadAdvance<ReadVMovSF_V, 0>;
1065 def : ReadAdvance<ReadVMovSF_F, 0>;
1066 defm "" : LMULReadAdvance<"ReadVISlideV", 0>;
1067 defm "" : LMULReadAdvance<"ReadVISlideX", 0>;
1068 defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;
1069 defm "" : LMULReadAdvance<"ReadVFSlideF", 0>;
1070 defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>;
1071 defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>;
1072 defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>;
1073 defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>;
1074 defm "" : LMULReadAdvance<"ReadVRGatherVI_data", 0>;
1075 defm "" : LMULSEWReadAdvance<"ReadVCompressV", 0>;
1076 // LMUL Aware
1077 def : ReadAdvance<ReadVMov1V, 0>;
1078 def : ReadAdvance<ReadVMov2V, 0>;
1079 def : ReadAdvance<ReadVMov4V, 0>;
1080 def : ReadAdvance<ReadVMov8V, 0>;
1081
1082 // Others
1083 def : ReadAdvance<ReadVMask, 0>;
1084 def : ReadAdvance<ReadVMergeOp_WorstCase, 0>;
1085 foreach mx = SchedMxList in {
1086   def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx), 0>;
1087   foreach sew = SchedSEWSet<mx>.val in
1088     def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx  # "_E" # sew), 0>;
1089 }
1090
1091 // Vector Crypto Extensions
1092 // Zvbb
1093 defm "" : LMULReadAdvance<"ReadVBREVV", 0>;
1094 defm "" : LMULReadAdvance<"ReadVCLZV", 0>;
1095 defm "" : LMULReadAdvance<"ReadVCPOPV", 0>;
1096 defm "" : LMULReadAdvance<"ReadVCTZV", 0>;
1097 defm "" : LMULReadAdvance<"ReadVWSLLV", 0>;
1098 defm "" : LMULReadAdvance<"ReadVWSLLX", 0>;
1099 // Zvbc
1100 defm "" : LMULReadAdvance<"ReadVCLMULV", 0>;
1101 defm "" : LMULReadAdvance<"ReadVCLMULX", 0>;
1102 // Zvkb
1103 // VANDN uses ReadVIALU[V|X|I]
1104 defm "" : LMULReadAdvance<"ReadVBREV8V", 0>;
1105 defm "" : LMULReadAdvance<"ReadVREV8V", 0>;
1106 defm "" : LMULReadAdvance<"ReadVRotV", 0>;
1107 defm "" : LMULReadAdvance<"ReadVRotX", 0>;
1108 // Zvkg
1109 defm "" : LMULReadAdvance<"ReadVGHSHV", 0>;
1110 defm "" : LMULReadAdvance<"ReadVGMULV", 0>;
1111 // Zvknha or Zvknhb
1112 defm "" : LMULReadAdvance<"ReadVSHA2CHV", 0>;
1113 defm "" : LMULReadAdvance<"ReadVSHA2CLV", 0>;
1114 defm "" : LMULReadAdvance<"ReadVSHA2MSV", 0>;
1115 // Zvkned
1116 defm "" : LMULReadAdvance<"ReadVAESMVV", 0>;
1117 defm "" : LMULReadAdvance<"ReadVAESKF1V", 0>;
1118 defm "" : LMULReadAdvance<"ReadVAESKF2V", 0>;
1119 defm "" : LMULReadAdvance<"ReadVAESZV", 0>;
1120 // Zvksed
1121 defm "" : LMULReadAdvance<"ReadVSM4KV", 0>;
1122 defm "" : LMULReadAdvance<"ReadVSM4RV", 0>;
1123 // Zbksh
1124 defm "" : LMULReadAdvance<"ReadVSM3CV", 0>;
1125 defm "" : LMULReadAdvance<"ReadVSM3MEV", 0>;
1126
1127 //===----------------------------------------------------------------------===//
1128 // Unsupported extensions
1129 defm : UnsupportedSchedZabha;
1130 defm : UnsupportedSchedZbc;
1131 defm : UnsupportedSchedZbkb;
1132 defm : UnsupportedSchedZbkx;
1133 defm : UnsupportedSchedSFB;
1134 defm : UnsupportedSchedZfa;
1135 defm : UnsupportedSchedXsfvcp;
1136 }