llvm/lib/Target/RISCV/RISCVScheduleXSf.td

   1 //===-- RISCVScheduleXSf.td - Scheduling Definitions XSf ---*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file describes the scheduling information for SiFive extensions.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 multiclass LMULSchedWritesVCIX<string id>{
  14 defm "" : LMULSchedWrites<"WriteVC_" # id>;
  15 defm "" : LMULSchedWrites<"WriteVC_V_" # id>;
  16 }
  17
  18 defm "" : LMULSchedWritesVCIX<"I">;
  19 defm "" : LMULSchedWritesVCIX<"X">;
  20 defm "" : LMULSchedWritesVCIX<"IV">;
  21 defm "" : LMULSchedWritesVCIX<"VV">;
  22 defm "" : LMULSchedWritesVCIX<"XV">;
  23 defm "" : LMULSchedWritesVCIX<"IVV">;
  24 defm "" : LMULSchedWritesVCIX<"IVW">;
  25 defm "" : LMULSchedWritesVCIX<"VVV">;
  26 defm "" : LMULSchedWritesVCIX<"VVW">;
  27 defm "" : LMULSchedWritesVCIX<"XVV">;
  28 defm "" : LMULSchedWritesVCIX<"XVW">;
  29 foreach f = ["FPR16", "FPR32", "FPR64"] in {
  30   defm "" : LMULSchedWritesVCIX<f # "V">;
  31   defm "" : LMULSchedWritesVCIX<f # "VV">;
  32   defm "" : LMULSchedWritesVCIX<f # "VW">;
  33 }
  34
  35 multiclass LMULWriteResVCIX<string id, list<ProcResourceKind> resources>{
  36 defm : LMULWriteRes<"WriteVC_" # id, resources>;
  37 defm : LMULWriteRes<"WriteVC_V_" # id, resources>;
  38 }
  39
  40 multiclass UnsupportedSchedXsfvcp {
  41 let Unsupported = true in {
  42 defm : LMULWriteResVCIX<"I", []>;
  43 defm : LMULWriteResVCIX<"X", []>;
  44 defm : LMULWriteResVCIX<"IV", []>;
  45 defm : LMULWriteResVCIX<"VV", []>;
  46 defm : LMULWriteResVCIX<"XV", []>;
  47 defm : LMULWriteResVCIX<"IVV", []>;
  48 defm : LMULWriteResVCIX<"IVW", []>;
  49 defm : LMULWriteResVCIX<"VVV", []>;
  50 defm : LMULWriteResVCIX<"VVW", []>;
  51 defm : LMULWriteResVCIX<"XVV", []>;
  52 defm : LMULWriteResVCIX<"XVW", []>;
  53 foreach f = ["FPR16", "FPR32", "FPR64"] in {
  54   defm : LMULWriteResVCIX<f # "V", []>;
  55   defm : LMULWriteResVCIX<f # "VV", []>;
  56   defm : LMULWriteResVCIX<f # "VW", []>;
  57 }
  58 }
  59 }