clang/test/CodeGenCXX/attr-target-clones-riscv.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals all --include-generated-funcs --version 4
   2 // RUN: %clang_cc1 -std=c++11 -triple riscv64-linux-gnu -target-feature +i -target-feature +m -emit-llvm %s -o - | FileCheck %s
   3
   4 __attribute__((target_clones("default", "arch=+m"))) int foo1(void) {
   5   return 1;
   6 }
   7 __attribute__((target_clones("default", "arch=+zbb", "arch=+m"))) int foo2(void) { return 2; }
   8 __attribute__((target_clones("default", "arch=+zbb,+c"))) int foo3(void) { return 3; }
   9 __attribute__((target_clones("default", "arch=+zbb,+v"))) int
  10 foo4(void) {
  11   return 4;
  12 }
  13 __attribute__((target_clones("default"))) int foo5(void) { return 5; }
  14 __attribute__((target_clones("default", "arch=+zvkt"))) int foo6(void) { return 2; }
  15
  16 __attribute__((target_clones("default", "arch=+zbb", "arch=+zba", "arch=+zbb,+zba"))) int foo7(void) { return 2; }
  17 __attribute__((target_clones("default", "arch=+zbb;priority=2", "arch=+zba;priority=1", "arch=+zbb,+zba;priority=3"))) int foo8(void) { return 2; }
  18 __attribute__((target_clones("default", "arch=+zbb;priority=1", "priority=2;arch=+zba", "priority=3;arch=+zbb,+zba"))) int foo9(void) { return 2; }
  19 __attribute__((target_clones("default", "arch=+zbb;priority=-1", "priority=-2;arch=+zba", "priority=3;arch=+zbb,+zba"))) int foo10(void) { return 2; }
  20
  21 int bar() { return foo1() + foo2() + foo3() + foo4() + foo5()+ foo6() + foo7() + foo8() + foo9() + foo10(); }
  22
  23 //.
  24 // CHECK: @__riscv_feature_bits = external dso_local global { i32, [2 x i64] }
  25 // CHECK: @_Z4foo1v.ifunc = weak_odr alias i32 (), ptr @_Z4foo1v
  26 // CHECK: @_Z4foo2v.ifunc = weak_odr alias i32 (), ptr @_Z4foo2v
  27 // CHECK: @_Z4foo3v.ifunc = weak_odr alias i32 (), ptr @_Z4foo3v
  28 // CHECK: @_Z4foo4v.ifunc = weak_odr alias i32 (), ptr @_Z4foo4v
  29 // CHECK: @_Z4foo5v.ifunc = weak_odr alias i32 (), ptr @_Z4foo5v
  30 // CHECK: @_Z4foo6v.ifunc = weak_odr alias i32 (), ptr @_Z4foo6v
  31 // CHECK: @_Z4foo7v.ifunc = weak_odr alias i32 (), ptr @_Z4foo7v
  32 // CHECK: @_Z4foo8v.ifunc = weak_odr alias i32 (), ptr @_Z4foo8v
  33 // CHECK: @_Z4foo9v.ifunc = weak_odr alias i32 (), ptr @_Z4foo9v
  34 // CHECK: @_Z5foo10v.ifunc = weak_odr alias i32 (), ptr @_Z5foo10v
  35 // CHECK: @_Z4foo1v = weak_odr ifunc i32 (), ptr @_Z4foo1v.resolver
  36 // CHECK: @_Z4foo2v = weak_odr ifunc i32 (), ptr @_Z4foo2v.resolver
  37 // CHECK: @_Z4foo3v = weak_odr ifunc i32 (), ptr @_Z4foo3v.resolver
  38 // CHECK: @_Z4foo4v = weak_odr ifunc i32 (), ptr @_Z4foo4v.resolver
  39 // CHECK: @_Z4foo5v = weak_odr ifunc i32 (), ptr @_Z4foo5v.resolver
  40 // CHECK: @_Z4foo6v = weak_odr ifunc i32 (), ptr @_Z4foo6v.resolver
  41 // CHECK: @_Z4foo7v = weak_odr ifunc i32 (), ptr @_Z4foo7v.resolver
  42 // CHECK: @_Z4foo8v = weak_odr ifunc i32 (), ptr @_Z4foo8v.resolver
  43 // CHECK: @_Z4foo9v = weak_odr ifunc i32 (), ptr @_Z4foo9v.resolver
  44 // CHECK: @_Z5foo10v = weak_odr ifunc i32 (), ptr @_Z5foo10v.resolver
  45 //.
  46 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo1v.default(
  47 // CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
  48 // CHECK-NEXT:  entry:
  49 // CHECK-NEXT:    ret i32 1
  50 //
  51 //
  52 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo1v._m(
  53 // CHECK-SAME: ) #[[ATTR0]] {
  54 // CHECK-NEXT:  entry:
  55 // CHECK-NEXT:    ret i32 1
  56 //
  57 //
  58 // CHECK-LABEL: define weak_odr ptr @_Z4foo1v.resolver() comdat {
  59 // CHECK-NEXT:  resolver_entry:
  60 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
  61 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
  62 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 4096
  63 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4096
  64 // CHECK-NEXT:    br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
  65 // CHECK:       resolver_return:
  66 // CHECK-NEXT:    ret ptr @_Z4foo1v._m
  67 // CHECK:       resolver_else:
  68 // CHECK-NEXT:    ret ptr @_Z4foo1v.default
  69 //
  70 //
  71 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v.default(
  72 // CHECK-SAME: ) #[[ATTR0]] {
  73 // CHECK-NEXT:  entry:
  74 // CHECK-NEXT:    ret i32 2
  75 //
  76 //
  77 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v._zbb(
  78 // CHECK-SAME: ) #[[ATTR1:[0-9]+]] {
  79 // CHECK-NEXT:  entry:
  80 // CHECK-NEXT:    ret i32 2
  81 //
  82 //
  83 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v._m(
  84 // CHECK-SAME: ) #[[ATTR0]] {
  85 // CHECK-NEXT:  entry:
  86 // CHECK-NEXT:    ret i32 2
  87 //
  88 //
  89 // CHECK-LABEL: define weak_odr ptr @_Z4foo2v.resolver() comdat {
  90 // CHECK-NEXT:  resolver_entry:
  91 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
  92 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
  93 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 268435456
  94 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435456
  95 // CHECK-NEXT:    br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
  96 // CHECK:       resolver_return:
  97 // CHECK-NEXT:    ret ptr @_Z4foo2v._zbb
  98 // CHECK:       resolver_else:
  99 // CHECK-NEXT:    [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 100 // CHECK-NEXT:    [[TMP4:%.*]] = and i64 [[TMP3]], 4096
 101 // CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 4096
 102 // CHECK-NEXT:    br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 103 // CHECK:       resolver_return1:
 104 // CHECK-NEXT:    ret ptr @_Z4foo2v._m
 105 // CHECK:       resolver_else2:
 106 // CHECK-NEXT:    ret ptr @_Z4foo2v.default
 107 //
 108 //
 109 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo3v.default(
 110 // CHECK-SAME: ) #[[ATTR0]] {
 111 // CHECK-NEXT:  entry:
 112 // CHECK-NEXT:    ret i32 3
 113 //
 114 //
 115 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo3v._c_zbb(
 116 // CHECK-SAME: ) #[[ATTR2:[0-9]+]] {
 117 // CHECK-NEXT:  entry:
 118 // CHECK-NEXT:    ret i32 3
 119 //
 120 //
 121 // CHECK-LABEL: define weak_odr ptr @_Z4foo3v.resolver() comdat {
 122 // CHECK-NEXT:  resolver_entry:
 123 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
 124 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 125 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 268435460
 126 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435460
 127 // CHECK-NEXT:    br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 128 // CHECK:       resolver_return:
 129 // CHECK-NEXT:    ret ptr @_Z4foo3v._c_zbb
 130 // CHECK:       resolver_else:
 131 // CHECK-NEXT:    ret ptr @_Z4foo3v.default
 132 //
 133 //
 134 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo4v.default(
 135 // CHECK-SAME: ) #[[ATTR0]] {
 136 // CHECK-NEXT:  entry:
 137 // CHECK-NEXT:    ret i32 4
 138 //
 139 //
 140 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo4v._v_zbb(
 141 // CHECK-SAME: ) #[[ATTR3:[0-9]+]] {
 142 // CHECK-NEXT:  entry:
 143 // CHECK-NEXT:    ret i32 4
 144 //
 145 //
 146 // CHECK-LABEL: define weak_odr ptr @_Z4foo4v.resolver() comdat {
 147 // CHECK-NEXT:  resolver_entry:
 148 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
 149 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 150 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 270532608
 151 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 270532608
 152 // CHECK-NEXT:    br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 153 // CHECK:       resolver_return:
 154 // CHECK-NEXT:    ret ptr @_Z4foo4v._v_zbb
 155 // CHECK:       resolver_else:
 156 // CHECK-NEXT:    ret ptr @_Z4foo4v.default
 157 //
 158 //
 159 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo5v.default(
 160 // CHECK-SAME: ) #[[ATTR0]] {
 161 // CHECK-NEXT:  entry:
 162 // CHECK-NEXT:    ret i32 5
 163 //
 164 //
 165 // CHECK-LABEL: define weak_odr ptr @_Z4foo5v.resolver() comdat {
 166 // CHECK-NEXT:  resolver_entry:
 167 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
 168 // CHECK-NEXT:    ret ptr @_Z4foo5v.default
 169 //
 170 //
 171 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo6v.default(
 172 // CHECK-SAME: ) #[[ATTR0]] {
 173 // CHECK-NEXT:  entry:
 174 // CHECK-NEXT:    ret i32 2
 175 //
 176 //
 177 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo6v._zvkt(
 178 // CHECK-SAME: ) #[[ATTR4:[0-9]+]] {
 179 // CHECK-NEXT:  entry:
 180 // CHECK-NEXT:    ret i32 2
 181 //
 182 //
 183 // CHECK-LABEL: define weak_odr ptr @_Z4foo6v.resolver() comdat {
 184 // CHECK-NEXT:  resolver_entry:
 185 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
 186 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 187 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 576460752303423488
 188 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 576460752303423488
 189 // CHECK-NEXT:    br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 190 // CHECK:       resolver_return:
 191 // CHECK-NEXT:    ret ptr @_Z4foo6v._zvkt
 192 // CHECK:       resolver_else:
 193 // CHECK-NEXT:    ret ptr @_Z4foo6v.default
 194 //
 195 //
 196 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v.default(
 197 // CHECK-SAME: ) #[[ATTR0]] {
 198 // CHECK-NEXT:  entry:
 199 // CHECK-NEXT:    ret i32 2
 200 //
 201 //
 202 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v._zbb(
 203 // CHECK-SAME: ) #[[ATTR1]] {
 204 // CHECK-NEXT:  entry:
 205 // CHECK-NEXT:    ret i32 2
 206 //
 207 //
 208 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v._zba(
 209 // CHECK-SAME: ) #[[ATTR5:[0-9]+]] {
 210 // CHECK-NEXT:  entry:
 211 // CHECK-NEXT:    ret i32 2
 212 //
 213 //
 214 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v._zba_zbb(
 215 // CHECK-SAME: ) #[[ATTR6:[0-9]+]] {
 216 // CHECK-NEXT:  entry:
 217 // CHECK-NEXT:    ret i32 2
 218 //
 219 //
 220 // CHECK-LABEL: define weak_odr ptr @_Z4foo7v.resolver() comdat {
 221 // CHECK-NEXT:  resolver_entry:
 222 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
 223 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 224 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 268435456
 225 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435456
 226 // CHECK-NEXT:    br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 227 // CHECK:       resolver_return:
 228 // CHECK-NEXT:    ret ptr @_Z4foo7v._zbb
 229 // CHECK:       resolver_else:
 230 // CHECK-NEXT:    [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 231 // CHECK-NEXT:    [[TMP4:%.*]] = and i64 [[TMP3]], 134217728
 232 // CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 134217728
 233 // CHECK-NEXT:    br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 234 // CHECK:       resolver_return1:
 235 // CHECK-NEXT:    ret ptr @_Z4foo7v._zba
 236 // CHECK:       resolver_else2:
 237 // CHECK-NEXT:    [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 238 // CHECK-NEXT:    [[TMP7:%.*]] = and i64 [[TMP6]], 402653184
 239 // CHECK-NEXT:    [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 402653184
 240 // CHECK-NEXT:    br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
 241 // CHECK:       resolver_return3:
 242 // CHECK-NEXT:    ret ptr @_Z4foo7v._zba_zbb
 243 // CHECK:       resolver_else4:
 244 // CHECK-NEXT:    ret ptr @_Z4foo7v.default
 245 //
 246 //
 247 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo8v.default(
 248 // CHECK-SAME: ) #[[ATTR0]] {
 249 // CHECK-NEXT:  entry:
 250 // CHECK-NEXT:    ret i32 2
 251 //
 252 //
 253 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo8v._zbb(
 254 // CHECK-SAME: ) #[[ATTR1]] {
 255 // CHECK-NEXT:  entry:
 256 // CHECK-NEXT:    ret i32 2
 257 //
 258 //
 259 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo8v._zba(
 260 // CHECK-SAME: ) #[[ATTR5]] {
 261 // CHECK-NEXT:  entry:
 262 // CHECK-NEXT:    ret i32 2
 263 //
 264 //
 265 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo8v._zba_zbb(
 266 // CHECK-SAME: ) #[[ATTR6]] {
 267 // CHECK-NEXT:  entry:
 268 // CHECK-NEXT:    ret i32 2
 269 //
 270 //
 271 // CHECK-LABEL: define weak_odr ptr @_Z4foo8v.resolver() comdat {
 272 // CHECK-NEXT:  resolver_entry:
 273 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
 274 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 275 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 402653184
 276 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 402653184
 277 // CHECK-NEXT:    br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 278 // CHECK:       resolver_return:
 279 // CHECK-NEXT:    ret ptr @_Z4foo8v._zba_zbb
 280 // CHECK:       resolver_else:
 281 // CHECK-NEXT:    [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 282 // CHECK-NEXT:    [[TMP4:%.*]] = and i64 [[TMP3]], 268435456
 283 // CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 268435456
 284 // CHECK-NEXT:    br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 285 // CHECK:       resolver_return1:
 286 // CHECK-NEXT:    ret ptr @_Z4foo8v._zbb
 287 // CHECK:       resolver_else2:
 288 // CHECK-NEXT:    [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 289 // CHECK-NEXT:    [[TMP7:%.*]] = and i64 [[TMP6]], 134217728
 290 // CHECK-NEXT:    [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 134217728
 291 // CHECK-NEXT:    br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
 292 // CHECK:       resolver_return3:
 293 // CHECK-NEXT:    ret ptr @_Z4foo8v._zba
 294 // CHECK:       resolver_else4:
 295 // CHECK-NEXT:    ret ptr @_Z4foo8v.default
 296 //
 297 //
 298 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo9v.default(
 299 // CHECK-SAME: ) #[[ATTR0]] {
 300 // CHECK-NEXT:  entry:
 301 // CHECK-NEXT:    ret i32 2
 302 //
 303 //
 304 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo9v._zbb(
 305 // CHECK-SAME: ) #[[ATTR1]] {
 306 // CHECK-NEXT:  entry:
 307 // CHECK-NEXT:    ret i32 2
 308 //
 309 //
 310 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo9v._zba(
 311 // CHECK-SAME: ) #[[ATTR5]] {
 312 // CHECK-NEXT:  entry:
 313 // CHECK-NEXT:    ret i32 2
 314 //
 315 //
 316 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo9v._zba_zbb(
 317 // CHECK-SAME: ) #[[ATTR6]] {
 318 // CHECK-NEXT:  entry:
 319 // CHECK-NEXT:    ret i32 2
 320 //
 321 //
 322 // CHECK-LABEL: define weak_odr ptr @_Z4foo9v.resolver() comdat {
 323 // CHECK-NEXT:  resolver_entry:
 324 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
 325 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 326 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 402653184
 327 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 402653184
 328 // CHECK-NEXT:    br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 329 // CHECK:       resolver_return:
 330 // CHECK-NEXT:    ret ptr @_Z4foo9v._zba_zbb
 331 // CHECK:       resolver_else:
 332 // CHECK-NEXT:    [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 333 // CHECK-NEXT:    [[TMP4:%.*]] = and i64 [[TMP3]], 134217728
 334 // CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 134217728
 335 // CHECK-NEXT:    br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 336 // CHECK:       resolver_return1:
 337 // CHECK-NEXT:    ret ptr @_Z4foo9v._zba
 338 // CHECK:       resolver_else2:
 339 // CHECK-NEXT:    [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 340 // CHECK-NEXT:    [[TMP7:%.*]] = and i64 [[TMP6]], 268435456
 341 // CHECK-NEXT:    [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 268435456
 342 // CHECK-NEXT:    br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
 343 // CHECK:       resolver_return3:
 344 // CHECK-NEXT:    ret ptr @_Z4foo9v._zbb
 345 // CHECK:       resolver_else4:
 346 // CHECK-NEXT:    ret ptr @_Z4foo9v.default
 347 //
 348 //
 349 // CHECK-LABEL: define dso_local noundef signext i32 @_Z5foo10v.default(
 350 // CHECK-SAME: ) #[[ATTR0]] {
 351 // CHECK-NEXT:  entry:
 352 // CHECK-NEXT:    ret i32 2
 353 //
 354 //
 355 // CHECK-LABEL: define dso_local noundef signext i32 @_Z5foo10v._zbb(
 356 // CHECK-SAME: ) #[[ATTR1]] {
 357 // CHECK-NEXT:  entry:
 358 // CHECK-NEXT:    ret i32 2
 359 //
 360 //
 361 // CHECK-LABEL: define dso_local noundef signext i32 @_Z5foo10v._zba(
 362 // CHECK-SAME: ) #[[ATTR5]] {
 363 // CHECK-NEXT:  entry:
 364 // CHECK-NEXT:    ret i32 2
 365 //
 366 //
 367 // CHECK-LABEL: define dso_local noundef signext i32 @_Z5foo10v._zba_zbb(
 368 // CHECK-SAME: ) #[[ATTR6]] {
 369 // CHECK-NEXT:  entry:
 370 // CHECK-NEXT:    ret i32 2
 371 //
 372 //
 373 // CHECK-LABEL: define weak_odr ptr @_Z5foo10v.resolver() comdat {
 374 // CHECK-NEXT:  resolver_entry:
 375 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
 376 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 377 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 402653184
 378 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 402653184
 379 // CHECK-NEXT:    br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 380 // CHECK:       resolver_return:
 381 // CHECK-NEXT:    ret ptr @_Z5foo10v._zba_zbb
 382 // CHECK:       resolver_else:
 383 // CHECK-NEXT:    [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 384 // CHECK-NEXT:    [[TMP4:%.*]] = and i64 [[TMP3]], 268435456
 385 // CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 268435456
 386 // CHECK-NEXT:    br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 387 // CHECK:       resolver_return1:
 388 // CHECK-NEXT:    ret ptr @_Z5foo10v._zbb
 389 // CHECK:       resolver_else2:
 390 // CHECK-NEXT:    [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 391 // CHECK-NEXT:    [[TMP7:%.*]] = and i64 [[TMP6]], 134217728
 392 // CHECK-NEXT:    [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 134217728
 393 // CHECK-NEXT:    br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
 394 // CHECK:       resolver_return3:
 395 // CHECK-NEXT:    ret ptr @_Z5foo10v._zba
 396 // CHECK:       resolver_else4:
 397 // CHECK-NEXT:    ret ptr @_Z5foo10v.default
 398 //
 399 //
 400 // CHECK-LABEL: define dso_local noundef signext i32 @_Z3barv(
 401 // CHECK-SAME: ) #[[ATTR0]] {
 402 // CHECK-NEXT:  entry:
 403 // CHECK-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z4foo1v()
 404 // CHECK-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_Z4foo2v()
 405 // CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]
 406 // CHECK-NEXT:    [[CALL2:%.*]] = call noundef signext i32 @_Z4foo3v()
 407 // CHECK-NEXT:    [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]]
 408 // CHECK-NEXT:    [[CALL4:%.*]] = call noundef signext i32 @_Z4foo4v()
 409 // CHECK-NEXT:    [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]]
 410 // CHECK-NEXT:    [[CALL6:%.*]] = call noundef signext i32 @_Z4foo5v()
 411 // CHECK-NEXT:    [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CALL6]]
 412 // CHECK-NEXT:    [[CALL8:%.*]] = call noundef signext i32 @_Z4foo6v()
 413 // CHECK-NEXT:    [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CALL8]]
 414 // CHECK-NEXT:    [[CALL10:%.*]] = call noundef signext i32 @_Z4foo7v()
 415 // CHECK-NEXT:    [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CALL10]]
 416 // CHECK-NEXT:    [[CALL12:%.*]] = call noundef signext i32 @_Z4foo8v()
 417 // CHECK-NEXT:    [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CALL12]]
 418 // CHECK-NEXT:    [[CALL14:%.*]] = call noundef signext i32 @_Z4foo9v()
 419 // CHECK-NEXT:    [[ADD15:%.*]] = add nsw i32 [[ADD13]], [[CALL14]]
 420 // CHECK-NEXT:    [[CALL16:%.*]] = call noundef signext i32 @_Z5foo10v()
 421 // CHECK-NEXT:    [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CALL16]]
 422 // CHECK-NEXT:    ret i32 [[ADD17]]
 423 //
 424 //.
 425 // CHECK: attributes #[[ATTR0]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zmmul" }
 426 // CHECK: attributes #[[ATTR1]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zbb,+zmmul" }
 427 // CHECK: attributes #[[ATTR2]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+c,+i,+m,+zbb,+zmmul" }
 428 // CHECK: attributes #[[ATTR3]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+m,+v,+zbb,+zicsr,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
 429 // CHECK: attributes #[[ATTR4]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zmmul,+zvkt" }
 430 // CHECK: attributes #[[ATTR5]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zba,+zmmul" }
 431 // CHECK: attributes #[[ATTR6]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zba,+zbb,+zmmul" }
 432 //.
 433 // CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
 434 // CHECK: [[META1:![0-9]+]] = !{i32 1, !"target-abi", !"lp64"}
 435 // CHECK: [[META2:![0-9]+]] = !{i32 6, !"riscv-isa", [[META3:![0-9]+]]}
 436 // CHECK: [[META3]] = !{!"rv64i2p1_m2p0_zmmul1p0"}
 437 // CHECK: [[META4:![0-9]+]] = !{i32 8, !"SmallDataLimit", i32 0}
 438 // CHECK: [[META5:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
 439 //.