[OpenACC] Create AST nodes for 'data' constructs
[llvm-project.git] / llvm / test / tools / llvm-mca / RISCV / SyntacoreSCR / SCR7-LSU.s
blob2b3ab2ba4192f01c2c3eb7dc74bb25219a28cfe7
1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2 # RUN: llvm-mca -mtriple=riscv64-unknown-unknown -mcpu=syntacore-scr7 --iterations=1 < %s | FileCheck %s --check-prefixes=CHECK
4 lw a0, 0(s0)
5 lw a1, 0(s0)
6 lw a2, 0(s0)
7 lw a3, 0(s0)
9 # CHECK: Iterations: 1
10 # CHECK-NEXT: Instructions: 4
11 # CHECK-NEXT: Total Cycles: 9
12 # CHECK-NEXT: Total uOps: 4
14 # CHECK: Dispatch Width: 2
15 # CHECK-NEXT: uOps Per Cycle: 0.44
16 # CHECK-NEXT: IPC: 0.44
17 # CHECK-NEXT: Block RThroughput: 4.0
19 # CHECK: Instruction Info:
20 # CHECK-NEXT: [1]: #uOps
21 # CHECK-NEXT: [2]: Latency
22 # CHECK-NEXT: [3]: RThroughput
23 # CHECK-NEXT: [4]: MayLoad
24 # CHECK-NEXT: [5]: MayStore
25 # CHECK-NEXT: [6]: HasSideEffects (U)
27 # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
28 # CHECK-NEXT: 1 3 1.00 * lw a0, 0(s0)
29 # CHECK-NEXT: 1 3 1.00 * lw a1, 0(s0)
30 # CHECK-NEXT: 1 3 1.00 * lw a2, 0(s0)
31 # CHECK-NEXT: 1 3 1.00 * lw a3, 0(s0)
33 # CHECK: Resources:
34 # CHECK-NEXT: [0] - SCR7_ALU_DIV_IS
35 # CHECK-NEXT: [1] - SCR7_ALU_MUL_IS
36 # CHECK-NEXT: [2] - SCR7_DIV
37 # CHECK-NEXT: [3] - SCR7_FALU
38 # CHECK-NEXT: [4] - SCR7_FDIVSQRT
39 # CHECK-NEXT: [5] - SCR7_FMA
40 # CHECK-NEXT: [6] - SCR7_FPU_IS
41 # CHECK-NEXT: [7] - SCR7_LSU
42 # CHECK-NEXT: [8] - SCR7_MUL
44 # CHECK: Resource pressure per iteration:
45 # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8]
46 # CHECK-NEXT: - - - - - - - 4.00 -
48 # CHECK: Resource pressure by instruction:
49 # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] Instructions:
50 # CHECK-NEXT: - - - - - - - 1.00 - lw a0, 0(s0)
51 # CHECK-NEXT: - - - - - - - 1.00 - lw a1, 0(s0)
52 # CHECK-NEXT: - - - - - - - 1.00 - lw a2, 0(s0)
53 # CHECK-NEXT: - - - - - - - 1.00 - lw a3, 0(s0)