llvm/lib/Target/RISCV/CMakeLists.txt

   1 add_llvm_component_group(RISCV)
   2
   3 set(LLVM_TARGET_DEFINITIONS RISCV.td)
   4
   5 tablegen(LLVM RISCVGenAsmMatcher.inc -gen-asm-matcher)
   6 tablegen(LLVM RISCVGenAsmWriter.inc -gen-asm-writer)
   7 tablegen(LLVM RISCVGenCompressInstEmitter.inc -gen-compress-inst-emitter)
   8 tablegen(LLVM RISCVGenMacroFusion.inc -gen-macro-fusion-pred)
   9 tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
  10 tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler)
  11 tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
  12 tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
  13 tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)
  14 tablegen(LLVM RISCVGenRegisterBank.inc -gen-register-bank)
  15 tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info)
  16 tablegen(LLVM RISCVGenSearchableTables.inc -gen-searchable-tables)
  17 tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget)
  18
  19 set(LLVM_TARGET_DEFINITIONS RISCVGISel.td)
  20 tablegen(LLVM RISCVGenGlobalISel.inc -gen-global-isel)
  21 tablegen(LLVM RISCVGenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner
  22               -combiners="RISCVO0PreLegalizerCombiner")
  23 tablegen(LLVM RISCVGenPreLegalizeGICombiner.inc -gen-global-isel-combiner
  24               -combiners="RISCVPreLegalizerCombiner")
  25 tablegen(LLVM RISCVGenPostLegalizeGICombiner.inc -gen-global-isel-combiner
  26               -combiners="RISCVPostLegalizerCombiner")
  27
  28 add_public_tablegen_target(RISCVCommonTableGen)
  29
  30 add_llvm_target(RISCVCodeGen
  31   RISCVAsmPrinter.cpp
  32   RISCVCodeGenPrepare.cpp
  33   RISCVDeadRegisterDefinitions.cpp
  34   RISCVMakeCompressible.cpp
  35   RISCVExpandAtomicPseudoInsts.cpp
  36   RISCVExpandPseudoInsts.cpp
  37   RISCVFoldMasks.cpp
  38   RISCVFrameLowering.cpp
  39   RISCVGatherScatterLowering.cpp
  40   RISCVInsertVSETVLI.cpp
  41   RISCVInsertReadWriteCSR.cpp
  42   RISCVInsertWriteVXRM.cpp
  43   RISCVInstrInfo.cpp
  44   RISCVISelDAGToDAG.cpp
  45   RISCVISelLowering.cpp
  46   RISCVMachineFunctionInfo.cpp
  47   RISCVMergeBaseOffset.cpp
  48   RISCVOptWInstrs.cpp
  49   RISCVPostRAExpandPseudoInsts.cpp
  50   RISCVRedundantCopyElimination.cpp
  51   RISCVMoveMerger.cpp
  52   RISCVPushPopOptimizer.cpp
  53   RISCVRegisterInfo.cpp
  54   RISCVRVVInitUndef.cpp
  55   RISCVSubtarget.cpp
  56   RISCVTargetMachine.cpp
  57   RISCVTargetObjectFile.cpp
  58   RISCVTargetTransformInfo.cpp
  59   GISel/RISCVCallLowering.cpp
  60   GISel/RISCVInstructionSelector.cpp
  61   GISel/RISCVLegalizerInfo.cpp
  62   GISel/RISCVPostLegalizerCombiner.cpp
  63   GISel/RISCVO0PreLegalizerCombiner.cpp
  64   GISel/RISCVPreLegalizerCombiner.cpp
  65   GISel/RISCVRegisterBankInfo.cpp
  66
  67   LINK_COMPONENTS
  68   Analysis
  69   AsmPrinter
  70   CodeGen
  71   CodeGenTypes
  72   Core
  73   GlobalISel
  74   IPO
  75   MC
  76   RISCVDesc
  77   RISCVInfo
  78   Scalar
  79   SelectionDAG
  80   Support
  81   Target
  82   TargetParser
  83   TransformUtils
  84
  85   ADD_TO_COMPONENT
  86   RISCV
  87   )
  88
  89 add_subdirectory(AsmParser)
  90 add_subdirectory(Disassembler)
  91 add_subdirectory(MCTargetDesc)
  92 add_subdirectory(MCA)
  93 add_subdirectory(TargetInfo)