llvm/lib/Target/RISCV/RISCVProcessors.td

   1 //===-- RISCVProcessors.td - RISC-V Processors -------------*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 //===----------------------------------------------------------------------===//
  10 // RISC-V processors supported.
  11 //===----------------------------------------------------------------------===//
  12
  13 class RISCVTuneInfo {
  14   bits<8> PrefFunctionAlignment = 1;
  15   bits<8> PrefLoopAlignment = 1;
  16
  17   // Information needed by LoopDataPrefetch.
  18   bits<16> CacheLineSize = 0;
  19   bits<16> PrefetchDistance = 0;
  20   bits<16> MinPrefetchStride = 1;
  21   bits<32> MaxPrefetchIterationsAhead = -1;
  22
  23   bits<32> MinimumJumpTableEntries = 5;
  24 }
  25
  26 def RISCVTuneInfoTable : GenericTable {
  27   let FilterClass = "RISCVTuneInfo";
  28   let CppTypeName = "RISCVTuneInfo";
  29   let Fields = ["Name", "PrefFunctionAlignment", "PrefLoopAlignment",
  30                 "CacheLineSize", "PrefetchDistance",
  31                 "MinPrefetchStride", "MaxPrefetchIterationsAhead",
  32                 "MinimumJumpTableEntries"];
  33 }
  34
  35 def getRISCVTuneInfo : SearchIndex {
  36   let Table = RISCVTuneInfoTable;
  37   let Key = ["Name"];
  38 }
  39
  40 class GenericTuneInfo: RISCVTuneInfo;
  41
  42 class RISCVProcessorModel<string n,
  43                           SchedMachineModel m,
  44                           list<SubtargetFeature> f,
  45                           list<SubtargetFeature> tunef = [],
  46                           string default_march = "">
  47       :  ProcessorModel<n, m, f, tunef> {
  48   string DefaultMarch = default_march;
  49 }
  50
  51 class RISCVTuneProcessorModel<string n,
  52                               SchedMachineModel m,
  53                               list<SubtargetFeature> tunef = [],
  54                               list<SubtargetFeature> f = []>
  55       : ProcessorModel<n, m, f,tunef>;
  56
  57 def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
  58                                        NoSchedModel,
  59                                        [Feature32Bit]>,
  60                    GenericTuneInfo;
  61 def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
  62                                        NoSchedModel,
  63                                        [Feature64Bit]>,
  64                    GenericTuneInfo;
  65 // Support generic for compatibility with other targets. The triple will be used
  66 // to change to the appropriate rv32/rv64 version.
  67 def : ProcessorModel<"generic", NoSchedModel, []>, GenericTuneInfo;
  68
  69 def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32",
  70                                       RocketModel,
  71                                       [Feature32Bit,
  72                                        FeatureStdExtZifencei,
  73                                        FeatureStdExtZicsr]>;
  74 def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64",
  75                                       RocketModel,
  76                                       [Feature64Bit,
  77                                        FeatureStdExtZifencei,
  78                                        FeatureStdExtZicsr]>;
  79 def ROCKET : RISCVTuneProcessorModel<"rocket",
  80                                      RocketModel>;
  81
  82 def SIFIVE_7 : RISCVTuneProcessorModel<"sifive-7-series",
  83                                        SiFive7Model,
  84                                        [TuneSiFive7]>;
  85
  86 def SIFIVE_E20 : RISCVProcessorModel<"sifive-e20",
  87                                      RocketModel,
  88                                      [Feature32Bit,
  89                                       FeatureStdExtZicsr,
  90                                       FeatureStdExtZifencei,
  91                                       FeatureStdExtM,
  92                                       FeatureStdExtC]>;
  93
  94 def SIFIVE_E21 : RISCVProcessorModel<"sifive-e21",
  95                                      RocketModel,
  96                                      [Feature32Bit,
  97                                       FeatureStdExtZicsr,
  98                                       FeatureStdExtZifencei,
  99                                       FeatureStdExtM,
 100                                       FeatureStdExtA,
 101                                       FeatureStdExtC]>;
 102
 103 def SIFIVE_E24 : RISCVProcessorModel<"sifive-e24",
 104                                      RocketModel,
 105                                      [Feature32Bit,
 106                                       FeatureStdExtZifencei,
 107                                       FeatureStdExtM,
 108                                       FeatureStdExtA,
 109                                       FeatureStdExtF,
 110                                       FeatureStdExtC]>;
 111
 112 def SIFIVE_E31 : RISCVProcessorModel<"sifive-e31",
 113                                      RocketModel,
 114                                      [Feature32Bit,
 115                                       FeatureStdExtZifencei,
 116                                       FeatureStdExtZicsr,
 117                                       FeatureStdExtM,
 118                                       FeatureStdExtA,
 119                                       FeatureStdExtC]>;
 120
 121 def SIFIVE_E34 : RISCVProcessorModel<"sifive-e34",
 122                                      RocketModel,
 123                                      [Feature32Bit,
 124                                       FeatureStdExtZifencei,
 125                                       FeatureStdExtM,
 126                                       FeatureStdExtA,
 127                                       FeatureStdExtF,
 128                                       FeatureStdExtC]>;
 129
 130 def SIFIVE_E76 : RISCVProcessorModel<"sifive-e76",
 131                                      SiFive7Model,
 132                                      [Feature32Bit,
 133                                       FeatureStdExtZifencei,
 134                                       FeatureStdExtM,
 135                                       FeatureStdExtA,
 136                                       FeatureStdExtF,
 137                                       FeatureStdExtC],
 138                                      [TuneSiFive7]>;
 139
 140 def SIFIVE_S21 : RISCVProcessorModel<"sifive-s21",
 141                                      RocketModel,
 142                                      [Feature64Bit,
 143                                       FeatureStdExtZicsr,
 144                                       FeatureStdExtZifencei,
 145                                       FeatureStdExtM,
 146                                       FeatureStdExtA,
 147                                       FeatureStdExtC]>;
 148
 149 def SIFIVE_S51 : RISCVProcessorModel<"sifive-s51",
 150                                      RocketModel,
 151                                      [Feature64Bit,
 152                                       FeatureStdExtZicsr,
 153                                       FeatureStdExtZifencei,
 154                                       FeatureStdExtM,
 155                                       FeatureStdExtA,
 156                                       FeatureStdExtC]>;
 157
 158 def SIFIVE_S54 : RISCVProcessorModel<"sifive-s54",
 159                                       RocketModel,
 160                                       [Feature64Bit,
 161                                        FeatureStdExtZifencei,
 162                                        FeatureStdExtM,
 163                                        FeatureStdExtA,
 164                                        FeatureStdExtF,
 165                                        FeatureStdExtD,
 166                                        FeatureStdExtC]>;
 167
 168 def SIFIVE_S76 : RISCVProcessorModel<"sifive-s76",
 169                                      SiFive7Model,
 170                                      [Feature64Bit,
 171                                       FeatureStdExtZifencei,
 172                                       FeatureStdExtM,
 173                                       FeatureStdExtA,
 174                                       FeatureStdExtF,
 175                                       FeatureStdExtD,
 176                                       FeatureStdExtC,
 177                                       FeatureStdExtZihintpause],
 178                                      [TuneSiFive7]>;
 179
 180 def SIFIVE_U54 : RISCVProcessorModel<"sifive-u54",
 181                                      RocketModel,
 182                                      [Feature64Bit,
 183                                       FeatureStdExtZifencei,
 184                                       FeatureStdExtM,
 185                                       FeatureStdExtA,
 186                                       FeatureStdExtF,
 187                                       FeatureStdExtD,
 188                                       FeatureStdExtC]>;
 189
 190 def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74",
 191                                      SiFive7Model,
 192                                      [Feature64Bit,
 193                                       FeatureStdExtZifencei,
 194                                       FeatureStdExtM,
 195                                       FeatureStdExtA,
 196                                       FeatureStdExtF,
 197                                       FeatureStdExtD,
 198                                       FeatureStdExtC],
 199                                      [TuneSiFive7]>;
 200
 201 def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
 202                                       [Feature64Bit,
 203                                        FeatureStdExtZifencei,
 204                                        FeatureStdExtM,
 205                                        FeatureStdExtA,
 206                                        FeatureStdExtF,
 207                                        FeatureStdExtD,
 208                                        FeatureStdExtC,
 209                                        FeatureStdExtV,
 210                                        FeatureStdExtZvl512b,
 211                                        FeatureStdExtZfh,
 212                                        FeatureStdExtZvfh,
 213                                        FeatureStdExtZba,
 214                                        FeatureStdExtZbb],
 215                                       [TuneSiFive7,
 216                                        TuneDLenFactor2]>;
 217
 218 def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model,
 219                                       [Feature64Bit,
 220                                        FeatureStdExtZifencei,
 221                                        FeatureStdExtM,
 222                                        FeatureStdExtA,
 223                                        FeatureStdExtF,
 224                                        FeatureStdExtD,
 225                                        FeatureStdExtC,
 226                                        FeatureStdExtZa64rs,
 227                                        FeatureStdExtZic64b,
 228                                        FeatureStdExtZicbop,
 229                                        FeatureStdExtZicbom,
 230                                        FeatureStdExtZicboz,
 231                                        FeatureStdExtZiccamoa,
 232                                        FeatureStdExtZiccif,
 233                                        FeatureStdExtZicclsm,
 234                                        FeatureStdExtZiccrse,
 235                                        FeatureStdExtZihintntl,
 236                                        FeatureStdExtZihintpause,
 237                                        FeatureStdExtZihpm,
 238                                        FeatureStdExtZba,
 239                                        FeatureStdExtZbb,
 240                                        FeatureStdExtZbs,
 241                                        FeatureStdExtZfhmin,
 242                                        FeatureFastUnalignedAccess],
 243                                       [TuneNoDefaultUnroll,
 244                                        TuneConditionalCompressedMoveFusion,
 245                                        TuneLUIADDIFusion,
 246                                        TuneAUIPCADDIFusion]>;
 247
 248 def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", NoSchedModel,
 249                                       [Feature64Bit,
 250                                        FeatureStdExtZifencei,
 251                                        FeatureStdExtM,
 252                                        FeatureStdExtA,
 253                                        FeatureStdExtF,
 254                                        FeatureStdExtD,
 255                                        FeatureStdExtC,
 256                                        FeatureStdExtZa64rs,
 257                                        FeatureStdExtZic64b,
 258                                        FeatureStdExtZicbop,
 259                                        FeatureStdExtZicbom,
 260                                        FeatureStdExtZicboz,
 261                                        FeatureStdExtZiccamoa,
 262                                        FeatureStdExtZiccif,
 263                                        FeatureStdExtZicclsm,
 264                                        FeatureStdExtZiccrse,
 265                                        FeatureStdExtZihintntl,
 266                                        FeatureStdExtZihintpause,
 267                                        FeatureStdExtZihpm,
 268                                        FeatureStdExtZba,
 269                                        FeatureStdExtZbb,
 270                                        FeatureStdExtZbs,
 271                                        FeatureStdExtZfhmin,
 272                                        FeatureStdExtV,
 273                                        FeatureStdExtZvl128b,
 274                                        FeatureStdExtZvbb,
 275                                        FeatureStdExtZvknc,
 276                                        FeatureStdExtZvkng,
 277                                        FeatureStdExtZvksc,
 278                                        FeatureStdExtZvksg,
 279                                        FeatureFastUnalignedAccess],
 280                                       [TuneNoDefaultUnroll,
 281                                        TuneConditionalCompressedMoveFusion,
 282                                        TuneLUIADDIFusion,
 283                                        TuneAUIPCADDIFusion]>;
 284
 285 def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
 286                                               SyntacoreSCR1Model,
 287                                               [Feature32Bit,
 288                                                FeatureStdExtZicsr,
 289                                                FeatureStdExtZifencei,
 290                                                FeatureStdExtC],
 291                                               [TuneNoDefaultUnroll]>;
 292
 293 def SYNTACORE_SCR1_MAX : RISCVProcessorModel<"syntacore-scr1-max",
 294                                              SyntacoreSCR1Model,
 295                                              [Feature32Bit,
 296                                               FeatureStdExtZicsr,
 297                                               FeatureStdExtZifencei,
 298                                               FeatureStdExtM,
 299                                               FeatureStdExtC],
 300                                              [TuneNoDefaultUnroll]>;
 301
 302 def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
 303                                             NoSchedModel,
 304                                             [Feature64Bit,
 305                                              FeatureStdExtZifencei,
 306                                              FeatureStdExtZicsr,
 307                                              FeatureStdExtZicntr,
 308                                              FeatureStdExtZihpm,
 309                                              FeatureStdExtZihintpause,
 310                                              FeatureStdExtM,
 311                                              FeatureStdExtA,
 312                                              FeatureStdExtF,
 313                                              FeatureStdExtD,
 314                                              FeatureStdExtC,
 315                                              FeatureStdExtZba,
 316                                              FeatureStdExtZbb,
 317                                              FeatureStdExtZbc,
 318                                              FeatureStdExtZbs,
 319                                              FeatureStdExtZicbom,
 320                                              FeatureStdExtZicbop,
 321                                              FeatureStdExtZicboz,
 322                                              FeatureVendorXVentanaCondOps],
 323                                              [TuneVentanaVeyron,
 324                                               TuneLUIADDIFusion,
 325                                               TuneAUIPCADDIFusion,
 326                                               TuneZExtHFusion,
 327                                               TuneZExtWFusion,
 328                                               TuneShiftedZExtWFusion,
 329                                               TuneLDADDFusion]>;
 330
 331 def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
 332                                           NoSchedModel,
 333                                           [Feature64Bit,
 334                                            FeatureStdExtZicsr,
 335                                            FeatureStdExtZifencei,
 336                                            FeatureStdExtM,
 337                                            FeatureStdExtA,
 338                                            FeatureStdExtF,
 339                                            FeatureStdExtD,
 340                                            FeatureStdExtC,
 341                                            FeatureStdExtZba,
 342                                            FeatureStdExtZbb,
 343                                            FeatureStdExtZbc,
 344                                            FeatureStdExtZbs,
 345                                            FeatureStdExtZkn,
 346                                            FeatureStdExtZksed,
 347                                            FeatureStdExtZksh,
 348                                            FeatureStdExtSvinval,
 349                                            FeatureStdExtZicbom,
 350                                            FeatureStdExtZicboz]>;