llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td

   1 //==- RISCVSchedSyntacoreSCR1.td - Syntacore SCR1 Scheduling Definitions --------*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 //===----------------------------------------------------------------------===//
  10
  11 // SCR1: https://github.com/syntacore/scr1
  12
  13 // This model covers SYNTACORE_SCR1_CFG_RV32IMC_MAX configuration (syntacore-scr1-max).
  14 // SYNTACORE_SCR1_CFG_RV32IC_BASE (syntacore-scr1-base) configuration has essentially
  15 // same scheduling characteristics.
  16
  17 // SCR1 is single-issue in-order processor
  18 def SyntacoreSCR1Model : SchedMachineModel {
  19   let MicroOpBufferSize = 0;
  20   let IssueWidth = 1;
  21   let LoadLatency = 2;
  22   let MispredictPenalty = 3;
  23   let CompleteModel = 0;
  24   let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
  25                              HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
  26                              HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
  27                              HasVInstructions];
  28 }
  29
  30 let SchedModel = SyntacoreSCR1Model in {
  31
  32 let BufferSize = 0 in {
  33 def SCR1_ALU : ProcResource<1>;
  34 def SCR1_LSU : ProcResource<1>;
  35 def SCR1_MUL : ProcResource<1>;
  36 def SCR1_DIV : ProcResource<1>;
  37 def SCR1_CFU : ProcResource<1>;
  38 }
  39
  40 // Branching
  41 def : WriteRes<WriteJmp, [SCR1_CFU]>;
  42 def : WriteRes<WriteJal, [SCR1_CFU]>;
  43 def : WriteRes<WriteJalr, [SCR1_CFU]>;
  44
  45 // Integer arithmetic and logic
  46 def : WriteRes<WriteIALU32, [SCR1_ALU]>;
  47 def : WriteRes<WriteIALU, [SCR1_ALU]>;
  48 def : WriteRes<WriteShiftImm32, [SCR1_ALU]>;
  49 def : WriteRes<WriteShiftImm, [SCR1_ALU]>;
  50 def : WriteRes<WriteShiftReg32, [SCR1_ALU]>;
  51 def : WriteRes<WriteShiftReg, [SCR1_ALU]>;
  52
  53 // Integer multiplication: single-cycle multiplier in SCR1_CFG_RV32IMC_MAX
  54 def : WriteRes<WriteIMul, [SCR1_MUL]>;
  55 def : WriteRes<WriteIMul32, [SCR1_MUL]>;
  56
  57 // Integer division: latency 33, inverse throughput 33
  58 let Latency = 33, ReleaseAtCycles = [33] in {
  59 def : WriteRes<WriteIDiv32, [SCR1_DIV]>;
  60 def : WriteRes<WriteIDiv, [SCR1_DIV]>;
  61 }
  62
  63 // Load/store instructions on SCR1 have latency 2 and inverse throughput 2
  64 // (SCR1_CFG_RV32IMC_MAX includes TCM)
  65 let Latency = 2, ReleaseAtCycles=[2] in {
  66 // Memory
  67 def : WriteRes<WriteSTB, [SCR1_LSU]>;
  68 def : WriteRes<WriteSTH, [SCR1_LSU]>;
  69 def : WriteRes<WriteSTW, [SCR1_LSU]>;
  70 def : WriteRes<WriteSTD, [SCR1_LSU]>;
  71 def : WriteRes<WriteLDB, [SCR1_LSU]>;
  72 def : WriteRes<WriteLDH, [SCR1_LSU]>;
  73 def : WriteRes<WriteLDW, [SCR1_LSU]>;
  74 def : WriteRes<WriteLDD, [SCR1_LSU]>;
  75 }
  76
  77 let Unsupported = true in {
  78 // Atomic memory
  79 def : WriteRes<WriteAtomicW, [SCR1_LSU]>;
  80 def : WriteRes<WriteAtomicD, [SCR1_LSU]>;
  81 def : WriteRes<WriteAtomicLDW, [SCR1_LSU]>;
  82 def : WriteRes<WriteAtomicLDD, [SCR1_LSU]>;
  83 def : WriteRes<WriteAtomicSTW, [SCR1_LSU]>;
  84 def : WriteRes<WriteAtomicSTD, [SCR1_LSU]>;
  85
  86 // FP load/store
  87 def : WriteRes<WriteFST32, [SCR1_LSU]>;
  88 def : WriteRes<WriteFST64, [SCR1_LSU]>;
  89 def : WriteRes<WriteFLD32, [SCR1_LSU]>;
  90 def : WriteRes<WriteFLD64, [SCR1_LSU]>;
  91
  92 // FP instructions
  93 def : WriteRes<WriteFAdd32, []>;
  94 def : WriteRes<WriteFSGNJ32, []>;
  95 def : WriteRes<WriteFMinMax32, []>;
  96 def : WriteRes<WriteFAdd64, []>;
  97 def : WriteRes<WriteFSGNJ64, []>;
  98 def : WriteRes<WriteFMinMax64, []>;
  99 def : WriteRes<WriteFCvtI32ToF32, []>;
 100 def : WriteRes<WriteFCvtI32ToF64, []>;
 101 def : WriteRes<WriteFCvtI64ToF32, []>;
 102 def : WriteRes<WriteFCvtI64ToF64, []>;
 103 def : WriteRes<WriteFCvtF32ToI32, []>;
 104 def : WriteRes<WriteFCvtF32ToI64, []>;
 105 def : WriteRes<WriteFCvtF64ToI32, []>;
 106 def : WriteRes<WriteFCvtF64ToI64, []>;
 107 def : WriteRes<WriteFCvtF32ToF64, []>;
 108 def : WriteRes<WriteFCvtF64ToF32, []>;
 109 def : WriteRes<WriteFClass32, []>;
 110 def : WriteRes<WriteFClass64, []>;
 111 def : WriteRes<WriteFCmp32, []>;
 112 def : WriteRes<WriteFCmp64, []>;
 113 def : WriteRes<WriteFMovF32ToI32, []>;
 114 def : WriteRes<WriteFMovI32ToF32, []>;
 115 def : WriteRes<WriteFMovF64ToI64, []>;
 116 def : WriteRes<WriteFMovI64ToF64, []>;
 117 def : WriteRes<WriteFMul32, []>;
 118 def : WriteRes<WriteFMA32, []>;
 119 def : WriteRes<WriteFMul64, []>;
 120 def : WriteRes<WriteFMA64, []>;
 121 def : WriteRes<WriteFDiv32, []>;
 122 def : WriteRes<WriteFDiv64, []>;
 123 def : WriteRes<WriteFSqrt32, []>;
 124 def : WriteRes<WriteFSqrt64, []>;
 125
 126 def : WriteRes<WriteSFB, []>;
 127 }
 128
 129 // Others
 130 def : WriteRes<WriteCSR, []>;
 131 def : WriteRes<WriteNop, []>;
 132
 133 def : InstRW<[WriteIALU], (instrs COPY)>;
 134
 135 //===----------------------------------------------------------------------===//
 136 // Bypasses (none)
 137 def : ReadAdvance<ReadJmp, 0>;
 138 def : ReadAdvance<ReadJalr, 0>;
 139 def : ReadAdvance<ReadCSR, 0>;
 140 def : ReadAdvance<ReadStoreData, 0>;
 141 def : ReadAdvance<ReadMemBase, 0>;
 142 def : ReadAdvance<ReadIALU, 0>;
 143 def : ReadAdvance<ReadIALU32, 0>;
 144 def : ReadAdvance<ReadShiftImm, 0>;
 145 def : ReadAdvance<ReadShiftImm32, 0>;
 146 def : ReadAdvance<ReadShiftReg, 0>;
 147 def : ReadAdvance<ReadShiftReg32, 0>;
 148 def : ReadAdvance<ReadIDiv, 0>;
 149 def : ReadAdvance<ReadIDiv32, 0>;
 150 def : ReadAdvance<ReadIMul, 0>;
 151 def : ReadAdvance<ReadIMul32, 0>;
 152 def : ReadAdvance<ReadAtomicWA, 0>;
 153 def : ReadAdvance<ReadAtomicWD, 0>;
 154 def : ReadAdvance<ReadAtomicDA, 0>;
 155 def : ReadAdvance<ReadAtomicDD, 0>;
 156 def : ReadAdvance<ReadAtomicLDW, 0>;
 157 def : ReadAdvance<ReadAtomicLDD, 0>;
 158 def : ReadAdvance<ReadAtomicSTW, 0>;
 159 def : ReadAdvance<ReadAtomicSTD, 0>;
 160 def : ReadAdvance<ReadFStoreData, 0>;
 161 def : ReadAdvance<ReadFMemBase, 0>;
 162 def : ReadAdvance<ReadFAdd32, 0>;
 163 def : ReadAdvance<ReadFAdd64, 0>;
 164 def : ReadAdvance<ReadFMul32, 0>;
 165 def : ReadAdvance<ReadFMul64, 0>;
 166 def : ReadAdvance<ReadFMA32, 0>;
 167 def : ReadAdvance<ReadFMA32Addend, 0>;
 168 def : ReadAdvance<ReadFMA64, 0>;
 169 def : ReadAdvance<ReadFMA64Addend, 0>;
 170 def : ReadAdvance<ReadFDiv32, 0>;
 171 def : ReadAdvance<ReadFDiv64, 0>;
 172 def : ReadAdvance<ReadFSqrt32, 0>;
 173 def : ReadAdvance<ReadFSqrt64, 0>;
 174 def : ReadAdvance<ReadFCmp32, 0>;
 175 def : ReadAdvance<ReadFCmp64, 0>;
 176 def : ReadAdvance<ReadFSGNJ32, 0>;
 177 def : ReadAdvance<ReadFSGNJ64, 0>;
 178 def : ReadAdvance<ReadFMinMax32, 0>;
 179 def : ReadAdvance<ReadFMinMax64, 0>;
 180 def : ReadAdvance<ReadFCvtF32ToI32, 0>;
 181 def : ReadAdvance<ReadFCvtF32ToI64, 0>;
 182 def : ReadAdvance<ReadFCvtF64ToI32, 0>;
 183 def : ReadAdvance<ReadFCvtF64ToI64, 0>;
 184 def : ReadAdvance<ReadFCvtI32ToF32, 0>;
 185 def : ReadAdvance<ReadFCvtI32ToF64, 0>;
 186 def : ReadAdvance<ReadFCvtI64ToF32, 0>;
 187 def : ReadAdvance<ReadFCvtI64ToF64, 0>;
 188 def : ReadAdvance<ReadFCvtF32ToF64, 0>;
 189 def : ReadAdvance<ReadFCvtF64ToF32, 0>;
 190 def : ReadAdvance<ReadFMovF32ToI32, 0>;
 191 def : ReadAdvance<ReadFMovI32ToF32, 0>;
 192 def : ReadAdvance<ReadFMovF64ToI64, 0>;
 193 def : ReadAdvance<ReadFMovI64ToF64, 0>;
 194 def : ReadAdvance<ReadFClass32, 0>;
 195 def : ReadAdvance<ReadFClass64, 0>;
 196 def : ReadAdvance<ReadSFBJmp, 0>;
 197 def : ReadAdvance<ReadSFBALU, 0>;
 198
 199 //===----------------------------------------------------------------------===//
 200 // Unsupported extensions
 201 defm : UnsupportedSchedV;
 202 defm : UnsupportedSchedZba;
 203 defm : UnsupportedSchedZbb;
 204 defm : UnsupportedSchedZbc;
 205 defm : UnsupportedSchedZbs;
 206 defm : UnsupportedSchedZbkb;
 207 defm : UnsupportedSchedZbkx;
 208 defm : UnsupportedSchedZfa;
 209 defm : UnsupportedSchedZfh;
 210 }