| blob | f17b9724aadba37b4b08af7a857be00d37934983 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3 ; RUN: llc -mtriple=aarch64-unknown-linux-gnu -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
5 define <8 x i8> @and8xi8(<8 x i8> %a, <8 x i8> %b) {
6 ; CHECK-LABEL: and8xi8:
7 ; CHECK: // %bb.0:
8 ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
9 ; CHECK-NEXT: ret
10 %tmp1 = and <8 x i8> %a, %b;
11 ret <8 x i8> %tmp1
12 }
14 define <16 x i8> @and16xi8(<16 x i8> %a, <16 x i8> %b) {
15 ; CHECK-LABEL: and16xi8:
16 ; CHECK: // %bb.0:
17 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
18 ; CHECK-NEXT: ret
19 %tmp1 = and <16 x i8> %a, %b;
20 ret <16 x i8> %tmp1
21 }
24 define <8 x i8> @orr8xi8(<8 x i8> %a, <8 x i8> %b) {
25 ; CHECK-LABEL: orr8xi8:
26 ; CHECK: // %bb.0:
27 ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
28 ; CHECK-NEXT: ret
29 %tmp1 = or <8 x i8> %a, %b;
30 ret <8 x i8> %tmp1
31 }
33 define <16 x i8> @orr16xi8(<16 x i8> %a, <16 x i8> %b) {
34 ; CHECK-LABEL: orr16xi8:
35 ; CHECK: // %bb.0:
36 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
37 ; CHECK-NEXT: ret
38 %tmp1 = or <16 x i8> %a, %b;
39 ret <16 x i8> %tmp1
40 }
43 define <8 x i8> @xor8xi8(<8 x i8> %a, <8 x i8> %b) {
44 ; CHECK-LABEL: xor8xi8:
45 ; CHECK: // %bb.0:
46 ; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
47 ; CHECK-NEXT: ret
48 %tmp1 = xor <8 x i8> %a, %b;
49 ret <8 x i8> %tmp1
50 }
52 define <16 x i8> @xor16xi8(<16 x i8> %a, <16 x i8> %b) {
53 ; CHECK-LABEL: xor16xi8:
54 ; CHECK: // %bb.0:
55 ; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
56 ; CHECK-NEXT: ret
57 %tmp1 = xor <16 x i8> %a, %b;
58 ret <16 x i8> %tmp1
59 }
61 define <8 x i8> @bsl8xi8_const(<8 x i8> %a, <8 x i8> %b) {
62 ; CHECK-SD-LABEL: bsl8xi8_const:
63 ; CHECK-SD: // %bb.0:
64 ; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff
65 ; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b
66 ; CHECK-SD-NEXT: ret
67 ;
68 ; CHECK-GI-LABEL: bsl8xi8_const:
69 ; CHECK-GI: // %bb.0:
70 ; CHECK-GI-NEXT: adrp x8, .LCPI6_0
71 ; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI6_0]
72 ; CHECK-GI-NEXT: bif v0.8b, v1.8b, v2.8b
73 ; CHECK-GI-NEXT: ret
74 %tmp1 = and <8 x i8> %a, < i8 -1, i8 -1, i8 0, i8 0, i8 -1, i8 -1, i8 0, i8 0 >
75 %tmp2 = and <8 x i8> %b, < i8 0, i8 0, i8 -1, i8 -1, i8 0, i8 0, i8 -1, i8 -1 >
76 %tmp3 = or <8 x i8> %tmp1, %tmp2
77 ret <8 x i8> %tmp3
78 }
80 define <16 x i8> @bsl16xi8_const(<16 x i8> %a, <16 x i8> %b) {
81 ; CHECK-SD-LABEL: bsl16xi8_const:
82 ; CHECK-SD: // %bb.0:
83 ; CHECK-SD-NEXT: movi v2.2d, #0x000000ffffffff
84 ; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b
85 ; CHECK-SD-NEXT: ret
86 ;
87 ; CHECK-GI-LABEL: bsl16xi8_const:
88 ; CHECK-GI: // %bb.0:
89 ; CHECK-GI-NEXT: adrp x8, .LCPI7_0
90 ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI7_0]
91 ; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
92 ; CHECK-GI-NEXT: ret
93 %tmp1 = and <16 x i8> %a, < i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0 >
94 %tmp2 = and <16 x i8> %b, < i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1 >
95 %tmp3 = or <16 x i8> %tmp1, %tmp2
96 ret <16 x i8> %tmp3
97 }
99 define <8 x i8> @orn8xi8(<8 x i8> %a, <8 x i8> %b) {
100 ; CHECK-LABEL: orn8xi8:
101 ; CHECK: // %bb.0:
102 ; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b
103 ; CHECK-NEXT: ret
104 %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
105 %tmp2 = or <8 x i8> %a, %tmp1
106 ret <8 x i8> %tmp2
107 }
109 define <16 x i8> @orn16xi8(<16 x i8> %a, <16 x i8> %b) {
110 ; CHECK-LABEL: orn16xi8:
111 ; CHECK: // %bb.0:
112 ; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b
113 ; CHECK-NEXT: ret
114 %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
115 %tmp2 = or <16 x i8> %a, %tmp1
116 ret <16 x i8> %tmp2
117 }
119 define <8 x i8> @bic8xi8(<8 x i8> %a, <8 x i8> %b) {
120 ; CHECK-LABEL: bic8xi8:
121 ; CHECK: // %bb.0:
122 ; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b
123 ; CHECK-NEXT: ret
124 %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
125 %tmp2 = and <8 x i8> %a, %tmp1
126 ret <8 x i8> %tmp2
127 }
129 define <16 x i8> @bic16xi8(<16 x i8> %a, <16 x i8> %b) {
130 ; CHECK-LABEL: bic16xi8:
131 ; CHECK: // %bb.0:
132 ; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b
133 ; CHECK-NEXT: ret
134 %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
135 %tmp2 = and <16 x i8> %a, %tmp1
136 ret <16 x i8> %tmp2
137 }
139 define <2 x i32> @orrimm2s_lsl0(<2 x i32> %a) {
140 ; CHECK-SD-LABEL: orrimm2s_lsl0:
141 ; CHECK-SD: // %bb.0:
142 ; CHECK-SD-NEXT: orr v0.2s, #255
143 ; CHECK-SD-NEXT: ret
144 ;
145 ; CHECK-GI-LABEL: orrimm2s_lsl0:
146 ; CHECK-GI: // %bb.0:
147 ; CHECK-GI-NEXT: movi d1, #0x0000ff000000ff
148 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
149 ; CHECK-GI-NEXT: ret
150 %tmp1 = or <2 x i32> %a, < i32 255, i32 255>
151 ret <2 x i32> %tmp1
152 }
154 define <2 x i32> @orrimm2s_lsl8(<2 x i32> %a) {
155 ; CHECK-SD-LABEL: orrimm2s_lsl8:
156 ; CHECK-SD: // %bb.0:
157 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #8
158 ; CHECK-SD-NEXT: ret
159 ;
160 ; CHECK-GI-LABEL: orrimm2s_lsl8:
161 ; CHECK-GI: // %bb.0:
162 ; CHECK-GI-NEXT: movi d1, #0x00ff000000ff00
163 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
164 ; CHECK-GI-NEXT: ret
165 %tmp1 = or <2 x i32> %a, < i32 65280, i32 65280>
166 ret <2 x i32> %tmp1
167 }
169 define <2 x i32> @orrimm2s_lsl16(<2 x i32> %a) {
170 ; CHECK-SD-LABEL: orrimm2s_lsl16:
171 ; CHECK-SD: // %bb.0:
172 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #16
173 ; CHECK-SD-NEXT: ret
174 ;
175 ; CHECK-GI-LABEL: orrimm2s_lsl16:
176 ; CHECK-GI: // %bb.0:
177 ; CHECK-GI-NEXT: movi d1, #0xff000000ff0000
178 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
179 ; CHECK-GI-NEXT: ret
180 %tmp1 = or <2 x i32> %a, < i32 16711680, i32 16711680>
181 ret <2 x i32> %tmp1
182 }
184 define <2 x i32> @orrimm2s_lsl24(<2 x i32> %a) {
185 ; CHECK-SD-LABEL: orrimm2s_lsl24:
186 ; CHECK-SD: // %bb.0:
187 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #24
188 ; CHECK-SD-NEXT: ret
189 ;
190 ; CHECK-GI-LABEL: orrimm2s_lsl24:
191 ; CHECK-GI: // %bb.0:
192 ; CHECK-GI-NEXT: movi d1, #0xff000000ff000000
193 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
194 ; CHECK-GI-NEXT: ret
195 %tmp1 = or <2 x i32> %a, < i32 4278190080, i32 4278190080>
196 ret <2 x i32> %tmp1
197 }
199 define <4 x i32> @orrimm4s_lsl0(<4 x i32> %a) {
200 ; CHECK-SD-LABEL: orrimm4s_lsl0:
201 ; CHECK-SD: // %bb.0:
202 ; CHECK-SD-NEXT: orr v0.4s, #255
203 ; CHECK-SD-NEXT: ret
204 ;
205 ; CHECK-GI-LABEL: orrimm4s_lsl0:
206 ; CHECK-GI: // %bb.0:
207 ; CHECK-GI-NEXT: movi v1.2d, #0x0000ff000000ff
208 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
209 ; CHECK-GI-NEXT: ret
210 %tmp1 = or <4 x i32> %a, < i32 255, i32 255, i32 255, i32 255>
211 ret <4 x i32> %tmp1
212 }
214 define <4 x i32> @orrimm4s_lsl8(<4 x i32> %a) {
215 ; CHECK-SD-LABEL: orrimm4s_lsl8:
216 ; CHECK-SD: // %bb.0:
217 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #8
218 ; CHECK-SD-NEXT: ret
219 ;
220 ; CHECK-GI-LABEL: orrimm4s_lsl8:
221 ; CHECK-GI: // %bb.0:
222 ; CHECK-GI-NEXT: movi v1.2d, #0x00ff000000ff00
223 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
224 ; CHECK-GI-NEXT: ret
225 %tmp1 = or <4 x i32> %a, < i32 65280, i32 65280, i32 65280, i32 65280>
226 ret <4 x i32> %tmp1
227 }
229 define <4 x i32> @orrimm4s_lsl16(<4 x i32> %a) {
230 ; CHECK-SD-LABEL: orrimm4s_lsl16:
231 ; CHECK-SD: // %bb.0:
232 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #16
233 ; CHECK-SD-NEXT: ret
234 ;
235 ; CHECK-GI-LABEL: orrimm4s_lsl16:
236 ; CHECK-GI: // %bb.0:
237 ; CHECK-GI-NEXT: movi v1.2d, #0xff000000ff0000
238 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
239 ; CHECK-GI-NEXT: ret
240 %tmp1 = or <4 x i32> %a, < i32 16711680, i32 16711680, i32 16711680, i32 16711680>
241 ret <4 x i32> %tmp1
242 }
244 define <4 x i32> @orrimm4s_lsl24(<4 x i32> %a) {
245 ; CHECK-SD-LABEL: orrimm4s_lsl24:
246 ; CHECK-SD: // %bb.0:
247 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #24
248 ; CHECK-SD-NEXT: ret
249 ;
250 ; CHECK-GI-LABEL: orrimm4s_lsl24:
251 ; CHECK-GI: // %bb.0:
252 ; CHECK-GI-NEXT: movi v1.2d, #0xff000000ff000000
253 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
254 ; CHECK-GI-NEXT: ret
255 %tmp1 = or <4 x i32> %a, < i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080>
256 ret <4 x i32> %tmp1
257 }
259 define <4 x i16> @orrimm4h_lsl0(<4 x i16> %a) {
260 ; CHECK-SD-LABEL: orrimm4h_lsl0:
261 ; CHECK-SD: // %bb.0:
262 ; CHECK-SD-NEXT: orr v0.4h, #255
263 ; CHECK-SD-NEXT: ret
264 ;
265 ; CHECK-GI-LABEL: orrimm4h_lsl0:
266 ; CHECK-GI: // %bb.0:
267 ; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff
268 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
269 ; CHECK-GI-NEXT: ret
270 %tmp1 = or <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255 >
271 ret <4 x i16> %tmp1
272 }
274 define <4 x i16> @orrimm4h_lsl8(<4 x i16> %a) {
275 ; CHECK-SD-LABEL: orrimm4h_lsl8:
276 ; CHECK-SD: // %bb.0:
277 ; CHECK-SD-NEXT: orr v0.4h, #255, lsl #8
278 ; CHECK-SD-NEXT: ret
279 ;
280 ; CHECK-GI-LABEL: orrimm4h_lsl8:
281 ; CHECK-GI: // %bb.0:
282 ; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff00
283 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
284 ; CHECK-GI-NEXT: ret
285 %tmp1 = or <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 >
286 ret <4 x i16> %tmp1
287 }
289 define <8 x i16> @orrimm8h_lsl0(<8 x i16> %a) {
290 ; CHECK-SD-LABEL: orrimm8h_lsl0:
291 ; CHECK-SD: // %bb.0:
292 ; CHECK-SD-NEXT: orr v0.8h, #255
293 ; CHECK-SD-NEXT: ret
294 ;
295 ; CHECK-GI-LABEL: orrimm8h_lsl0:
296 ; CHECK-GI: // %bb.0:
297 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff
298 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
299 ; CHECK-GI-NEXT: ret
300 %tmp1 = or <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255 >
301 ret <8 x i16> %tmp1
302 }
304 define <8 x i16> @orrimm8h_lsl8(<8 x i16> %a) {
305 ; CHECK-SD-LABEL: orrimm8h_lsl8:
306 ; CHECK-SD: // %bb.0:
307 ; CHECK-SD-NEXT: orr v0.8h, #255, lsl #8
308 ; CHECK-SD-NEXT: ret
309 ;
310 ; CHECK-GI-LABEL: orrimm8h_lsl8:
311 ; CHECK-GI: // %bb.0:
312 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff00
313 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
314 ; CHECK-GI-NEXT: ret
315 %tmp1 = or <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
316 ret <8 x i16> %tmp1
317 }
319 define <2 x i32> @bicimm2s_lsl0(<2 x i32> %a) {
320 ; CHECK-SD-LABEL: bicimm2s_lsl0:
321 ; CHECK-SD: // %bb.0:
322 ; CHECK-SD-NEXT: bic v0.2s, #16
323 ; CHECK-SD-NEXT: ret
324 ;
325 ; CHECK-GI-LABEL: bicimm2s_lsl0:
326 ; CHECK-GI: // %bb.0:
327 ; CHECK-GI-NEXT: mvni v1.2s, #16
328 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
329 ; CHECK-GI-NEXT: ret
330 %tmp1 = and <2 x i32> %a, < i32 4294967279, i32 4294967279 >
331 ret <2 x i32> %tmp1
332 }
334 define <2 x i32> @bicimm2s_lsl8(<2 x i32> %a) {
335 ; CHECK-SD-LABEL: bicimm2s_lsl8:
336 ; CHECK-SD: // %bb.0:
337 ; CHECK-SD-NEXT: bic v0.2s, #16, lsl #8
338 ; CHECK-SD-NEXT: ret
339 ;
340 ; CHECK-GI-LABEL: bicimm2s_lsl8:
341 ; CHECK-GI: // %bb.0:
342 ; CHECK-GI-NEXT: mvni v1.2s, #16, lsl #8
343 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
344 ; CHECK-GI-NEXT: ret
345 %tmp1 = and <2 x i32> %a, < i32 4294963199, i32 4294963199 >
346 ret <2 x i32> %tmp1
347 }
349 define <2 x i32> @bicimm2s_lsl16(<2 x i32> %a) {
350 ; CHECK-SD-LABEL: bicimm2s_lsl16:
351 ; CHECK-SD: // %bb.0:
352 ; CHECK-SD-NEXT: bic v0.2s, #16, lsl #16
353 ; CHECK-SD-NEXT: ret
354 ;
355 ; CHECK-GI-LABEL: bicimm2s_lsl16:
356 ; CHECK-GI: // %bb.0:
357 ; CHECK-GI-NEXT: mvni v1.2s, #16, lsl #16
358 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
359 ; CHECK-GI-NEXT: ret
360 %tmp1 = and <2 x i32> %a, < i32 4293918719, i32 4293918719 >
361 ret <2 x i32> %tmp1
362 }
364 define <2 x i32> @bicimm2s_lsl124(<2 x i32> %a) {
365 ; CHECK-SD-LABEL: bicimm2s_lsl124:
366 ; CHECK-SD: // %bb.0:
367 ; CHECK-SD-NEXT: bic v0.2s, #16, lsl #24
368 ; CHECK-SD-NEXT: ret
369 ;
370 ; CHECK-GI-LABEL: bicimm2s_lsl124:
371 ; CHECK-GI: // %bb.0:
372 ; CHECK-GI-NEXT: mvni v1.2s, #16, lsl #24
373 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
374 ; CHECK-GI-NEXT: ret
375 %tmp1 = and <2 x i32> %a, < i32 4026531839, i32 4026531839>
376 ret <2 x i32> %tmp1
377 }
379 define <4 x i32> @bicimm4s_lsl0(<4 x i32> %a) {
380 ; CHECK-SD-LABEL: bicimm4s_lsl0:
381 ; CHECK-SD: // %bb.0:
382 ; CHECK-SD-NEXT: bic v0.4s, #16
383 ; CHECK-SD-NEXT: ret
384 ;
385 ; CHECK-GI-LABEL: bicimm4s_lsl0:
386 ; CHECK-GI: // %bb.0:
387 ; CHECK-GI-NEXT: mvni v1.4s, #16
388 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
389 ; CHECK-GI-NEXT: ret
390 %tmp1 = and <4 x i32> %a, < i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279 >
391 ret <4 x i32> %tmp1
392 }
394 define <4 x i32> @bicimm4s_lsl8(<4 x i32> %a) {
395 ; CHECK-SD-LABEL: bicimm4s_lsl8:
396 ; CHECK-SD: // %bb.0:
397 ; CHECK-SD-NEXT: bic v0.4s, #16, lsl #8
398 ; CHECK-SD-NEXT: ret
399 ;
400 ; CHECK-GI-LABEL: bicimm4s_lsl8:
401 ; CHECK-GI: // %bb.0:
402 ; CHECK-GI-NEXT: mvni v1.4s, #16, lsl #8
403 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
404 ; CHECK-GI-NEXT: ret
405 %tmp1 = and <4 x i32> %a, < i32 4294963199, i32 4294963199, i32 4294963199, i32 4294963199 >
406 ret <4 x i32> %tmp1
407 }
409 define <4 x i32> @bicimm4s_lsl16(<4 x i32> %a) {
410 ; CHECK-SD-LABEL: bicimm4s_lsl16:
411 ; CHECK-SD: // %bb.0:
412 ; CHECK-SD-NEXT: bic v0.4s, #16, lsl #16
413 ; CHECK-SD-NEXT: ret
414 ;
415 ; CHECK-GI-LABEL: bicimm4s_lsl16:
416 ; CHECK-GI: // %bb.0:
417 ; CHECK-GI-NEXT: mvni v1.4s, #16, lsl #16
418 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
419 ; CHECK-GI-NEXT: ret
420 %tmp1 = and <4 x i32> %a, < i32 4293918719, i32 4293918719, i32 4293918719, i32 4293918719 >
421 ret <4 x i32> %tmp1
422 }
424 define <4 x i32> @bicimm4s_lsl124(<4 x i32> %a) {
425 ; CHECK-SD-LABEL: bicimm4s_lsl124:
426 ; CHECK-SD: // %bb.0:
427 ; CHECK-SD-NEXT: bic v0.4s, #16, lsl #24
428 ; CHECK-SD-NEXT: ret
429 ;
430 ; CHECK-GI-LABEL: bicimm4s_lsl124:
431 ; CHECK-GI: // %bb.0:
432 ; CHECK-GI-NEXT: mvni v1.4s, #16, lsl #24
433 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
434 ; CHECK-GI-NEXT: ret
435 %tmp1 = and <4 x i32> %a, < i32 4026531839, i32 4026531839, i32 4026531839, i32 4026531839>
436 ret <4 x i32> %tmp1
437 }
439 define <4 x i16> @bicimm4h_lsl0_a(<4 x i16> %a) {
440 ; CHECK-SD-LABEL: bicimm4h_lsl0_a:
441 ; CHECK-SD: // %bb.0:
442 ; CHECK-SD-NEXT: bic v0.4h, #16
443 ; CHECK-SD-NEXT: ret
444 ;
445 ; CHECK-GI-LABEL: bicimm4h_lsl0_a:
446 ; CHECK-GI: // %bb.0:
447 ; CHECK-GI-NEXT: mvni v1.4h, #16
448 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
449 ; CHECK-GI-NEXT: ret
450 %tmp1 = and <4 x i16> %a, < i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279 >
451 ret <4 x i16> %tmp1
452 }
454 define <4 x i16> @bicimm4h_lsl0_b(<4 x i16> %a) {
455 ; CHECK-SD-LABEL: bicimm4h_lsl0_b:
456 ; CHECK-SD: // %bb.0:
457 ; CHECK-SD-NEXT: bic v0.4h, #255
458 ; CHECK-SD-NEXT: ret
459 ;
460 ; CHECK-GI-LABEL: bicimm4h_lsl0_b:
461 ; CHECK-GI: // %bb.0:
462 ; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff00
463 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
464 ; CHECK-GI-NEXT: ret
465 %tmp1 = and <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 >
466 ret <4 x i16> %tmp1
467 }
469 define <4 x i16> @bicimm4h_lsl8_a(<4 x i16> %a) {
470 ; CHECK-SD-LABEL: bicimm4h_lsl8_a:
471 ; CHECK-SD: // %bb.0:
472 ; CHECK-SD-NEXT: bic v0.4h, #16, lsl #8
473 ; CHECK-SD-NEXT: ret
474 ;
475 ; CHECK-GI-LABEL: bicimm4h_lsl8_a:
476 ; CHECK-GI: // %bb.0:
477 ; CHECK-GI-NEXT: mvni v1.4h, #16, lsl #8
478 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
479 ; CHECK-GI-NEXT: ret
480 %tmp1 = and <4 x i16> %a, < i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199>
481 ret <4 x i16> %tmp1
482 }
484 define <4 x i16> @bicimm4h_lsl8_b(<4 x i16> %a) {
485 ; CHECK-SD-LABEL: bicimm4h_lsl8_b:
486 ; CHECK-SD: // %bb.0:
487 ; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
488 ; CHECK-SD-NEXT: ret
489 ;
490 ; CHECK-GI-LABEL: bicimm4h_lsl8_b:
491 ; CHECK-GI: // %bb.0:
492 ; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff
493 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
494 ; CHECK-GI-NEXT: ret
495 %tmp1 = and <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255>
496 ret <4 x i16> %tmp1
497 }
499 define <8 x i16> @bicimm8h_lsl0_a(<8 x i16> %a) {
500 ; CHECK-SD-LABEL: bicimm8h_lsl0_a:
501 ; CHECK-SD: // %bb.0:
502 ; CHECK-SD-NEXT: bic v0.8h, #16
503 ; CHECK-SD-NEXT: ret
504 ;
505 ; CHECK-GI-LABEL: bicimm8h_lsl0_a:
506 ; CHECK-GI: // %bb.0:
507 ; CHECK-GI-NEXT: mvni v1.8h, #16
508 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
509 ; CHECK-GI-NEXT: ret
510 %tmp1 = and <8 x i16> %a, < i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279,
511 i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279 >
512 ret <8 x i16> %tmp1
513 }
515 define <8 x i16> @bicimm8h_lsl0_b(<8 x i16> %a) {
516 ; CHECK-SD-LABEL: bicimm8h_lsl0_b:
517 ; CHECK-SD: // %bb.0:
518 ; CHECK-SD-NEXT: bic v0.8h, #255
519 ; CHECK-SD-NEXT: ret
520 ;
521 ; CHECK-GI-LABEL: bicimm8h_lsl0_b:
522 ; CHECK-GI: // %bb.0:
523 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff00
524 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
525 ; CHECK-GI-NEXT: ret
526 %tmp1 = and <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
527 ret <8 x i16> %tmp1
528 }
530 define <8 x i16> @bicimm8h_lsl8_a(<8 x i16> %a) {
531 ; CHECK-SD-LABEL: bicimm8h_lsl8_a:
532 ; CHECK-SD: // %bb.0:
533 ; CHECK-SD-NEXT: bic v0.8h, #16, lsl #8
534 ; CHECK-SD-NEXT: ret
535 ;
536 ; CHECK-GI-LABEL: bicimm8h_lsl8_a:
537 ; CHECK-GI: // %bb.0:
538 ; CHECK-GI-NEXT: mvni v1.8h, #16, lsl #8
539 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
540 ; CHECK-GI-NEXT: ret
541 %tmp1 = and <8 x i16> %a, < i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199,
542 i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199>
543 ret <8 x i16> %tmp1
544 }
546 define <8 x i16> @bicimm8h_lsl8_b(<8 x i16> %a) {
547 ; CHECK-SD-LABEL: bicimm8h_lsl8_b:
548 ; CHECK-SD: // %bb.0:
549 ; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8
550 ; CHECK-SD-NEXT: ret
551 ;
552 ; CHECK-GI-LABEL: bicimm8h_lsl8_b:
553 ; CHECK-GI: // %bb.0:
554 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff
555 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
556 ; CHECK-GI-NEXT: ret
557 %tmp1 = and <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
558 ret <8 x i16> %tmp1
559 }
561 define <2 x i32> @and2xi32(<2 x i32> %a, <2 x i32> %b) {
562 ; CHECK-LABEL: and2xi32:
563 ; CHECK: // %bb.0:
564 ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
565 ; CHECK-NEXT: ret
566 %tmp1 = and <2 x i32> %a, %b;
567 ret <2 x i32> %tmp1
568 }
570 define <4 x i16> @and4xi16(<4 x i16> %a, <4 x i16> %b) {
571 ; CHECK-LABEL: and4xi16:
572 ; CHECK: // %bb.0:
573 ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
574 ; CHECK-NEXT: ret
575 %tmp1 = and <4 x i16> %a, %b;
576 ret <4 x i16> %tmp1
577 }
579 define <1 x i64> @and1xi64(<1 x i64> %a, <1 x i64> %b) {
580 ; CHECK-SD-LABEL: and1xi64:
581 ; CHECK-SD: // %bb.0:
582 ; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
583 ; CHECK-SD-NEXT: ret
584 ;
585 ; CHECK-GI-LABEL: and1xi64:
586 ; CHECK-GI: // %bb.0:
587 ; CHECK-GI-NEXT: fmov x8, d0
588 ; CHECK-GI-NEXT: fmov x9, d1
589 ; CHECK-GI-NEXT: and x8, x8, x9
590 ; CHECK-GI-NEXT: fmov d0, x8
591 ; CHECK-GI-NEXT: ret
592 %tmp1 = and <1 x i64> %a, %b;
593 ret <1 x i64> %tmp1
594 }
596 define <4 x i32> @and4xi32(<4 x i32> %a, <4 x i32> %b) {
597 ; CHECK-LABEL: and4xi32:
598 ; CHECK: // %bb.0:
599 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
600 ; CHECK-NEXT: ret
601 %tmp1 = and <4 x i32> %a, %b;
602 ret <4 x i32> %tmp1
603 }
605 define <8 x i16> @and8xi16(<8 x i16> %a, <8 x i16> %b) {
606 ; CHECK-LABEL: and8xi16:
607 ; CHECK: // %bb.0:
608 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
609 ; CHECK-NEXT: ret
610 %tmp1 = and <8 x i16> %a, %b;
611 ret <8 x i16> %tmp1
612 }
614 define <2 x i64> @and2xi64(<2 x i64> %a, <2 x i64> %b) {
615 ; CHECK-LABEL: and2xi64:
616 ; CHECK: // %bb.0:
617 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
618 ; CHECK-NEXT: ret
619 %tmp1 = and <2 x i64> %a, %b;
620 ret <2 x i64> %tmp1
621 }
623 define <2 x i32> @orr2xi32(<2 x i32> %a, <2 x i32> %b) {
624 ; CHECK-LABEL: orr2xi32:
625 ; CHECK: // %bb.0:
626 ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
627 ; CHECK-NEXT: ret
628 %tmp1 = or <2 x i32> %a, %b;
629 ret <2 x i32> %tmp1
630 }
632 define <4 x i16> @orr4xi16(<4 x i16> %a, <4 x i16> %b) {
633 ; CHECK-LABEL: orr4xi16:
634 ; CHECK: // %bb.0:
635 ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
636 ; CHECK-NEXT: ret
637 %tmp1 = or <4 x i16> %a, %b;
638 ret <4 x i16> %tmp1
639 }
641 define <1 x i64> @orr1xi64(<1 x i64> %a, <1 x i64> %b) {
642 ; CHECK-SD-LABEL: orr1xi64:
643 ; CHECK-SD: // %bb.0:
644 ; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
645 ; CHECK-SD-NEXT: ret
646 ;
647 ; CHECK-GI-LABEL: orr1xi64:
648 ; CHECK-GI: // %bb.0:
649 ; CHECK-GI-NEXT: fmov x8, d0
650 ; CHECK-GI-NEXT: fmov x9, d1
651 ; CHECK-GI-NEXT: orr x8, x8, x9
652 ; CHECK-GI-NEXT: fmov d0, x8
653 ; CHECK-GI-NEXT: ret
654 %tmp1 = or <1 x i64> %a, %b;
655 ret <1 x i64> %tmp1
656 }
658 define <4 x i32> @orr4xi32(<4 x i32> %a, <4 x i32> %b) {
659 ; CHECK-LABEL: orr4xi32:
660 ; CHECK: // %bb.0:
661 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
662 ; CHECK-NEXT: ret
663 %tmp1 = or <4 x i32> %a, %b;
664 ret <4 x i32> %tmp1
665 }
667 define <8 x i16> @orr8xi16(<8 x i16> %a, <8 x i16> %b) {
668 ; CHECK-LABEL: orr8xi16:
669 ; CHECK: // %bb.0:
670 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
671 ; CHECK-NEXT: ret
672 %tmp1 = or <8 x i16> %a, %b;
673 ret <8 x i16> %tmp1
674 }
676 define <2 x i64> @orr2xi64(<2 x i64> %a, <2 x i64> %b) {
677 ; CHECK-LABEL: orr2xi64:
678 ; CHECK: // %bb.0:
679 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
680 ; CHECK-NEXT: ret
681 %tmp1 = or <2 x i64> %a, %b;
682 ret <2 x i64> %tmp1
683 }
685 define <2 x i32> @eor2xi32(<2 x i32> %a, <2 x i32> %b) {
686 ; CHECK-LABEL: eor2xi32:
687 ; CHECK: // %bb.0:
688 ; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
689 ; CHECK-NEXT: ret
690 %tmp1 = xor <2 x i32> %a, %b;
691 ret <2 x i32> %tmp1
692 }
694 define <4 x i16> @eor4xi16(<4 x i16> %a, <4 x i16> %b) {
695 ; CHECK-LABEL: eor4xi16:
696 ; CHECK: // %bb.0:
697 ; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
698 ; CHECK-NEXT: ret
699 %tmp1 = xor <4 x i16> %a, %b;
700 ret <4 x i16> %tmp1
701 }
703 define <1 x i64> @eor1xi64(<1 x i64> %a, <1 x i64> %b) {
704 ; CHECK-SD-LABEL: eor1xi64:
705 ; CHECK-SD: // %bb.0:
706 ; CHECK-SD-NEXT: eor v0.8b, v0.8b, v1.8b
707 ; CHECK-SD-NEXT: ret
708 ;
709 ; CHECK-GI-LABEL: eor1xi64:
710 ; CHECK-GI: // %bb.0:
711 ; CHECK-GI-NEXT: fmov x8, d0
712 ; CHECK-GI-NEXT: fmov x9, d1
713 ; CHECK-GI-NEXT: eor x8, x8, x9
714 ; CHECK-GI-NEXT: fmov d0, x8
715 ; CHECK-GI-NEXT: ret
716 %tmp1 = xor <1 x i64> %a, %b;
717 ret <1 x i64> %tmp1
718 }
720 define <4 x i32> @eor4xi32(<4 x i32> %a, <4 x i32> %b) {
721 ; CHECK-LABEL: eor4xi32:
722 ; CHECK: // %bb.0:
723 ; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
724 ; CHECK-NEXT: ret
725 %tmp1 = xor <4 x i32> %a, %b;
726 ret <4 x i32> %tmp1
727 }
729 define <8 x i16> @eor8xi16(<8 x i16> %a, <8 x i16> %b) {
730 ; CHECK-LABEL: eor8xi16:
731 ; CHECK: // %bb.0:
732 ; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
733 ; CHECK-NEXT: ret
734 %tmp1 = xor <8 x i16> %a, %b;
735 ret <8 x i16> %tmp1
736 }
738 define <2 x i64> @eor2xi64(<2 x i64> %a, <2 x i64> %b) {
739 ; CHECK-LABEL: eor2xi64:
740 ; CHECK: // %bb.0:
741 ; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
742 ; CHECK-NEXT: ret
743 %tmp1 = xor <2 x i64> %a, %b;
744 ret <2 x i64> %tmp1
745 }
748 define <2 x i32> @bic2xi32(<2 x i32> %a, <2 x i32> %b) {
749 ; CHECK-LABEL: bic2xi32:
750 ; CHECK: // %bb.0:
751 ; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b
752 ; CHECK-NEXT: ret
753 %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 >
754 %tmp2 = and <2 x i32> %a, %tmp1
755 ret <2 x i32> %tmp2
756 }
758 define <4 x i16> @bic4xi16(<4 x i16> %a, <4 x i16> %b) {
759 ; CHECK-LABEL: bic4xi16:
760 ; CHECK: // %bb.0:
761 ; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b
762 ; CHECK-NEXT: ret
763 %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 >
764 %tmp2 = and <4 x i16> %a, %tmp1
765 ret <4 x i16> %tmp2
766 }
768 define <1 x i64> @bic1xi64(<1 x i64> %a, <1 x i64> %b) {
769 ; CHECK-SD-LABEL: bic1xi64:
770 ; CHECK-SD: // %bb.0:
771 ; CHECK-SD-NEXT: bic v0.8b, v0.8b, v1.8b
772 ; CHECK-SD-NEXT: ret
773 ;
774 ; CHECK-GI-LABEL: bic1xi64:
775 ; CHECK-GI: // %bb.0:
776 ; CHECK-GI-NEXT: fmov x8, d1
777 ; CHECK-GI-NEXT: fmov x9, d0
778 ; CHECK-GI-NEXT: bic x8, x9, x8
779 ; CHECK-GI-NEXT: fmov d0, x8
780 ; CHECK-GI-NEXT: ret
781 %tmp1 = xor <1 x i64> %b, < i64 -1>
782 %tmp2 = and <1 x i64> %a, %tmp1
783 ret <1 x i64> %tmp2
784 }
786 define <4 x i32> @bic4xi32(<4 x i32> %a, <4 x i32> %b) {
787 ; CHECK-LABEL: bic4xi32:
788 ; CHECK: // %bb.0:
789 ; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b
790 ; CHECK-NEXT: ret
791 %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1>
792 %tmp2 = and <4 x i32> %a, %tmp1
793 ret <4 x i32> %tmp2
794 }
796 define <8 x i16> @bic8xi16(<8 x i16> %a, <8 x i16> %b) {
797 ; CHECK-LABEL: bic8xi16:
798 ; CHECK: // %bb.0:
799 ; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b
800 ; CHECK-NEXT: ret
801 %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 >
802 %tmp2 = and <8 x i16> %a, %tmp1
803 ret <8 x i16> %tmp2
804 }
806 define <2 x i64> @bic2xi64(<2 x i64> %a, <2 x i64> %b) {
807 ; CHECK-LABEL: bic2xi64:
808 ; CHECK: // %bb.0:
809 ; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b
810 ; CHECK-NEXT: ret
811 %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1>
812 %tmp2 = and <2 x i64> %a, %tmp1
813 ret <2 x i64> %tmp2
814 }
816 define <2 x i32> @orn2xi32(<2 x i32> %a, <2 x i32> %b) {
817 ; CHECK-LABEL: orn2xi32:
818 ; CHECK: // %bb.0:
819 ; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b
820 ; CHECK-NEXT: ret
821 %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 >
822 %tmp2 = or <2 x i32> %a, %tmp1
823 ret <2 x i32> %tmp2
824 }
826 define <4 x i16> @orn4xi16(<4 x i16> %a, <4 x i16> %b) {
827 ; CHECK-LABEL: orn4xi16:
828 ; CHECK: // %bb.0:
829 ; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b
830 ; CHECK-NEXT: ret
831 %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 >
832 %tmp2 = or <4 x i16> %a, %tmp1
833 ret <4 x i16> %tmp2
834 }
836 define <1 x i64> @orn1xi64(<1 x i64> %a, <1 x i64> %b) {
837 ; CHECK-SD-LABEL: orn1xi64:
838 ; CHECK-SD: // %bb.0:
839 ; CHECK-SD-NEXT: orn v0.8b, v0.8b, v1.8b
840 ; CHECK-SD-NEXT: ret
841 ;
842 ; CHECK-GI-LABEL: orn1xi64:
843 ; CHECK-GI: // %bb.0:
844 ; CHECK-GI-NEXT: fmov x8, d1
845 ; CHECK-GI-NEXT: fmov x9, d0
846 ; CHECK-GI-NEXT: orn x8, x9, x8
847 ; CHECK-GI-NEXT: fmov d0, x8
848 ; CHECK-GI-NEXT: ret
849 %tmp1 = xor <1 x i64> %b, < i64 -1>
850 %tmp2 = or <1 x i64> %a, %tmp1
851 ret <1 x i64> %tmp2
852 }
854 define <4 x i32> @orn4xi32(<4 x i32> %a, <4 x i32> %b) {
855 ; CHECK-LABEL: orn4xi32:
856 ; CHECK: // %bb.0:
857 ; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b
858 ; CHECK-NEXT: ret
859 %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1>
860 %tmp2 = or <4 x i32> %a, %tmp1
861 ret <4 x i32> %tmp2
862 }
864 define <8 x i16> @orn8xi16(<8 x i16> %a, <8 x i16> %b) {
865 ; CHECK-LABEL: orn8xi16:
866 ; CHECK: // %bb.0:
867 ; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b
868 ; CHECK-NEXT: ret
869 %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 >
870 %tmp2 = or <8 x i16> %a, %tmp1
871 ret <8 x i16> %tmp2
872 }
874 define <2 x i64> @orn2xi64(<2 x i64> %a, <2 x i64> %b) {
875 ; CHECK-LABEL: orn2xi64:
876 ; CHECK: // %bb.0:
877 ; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b
878 ; CHECK-NEXT: ret
879 %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1>
880 %tmp2 = or <2 x i64> %a, %tmp1
881 ret <2 x i64> %tmp2
882 }
884 define <2 x i32> @bsl2xi32_const(<2 x i32> %a, <2 x i32> %b) {
885 ; CHECK-SD-LABEL: bsl2xi32_const:
886 ; CHECK-SD: // %bb.0:
887 ; CHECK-SD-NEXT: movi d2, #0x000000ffffffff
888 ; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b
889 ; CHECK-SD-NEXT: ret
890 ;
891 ; CHECK-GI-LABEL: bsl2xi32_const:
892 ; CHECK-GI: // %bb.0:
893 ; CHECK-GI-NEXT: adrp x8, .LCPI70_0
894 ; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI70_0]
895 ; CHECK-GI-NEXT: bif v0.8b, v1.8b, v2.8b
896 ; CHECK-GI-NEXT: ret
897 %tmp1 = and <2 x i32> %a, < i32 -1, i32 0 >
898 %tmp2 = and <2 x i32> %b, < i32 0, i32 -1 >
899 %tmp3 = or <2 x i32> %tmp1, %tmp2
900 ret <2 x i32> %tmp3
901 }
904 define <4 x i16> @bsl4xi16_const(<4 x i16> %a, <4 x i16> %b) {
905 ; CHECK-SD-LABEL: bsl4xi16_const:
906 ; CHECK-SD: // %bb.0:
907 ; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff
908 ; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b
909 ; CHECK-SD-NEXT: ret
910 ;
911 ; CHECK-GI-LABEL: bsl4xi16_const:
912 ; CHECK-GI: // %bb.0:
913 ; CHECK-GI-NEXT: adrp x8, .LCPI71_0
914 ; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI71_0]
915 ; CHECK-GI-NEXT: bif v0.8b, v1.8b, v2.8b
916 ; CHECK-GI-NEXT: ret
917 %tmp1 = and <4 x i16> %a, < i16 -1, i16 0, i16 -1,i16 0 >
918 %tmp2 = and <4 x i16> %b, < i16 0, i16 -1,i16 0, i16 -1 >
919 %tmp3 = or <4 x i16> %tmp1, %tmp2
920 ret <4 x i16> %tmp3
921 }
923 define <1 x i64> @bsl1xi64_const(<1 x i64> %a, <1 x i64> %b) {
924 ; CHECK-SD-LABEL: bsl1xi64_const:
925 ; CHECK-SD: // %bb.0:
926 ; CHECK-SD-NEXT: movi d2, #0xffffffffffffff00
927 ; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b
928 ; CHECK-SD-NEXT: ret
929 ;
930 ; CHECK-GI-LABEL: bsl1xi64_const:
931 ; CHECK-GI: // %bb.0:
932 ; CHECK-GI-NEXT: fmov x8, d0
933 ; CHECK-GI-NEXT: fmov x9, d1
934 ; CHECK-GI-NEXT: and x8, x8, #0xffffffffffffff00
935 ; CHECK-GI-NEXT: and x9, x9, #0xff
936 ; CHECK-GI-NEXT: orr x8, x8, x9
937 ; CHECK-GI-NEXT: fmov d0, x8
938 ; CHECK-GI-NEXT: ret
939 %tmp1 = and <1 x i64> %a, < i64 -256 >
940 %tmp2 = and <1 x i64> %b, < i64 255 >
941 %tmp3 = or <1 x i64> %tmp1, %tmp2
942 ret <1 x i64> %tmp3
943 }
945 define <4 x i32> @bsl4xi32_const(<4 x i32> %a, <4 x i32> %b) {
946 ; CHECK-SD-LABEL: bsl4xi32_const:
947 ; CHECK-SD: // %bb.0:
948 ; CHECK-SD-NEXT: movi v2.2d, #0x000000ffffffff
949 ; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b
950 ; CHECK-SD-NEXT: ret
951 ;
952 ; CHECK-GI-LABEL: bsl4xi32_const:
953 ; CHECK-GI: // %bb.0:
954 ; CHECK-GI-NEXT: adrp x8, .LCPI73_0
955 ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI73_0]
956 ; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
957 ; CHECK-GI-NEXT: ret
958 %tmp1 = and <4 x i32> %a, < i32 -1, i32 0, i32 -1, i32 0 >
959 %tmp2 = and <4 x i32> %b, < i32 0, i32 -1, i32 0, i32 -1 >
960 %tmp3 = or <4 x i32> %tmp1, %tmp2
961 ret <4 x i32> %tmp3
962 }
964 define <8 x i16> @bsl8xi16_const(<8 x i16> %a, <8 x i16> %b) {
965 ; CHECK-SD-LABEL: bsl8xi16_const:
966 ; CHECK-SD: // %bb.0:
967 ; CHECK-SD-NEXT: movi v2.2d, #0x000000ffffffff
968 ; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b
969 ; CHECK-SD-NEXT: ret
970 ;
971 ; CHECK-GI-LABEL: bsl8xi16_const:
972 ; CHECK-GI: // %bb.0:
973 ; CHECK-GI-NEXT: adrp x8, .LCPI74_0
974 ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI74_0]
975 ; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
976 ; CHECK-GI-NEXT: ret
977 %tmp1 = and <8 x i16> %a, < i16 -1, i16 -1, i16 0,i16 0, i16 -1, i16 -1, i16 0,i16 0 >
978 %tmp2 = and <8 x i16> %b, < i16 0, i16 0, i16 -1, i16 -1, i16 0, i16 0, i16 -1, i16 -1 >
979 %tmp3 = or <8 x i16> %tmp1, %tmp2
980 ret <8 x i16> %tmp3
981 }
983 define <2 x i64> @bsl2xi64_const(<2 x i64> %a, <2 x i64> %b) {
984 ; CHECK-LABEL: bsl2xi64_const:
985 ; CHECK: // %bb.0:
986 ; CHECK-NEXT: adrp x8, .LCPI75_0
987 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI75_0]
988 ; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
989 ; CHECK-NEXT: ret
990 %tmp1 = and <2 x i64> %a, < i64 -1, i64 0 >
991 %tmp2 = and <2 x i64> %b, < i64 0, i64 -1 >
992 %tmp3 = or <2 x i64> %tmp1, %tmp2
993 ret <2 x i64> %tmp3
994 }
997 define <8 x i8> @bsl8xi8(<8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3) {
998 ; CHECK-LABEL: bsl8xi8:
999 ; CHECK: // %bb.0:
1000 ; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
1001 ; CHECK-NEXT: ret
1002 %1 = and <8 x i8> %v1, %v2
1003 %2 = xor <8 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
1004 %3 = and <8 x i8> %2, %v3
1005 %4 = or <8 x i8> %1, %3
1006 ret <8 x i8> %4
1007 }
1009 define <4 x i16> @bsl4xi16(<4 x i16> %v1, <4 x i16> %v2, <4 x i16> %v3) {
1010 ; CHECK-LABEL: bsl4xi16:
1011 ; CHECK: // %bb.0:
1012 ; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
1013 ; CHECK-NEXT: ret
1014 %1 = and <4 x i16> %v1, %v2
1015 %2 = xor <4 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1>
1016 %3 = and <4 x i16> %2, %v3
1017 %4 = or <4 x i16> %1, %3
1018 ret <4 x i16> %4
1019 }
1021 define <2 x i32> @bsl2xi32(<2 x i32> %v1, <2 x i32> %v2, <2 x i32> %v3) {
1022 ; CHECK-LABEL: bsl2xi32:
1023 ; CHECK: // %bb.0:
1024 ; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
1025 ; CHECK-NEXT: ret
1026 %1 = and <2 x i32> %v1, %v2
1027 %2 = xor <2 x i32> %v1, <i32 -1, i32 -1>
1028 %3 = and <2 x i32> %2, %v3
1029 %4 = or <2 x i32> %1, %3
1030 ret <2 x i32> %4
1031 }
1033 define <1 x i64> @bsl1xi64(<1 x i64> %v1, <1 x i64> %v2, <1 x i64> %v3) {
1034 ; CHECK-SD-LABEL: bsl1xi64:
1035 ; CHECK-SD: // %bb.0:
1036 ; CHECK-SD-NEXT: bsl v0.8b, v1.8b, v2.8b
1037 ; CHECK-SD-NEXT: ret
1038 ;
1039 ; CHECK-GI-LABEL: bsl1xi64:
1040 ; CHECK-GI: // %bb.0:
1041 ; CHECK-GI-NEXT: fmov x8, d0
1042 ; CHECK-GI-NEXT: fmov x9, d1
1043 ; CHECK-GI-NEXT: fmov x10, d2
1044 ; CHECK-GI-NEXT: and x9, x8, x9
1045 ; CHECK-GI-NEXT: bic x8, x10, x8
1046 ; CHECK-GI-NEXT: orr x8, x9, x8
1047 ; CHECK-GI-NEXT: fmov d0, x8
1048 ; CHECK-GI-NEXT: ret
1049 %1 = and <1 x i64> %v1, %v2
1050 %2 = xor <1 x i64> %v1, <i64 -1>
1051 %3 = and <1 x i64> %2, %v3
1052 %4 = or <1 x i64> %1, %3
1053 ret <1 x i64> %4
1054 }
1056 define <16 x i8> @bsl16xi8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3) {
1057 ; CHECK-LABEL: bsl16xi8:
1058 ; CHECK: // %bb.0:
1059 ; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
1060 ; CHECK-NEXT: ret
1061 %1 = and <16 x i8> %v1, %v2
1062 %2 = xor <16 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
1063 %3 = and <16 x i8> %2, %v3
1064 %4 = or <16 x i8> %1, %3
1065 ret <16 x i8> %4
1066 }
1068 define <8 x i16> @bsl8xi16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %v3) {
1069 ; CHECK-LABEL: bsl8xi16:
1070 ; CHECK: // %bb.0:
1071 ; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
1072 ; CHECK-NEXT: ret
1073 %1 = and <8 x i16> %v1, %v2
1074 %2 = xor <8 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
1075 %3 = and <8 x i16> %2, %v3
1076 %4 = or <8 x i16> %1, %3
1077 ret <8 x i16> %4
1078 }
1080 define <4 x i32> @bsl4xi32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
1081 ; CHECK-LABEL: bsl4xi32:
1082 ; CHECK: // %bb.0:
1083 ; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
1084 ; CHECK-NEXT: ret
1085 %1 = and <4 x i32> %v1, %v2
1086 %2 = xor <4 x i32> %v1, <i32 -1, i32 -1, i32 -1, i32 -1>
1087 %3 = and <4 x i32> %2, %v3
1088 %4 = or <4 x i32> %1, %3
1089 ret <4 x i32> %4
1090 }
1092 define <8 x i8> @vselect_constant_cond_zero_v8i8(<8 x i8> %a) {
1093 ; CHECK-SD-LABEL: vselect_constant_cond_zero_v8i8:
1094 ; CHECK-SD: // %bb.0:
1095 ; CHECK-SD-NEXT: movi d1, #0x00000000ff00ff
1096 ; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
1097 ; CHECK-SD-NEXT: ret
1098 ;
1099 ; CHECK-GI-LABEL: vselect_constant_cond_zero_v8i8:
1100 ; CHECK-GI: // %bb.0:
1101 ; CHECK-GI-NEXT: adrp x8, .LCPI83_0
1102 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI83_0]
1103 ; CHECK-GI-NEXT: shl v1.8b, v1.8b, #7
1104 ; CHECK-GI-NEXT: sshr v1.8b, v1.8b, #7
1105 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1106 ; CHECK-GI-NEXT: ret
1107 %b = select <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i8> %a, <8 x i8> zeroinitializer
1108 ret <8 x i8> %b
1109 }
1111 define <4 x i16> @vselect_constant_cond_zero_v4i16(<4 x i16> %a) {
1112 ; CHECK-SD-LABEL: vselect_constant_cond_zero_v4i16:
1113 ; CHECK-SD: // %bb.0:
1114 ; CHECK-SD-NEXT: movi d1, #0xffff00000000ffff
1115 ; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
1116 ; CHECK-SD-NEXT: ret
1117 ;
1118 ; CHECK-GI-LABEL: vselect_constant_cond_zero_v4i16:
1119 ; CHECK-GI: // %bb.0:
1120 ; CHECK-GI-NEXT: adrp x8, .LCPI84_0
1121 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI84_0]
1122 ; CHECK-GI-NEXT: shl v1.4h, v1.4h, #15
1123 ; CHECK-GI-NEXT: sshr v1.4h, v1.4h, #15
1124 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1125 ; CHECK-GI-NEXT: ret
1126 %b = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i16> %a, <4 x i16> zeroinitializer
1127 ret <4 x i16> %b
1128 }
1130 define <4 x i32> @vselect_constant_cond_zero_v4i32(<4 x i32> %a) {
1131 ; CHECK-SD-LABEL: vselect_constant_cond_zero_v4i32:
1132 ; CHECK-SD: // %bb.0:
1133 ; CHECK-SD-NEXT: adrp x8, .LCPI85_0
1134 ; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI85_0]
1135 ; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b
1136 ; CHECK-SD-NEXT: ret
1137 ;
1138 ; CHECK-GI-LABEL: vselect_constant_cond_zero_v4i32:
1139 ; CHECK-GI: // %bb.0:
1140 ; CHECK-GI-NEXT: adrp x8, .LCPI85_1
1141 ; CHECK-GI-NEXT: adrp x9, .LCPI85_0
1142 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI85_1]
1143 ; CHECK-GI-NEXT: ldr d2, [x9, :lo12:.LCPI85_0]
1144 ; CHECK-GI-NEXT: mov v1.d[1], v2.d[0]
1145 ; CHECK-GI-NEXT: shl v1.4s, v1.4s, #31
1146 ; CHECK-GI-NEXT: sshr v1.4s, v1.4s, #31
1147 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1148 ; CHECK-GI-NEXT: ret
1149 %b = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i32> %a, <4 x i32> zeroinitializer
1150 ret <4 x i32> %b
1151 }
1153 define <8 x i8> @vselect_constant_cond_v8i8(<8 x i8> %a, <8 x i8> %b) {
1154 ; CHECK-SD-LABEL: vselect_constant_cond_v8i8:
1155 ; CHECK-SD: // %bb.0:
1156 ; CHECK-SD-NEXT: movi d2, #0xffffffffff00ff00
1157 ; CHECK-SD-NEXT: movi d3, #0x00000000ff00ff
1158 ; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b
1159 ; CHECK-SD-NEXT: and v0.8b, v0.8b, v3.8b
1160 ; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
1161 ; CHECK-SD-NEXT: ret
1162 ;
1163 ; CHECK-GI-LABEL: vselect_constant_cond_v8i8:
1164 ; CHECK-GI: // %bb.0:
1165 ; CHECK-GI-NEXT: adrp x8, .LCPI86_0
1166 ; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI86_0]
1167 ; CHECK-GI-NEXT: shl v2.8b, v2.8b, #7
1168 ; CHECK-GI-NEXT: sshr v2.8b, v2.8b, #7
1169 ; CHECK-GI-NEXT: bif v0.8b, v1.8b, v2.8b
1170 ; CHECK-GI-NEXT: ret
1171 %c = select <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i8> %a, <8 x i8> %b
1172 ret <8 x i8> %c
1173 }
1175 define <4 x i16> @vselect_constant_cond_v4i16(<4 x i16> %a, <4 x i16> %b) {
1176 ; CHECK-SD-LABEL: vselect_constant_cond_v4i16:
1177 ; CHECK-SD: // %bb.0:
1178 ; CHECK-SD-NEXT: movi d2, #0x00ffffffff0000
1179 ; CHECK-SD-NEXT: movi d3, #0xffff00000000ffff
1180 ; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b
1181 ; CHECK-SD-NEXT: and v0.8b, v0.8b, v3.8b
1182 ; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
1183 ; CHECK-SD-NEXT: ret
1184 ;
1185 ; CHECK-GI-LABEL: vselect_constant_cond_v4i16:
1186 ; CHECK-GI: // %bb.0:
1187 ; CHECK-GI-NEXT: adrp x8, .LCPI87_0
1188 ; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI87_0]
1189 ; CHECK-GI-NEXT: shl v2.4h, v2.4h, #15
1190 ; CHECK-GI-NEXT: sshr v2.4h, v2.4h, #15
1191 ; CHECK-GI-NEXT: bif v0.8b, v1.8b, v2.8b
1192 ; CHECK-GI-NEXT: ret
1193 %c = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i16> %a, <4 x i16> %b
1194 ret <4 x i16> %c
1195 }
1197 define <4 x i32> @vselect_constant_cond_v4i32(<4 x i32> %a, <4 x i32> %b) {
1198 ; CHECK-SD-LABEL: vselect_constant_cond_v4i32:
1199 ; CHECK-SD: // %bb.0:
1200 ; CHECK-SD-NEXT: adrp x8, .LCPI88_0
1201 ; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI88_0]
1202 ; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b
1203 ; CHECK-SD-NEXT: ret
1204 ;
1205 ; CHECK-GI-LABEL: vselect_constant_cond_v4i32:
1206 ; CHECK-GI: // %bb.0:
1207 ; CHECK-GI-NEXT: adrp x8, .LCPI88_1
1208 ; CHECK-GI-NEXT: adrp x9, .LCPI88_0
1209 ; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI88_1]
1210 ; CHECK-GI-NEXT: ldr d3, [x9, :lo12:.LCPI88_0]
1211 ; CHECK-GI-NEXT: mov v2.d[1], v3.d[0]
1212 ; CHECK-GI-NEXT: shl v2.4s, v2.4s, #31
1213 ; CHECK-GI-NEXT: sshr v2.4s, v2.4s, #31
1214 ; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
1215 ; CHECK-GI-NEXT: ret
1216 %c = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i32> %a, <4 x i32> %b
1217 ret <4 x i32> %c
1218 }
1220 ; CHECK-SD: .byte 0
1221 ; CHECK-SD: .byte 8
1222 ; CHECK-SD: .byte 2
1223 ; CHECK-SD: .byte 9
1224 ; CHECK-SD: .byte 4
1225 ; CHECK-SD: .byte 5
1226 ; CHECK-SD: .byte 6
1227 ; CHECK-SD: .byte 7
1228 define <8 x i8> @vselect_equivalent_shuffle_v8i8(<8 x i8> %a, <8 x i8> %b) {
1229 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i8:
1230 ; CHECK-SD: // %bb.0:
1231 ; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
1232 ; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
1233 ; CHECK-SD-NEXT: adrp x8, .LCPI89_0
1234 ; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
1235 ; CHECK-SD-NEXT: ldr d1, [x8, :lo12:.LCPI89_0]
1236 ; CHECK-SD-NEXT: tbl v0.8b, { v0.16b }, v1.8b
1237 ; CHECK-SD-NEXT: ret
1238 ;
1239 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i8:
1240 ; CHECK-GI: // %bb.0:
1241 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
1242 ; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
1243 ; CHECK-GI-NEXT: adrp x8, .LCPI89_0
1244 ; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
1245 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI89_0]
1246 ; CHECK-GI-NEXT: tbl v0.16b, { v0.16b }, v1.16b
1247 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
1248 ; CHECK-GI-NEXT: ret
1249 %c = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 0, i32 8, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7>
1250 ret <8 x i8> %c
1251 }
1253 define <8 x i8> @vselect_equivalent_shuffle_v8i8_zero(<8 x i8> %a) {
1254 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i8_zero:
1255 ; CHECK-SD: // %bb.0:
1256 ; CHECK-SD-NEXT: movi d1, #0xffffffff00ff00ff
1257 ; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
1258 ; CHECK-SD-NEXT: ret
1259 ;
1260 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i8_zero:
1261 ; CHECK-GI: // %bb.0:
1262 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1263 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
1264 ; CHECK-GI-NEXT: adrp x8, .LCPI90_0
1265 ; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
1266 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI90_0]
1267 ; CHECK-GI-NEXT: tbl v0.16b, { v0.16b }, v1.16b
1268 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
1269 ; CHECK-GI-NEXT: ret
1270 %c = shufflevector <8 x i8> %a, <8 x i8> zeroinitializer, <8 x i32> <i32 0, i32 8, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7>
1271 ret <8 x i8> %c
1272 }
1274 ; CHECK-SD-LABEL: .LCPI91_0:
1275 ; CHECK-SD-NEXT: .byte 0
1276 ; CHECK-SD-NEXT: .byte 255
1277 ; CHECK-SD-NEXT: .byte 2
1278 ; CHECK-SD-NEXT: .byte 255
1279 ; CHECK-SD-NEXT: .byte 4
1280 ; CHECK-SD-NEXT: .byte 5
1281 ; CHECK-SD-NEXT: .byte 6
1282 ; CHECK-SD-NEXT: .byte 7
1283 define <8 x i8> @vselect_equivalent_shuffle_v8i8_zeroswap(<8 x i8> %a) {
1284 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i8_zeroswap:
1285 ; CHECK-SD: // %bb.0:
1286 ; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
1287 ; CHECK-SD-NEXT: adrp x8, .LCPI91_0
1288 ; CHECK-SD-NEXT: mov v0.d[1], v0.d[0]
1289 ; CHECK-SD-NEXT: ldr d1, [x8, :lo12:.LCPI91_0]
1290 ; CHECK-SD-NEXT: tbl v0.8b, { v0.16b }, v1.8b
1291 ; CHECK-SD-NEXT: ret
1292 ;
1293 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i8_zeroswap:
1294 ; CHECK-GI: // %bb.0:
1295 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1296 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
1297 ; CHECK-GI-NEXT: adrp x8, .LCPI91_0
1298 ; CHECK-GI-NEXT: mov v1.d[1], v0.d[0]
1299 ; CHECK-GI-NEXT: ldr d0, [x8, :lo12:.LCPI91_0]
1300 ; CHECK-GI-NEXT: tbl v0.16b, { v1.16b }, v0.16b
1301 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
1302 ; CHECK-GI-NEXT: ret
1303 %c = shufflevector <8 x i8> zeroinitializer, <8 x i8> %a, <8 x i32> <i32 8, i32 0, i32 10, i32 1, i32 12, i32 13, i32 14, i32 15>
1304 ret <8 x i8> %c
1305 }
1307 ; CHECK-SD-LABEL: .LCPI92_0:
1308 ; CHECK-SD-NEXT: .byte 0
1309 ; CHECK-SD-NEXT: .byte 1
1310 ; CHECK-SD-NEXT: .byte 16
1311 ; CHECK-SD-NEXT: .byte 17
1312 ; CHECK-SD-NEXT: .byte 4
1313 ; CHECK-SD-NEXT: .byte 5
1314 ; CHECK-SD-NEXT: .byte 18
1315 ; CHECK-SD-NEXT: .byte 19
1316 ; CHECK-SD-NEXT: .byte 8
1317 ; CHECK-SD-NEXT: .byte 9
1318 ; CHECK-SD-NEXT: .byte 10
1319 ; CHECK-SD-NEXT: .byte 11
1320 ; CHECK-SD-NEXT: .byte 12
1321 ; CHECK-SD-NEXT: .byte 13
1322 ; CHECK-SD-NEXT: .byte 14
1323 ; CHECK-SD-NEXT: .byte 15
1324 define <8 x i16> @vselect_equivalent_shuffle_v8i16(<8 x i16> %a, <8 x i16> %b) {
1325 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i16:
1326 ; CHECK-SD: // %bb.0:
1327 ; CHECK-SD-NEXT: adrp x8, .LCPI92_0
1328 ; CHECK-SD-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
1329 ; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI92_0]
1330 ; CHECK-SD-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
1331 ; CHECK-SD-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
1332 ; CHECK-SD-NEXT: ret
1333 ;
1334 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i16:
1335 ; CHECK-GI: // %bb.0:
1336 ; CHECK-GI-NEXT: adrp x8, .LCPI92_0
1337 ; CHECK-GI-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
1338 ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI92_0]
1339 ; CHECK-GI-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
1340 ; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
1341 ; CHECK-GI-NEXT: ret
1342 %c = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 8, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7>
1343 ret <8 x i16> %c
1344 }
1346 ; CHECK-SD-LABEL: .LCPI93_0:
1347 ; CHECK-SD-NEXT: .hword 65535 // 0xffff
1348 ; CHECK-SD-NEXT: .hword 0 // 0x0
1349 ; CHECK-SD-NEXT: .hword 65535 // 0xffff
1350 ; CHECK-SD-NEXT: .hword 0 // 0x0
1351 ; CHECK-SD-NEXT: .hword 65535 // 0xffff
1352 ; CHECK-SD-NEXT: .hword 65535 // 0xffff
1353 ; CHECK-SD-NEXT: .hword 65535 // 0xffff
1354 ; CHECK-SD-NEXT: .hword 65535 // 0xffff
1355 define <8 x i16> @vselect_equivalent_shuffle_v8i16_zero(<8 x i16> %a) {
1356 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i16_zero:
1357 ; CHECK-SD: // %bb.0:
1358 ; CHECK-SD-NEXT: adrp x8, .LCPI93_0
1359 ; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI93_0]
1360 ; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b
1361 ; CHECK-SD-NEXT: ret
1362 ;
1363 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i16_zero:
1364 ; CHECK-GI: // %bb.0:
1365 ; CHECK-GI-NEXT: // kill: def $q0 killed $q0 def $q0_q1
1366 ; CHECK-GI-NEXT: adrp x8, .LCPI93_0
1367 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1368 ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI93_0]
1369 ; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
1370 ; CHECK-GI-NEXT: ret
1371 %c = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 0, i32 8, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7>
1372 ret <8 x i16> %c
1373 }
1375 ; CHECK-SD: .byte 0
1376 ; CHECK-SD: .byte 1
1377 ; CHECK-SD: .byte 255
1378 ; CHECK-SD: .byte 255
1379 ; CHECK-SD: .byte 4
1380 ; CHECK-SD: .byte 5
1381 ; CHECK-SD: .byte 255
1382 ; CHECK-SD: .byte 255
1383 ; CHECK-SD: .byte 8
1384 ; CHECK-SD: .byte 9
1385 ; CHECK-SD: .byte 10
1386 ; CHECK-SD: .byte 11
1387 ; CHECK-SD: .byte 12
1388 ; CHECK-SD: .byte 13
1389 ; CHECK-SD: .byte 14
1390 ; CHECK-SD: .byte 15
1391 define <8 x i16> @vselect_equivalent_shuffle_v8i16_zeroswap(<8 x i16> %a) {
1392 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i16_zeroswap:
1393 ; CHECK-SD: // %bb.0:
1394 ; CHECK-SD-NEXT: adrp x8, .LCPI94_0
1395 ; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI94_0]
1396 ; CHECK-SD-NEXT: tbl v0.16b, { v0.16b }, v1.16b
1397 ; CHECK-SD-NEXT: ret
1398 ;
1399 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i16_zeroswap:
1400 ; CHECK-GI: // %bb.0:
1401 ; CHECK-GI-NEXT: // kill: def $q0 killed $q0 def $q31_q0
1402 ; CHECK-GI-NEXT: adrp x8, .LCPI94_0
1403 ; CHECK-GI-NEXT: movi v31.2d, #0000000000000000
1404 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI94_0]
1405 ; CHECK-GI-NEXT: tbl v0.16b, { v31.16b, v0.16b }, v1.16b
1406 ; CHECK-GI-NEXT: ret
1407 %c = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 8, i32 0, i32 10, i32 1, i32 12, i32 13, i32 14, i32 15>
1408 ret <8 x i16> %c
1409 }
1411 define <4 x i16> @vselect_equivalent_shuffle_v4i16(<4 x i16> %a, <4 x i16> %b) {
1412 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v4i16:
1413 ; CHECK-SD: // %bb.0:
1414 ; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
1415 ; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
1416 ; CHECK-SD-NEXT: mov v0.h[1], v1.h[0]
1417 ; CHECK-SD-NEXT: mov v0.h[2], v1.h[1]
1418 ; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
1419 ; CHECK-SD-NEXT: ret
1420 ;
1421 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v4i16:
1422 ; CHECK-GI: // %bb.0:
1423 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
1424 ; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
1425 ; CHECK-GI-NEXT: adrp x8, .LCPI95_0
1426 ; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
1427 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI95_0]
1428 ; CHECK-GI-NEXT: tbl v0.16b, { v0.16b }, v1.16b
1429 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
1430 ; CHECK-GI-NEXT: ret
1431 %c = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 0, i32 4, i32 5, i32 3>
1432 ret <4 x i16> %c
1433 }
1435 define <4 x i32> @vselect_equivalent_shuffle_v4i32(<4 x i32> %a, <4 x i32> %b) {
1436 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v4i32:
1437 ; CHECK-SD: // %bb.0:
1438 ; CHECK-SD-NEXT: mov v0.s[1], v1.s[0]
1439 ; CHECK-SD-NEXT: mov v0.s[2], v1.s[1]
1440 ; CHECK-SD-NEXT: ret
1441 ;
1442 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v4i32:
1443 ; CHECK-GI: // %bb.0:
1444 ; CHECK-GI-NEXT: adrp x8, .LCPI96_0
1445 ; CHECK-GI-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
1446 ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI96_0]
1447 ; CHECK-GI-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
1448 ; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
1449 ; CHECK-GI-NEXT: ret
1450 %c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 5, i32 3>
1451 ret <4 x i32> %c
1452 }
1454 define <8 x i8> @vselect_cmp_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
1455 ; CHECK-SD-LABEL: vselect_cmp_ne:
1456 ; CHECK-SD: // %bb.0:
1457 ; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, v1.8b
1458 ; CHECK-SD-NEXT: bsl v0.8b, v2.8b, v1.8b
1459 ; CHECK-SD-NEXT: ret
1460 ;
1461 ; CHECK-GI-LABEL: vselect_cmp_ne:
1462 ; CHECK-GI: // %bb.0:
1463 ; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v1.8b
1464 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
1465 ; CHECK-GI-NEXT: bsl v0.8b, v1.8b, v2.8b
1466 ; CHECK-GI-NEXT: ret
1467 %cmp = icmp ne <8 x i8> %a, %b
1468 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
1469 ret <8 x i8> %d
1470 }
1472 define <8 x i8> @vselect_cmp_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
1473 ; CHECK-LABEL: vselect_cmp_eq:
1474 ; CHECK: // %bb.0:
1475 ; CHECK-NEXT: cmeq v0.8b, v0.8b, v1.8b
1476 ; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
1477 ; CHECK-NEXT: ret
1478 %cmp = icmp eq <8 x i8> %a, %b
1479 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
1480 ret <8 x i8> %d
1481 }
1483 define <8 x i8> @vselect_cmpz_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
1484 ; CHECK-SD-LABEL: vselect_cmpz_ne:
1485 ; CHECK-SD: // %bb.0:
1486 ; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, #0
1487 ; CHECK-SD-NEXT: bsl v0.8b, v2.8b, v1.8b
1488 ; CHECK-SD-NEXT: ret
1489 ;
1490 ; CHECK-GI-LABEL: vselect_cmpz_ne:
1491 ; CHECK-GI: // %bb.0:
1492 ; CHECK-GI-NEXT: movi v3.2d, #0000000000000000
1493 ; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v3.8b
1494 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
1495 ; CHECK-GI-NEXT: bsl v0.8b, v1.8b, v2.8b
1496 ; CHECK-GI-NEXT: ret
1497 %cmp = icmp ne <8 x i8> %a, zeroinitializer
1498 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
1499 ret <8 x i8> %d
1500 }
1502 define <8 x i8> @vselect_cmpz_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
1503 ; CHECK-SD-LABEL: vselect_cmpz_eq:
1504 ; CHECK-SD: // %bb.0:
1505 ; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, #0
1506 ; CHECK-SD-NEXT: bsl v0.8b, v1.8b, v2.8b
1507 ; CHECK-SD-NEXT: ret
1508 ;
1509 ; CHECK-GI-LABEL: vselect_cmpz_eq:
1510 ; CHECK-GI: // %bb.0:
1511 ; CHECK-GI-NEXT: movi v3.2d, #0000000000000000
1512 ; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v3.8b
1513 ; CHECK-GI-NEXT: bsl v0.8b, v1.8b, v2.8b
1514 ; CHECK-GI-NEXT: ret
1515 %cmp = icmp eq <8 x i8> %a, zeroinitializer
1516 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
1517 ret <8 x i8> %d
1518 }
1520 define <8 x i8> @vselect_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
1521 ; CHECK-SD-LABEL: vselect_tst:
1522 ; CHECK-SD: // %bb.0:
1523 ; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
1524 ; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, #0
1525 ; CHECK-SD-NEXT: bsl v0.8b, v2.8b, v1.8b
1526 ; CHECK-SD-NEXT: ret
1527 ;
1528 ; CHECK-GI-LABEL: vselect_tst:
1529 ; CHECK-GI: // %bb.0:
1530 ; CHECK-GI-NEXT: movi v3.2d, #0000000000000000
1531 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1532 ; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v3.8b
1533 ; CHECK-GI-NEXT: bsl v0.8b, v2.8b, v1.8b
1534 ; CHECK-GI-NEXT: ret
1535 %tmp3 = and <8 x i8> %a, %b
1536 %tmp4 = icmp eq <8 x i8> %tmp3, zeroinitializer
1537 %d = select <8 x i1> %tmp4, <8 x i8> %c, <8 x i8> %b
1538 ret <8 x i8> %d
1539 }
1541 define <8 x i8> @sext_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
1542 ; CHECK-SD-LABEL: sext_tst:
1543 ; CHECK-SD: // %bb.0:
1544 ; CHECK-SD-NEXT: cmtst v0.8b, v0.8b, v1.8b
1545 ; CHECK-SD-NEXT: ret
1546 ;
1547 ; CHECK-GI-LABEL: sext_tst:
1548 ; CHECK-GI: // %bb.0:
1549 ; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
1550 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1551 ; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v2.8b
1552 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
1553 ; CHECK-GI-NEXT: ret
1554 %tmp3 = and <8 x i8> %a, %b
1555 %tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer
1556 %d = sext <8 x i1> %tmp4 to <8 x i8>
1557 ret <8 x i8> %d
1558 }
1560 define <2 x i64> @bsl2xi64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %v3) {
1561 ; CHECK-LABEL: bsl2xi64:
1562 ; CHECK: // %bb.0:
1563 ; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
1564 ; CHECK-NEXT: ret
1565 %1 = and <2 x i64> %v1, %v2
1566 %2 = xor <2 x i64> %v1, <i64 -1, i64 -1>
1567 %3 = and <2 x i64> %2, %v3
1568 %4 = or <2 x i64> %1, %3
1569 ret <2 x i64> %4
1570 }
1572 define <8 x i8> @orrimm8b_as_orrimm4h_lsl0(<8 x i8> %a) {
1573 ; CHECK-SD-LABEL: orrimm8b_as_orrimm4h_lsl0:
1574 ; CHECK-SD: // %bb.0:
1575 ; CHECK-SD-NEXT: orr v0.4h, #255
1576 ; CHECK-SD-NEXT: ret
1577 ;
1578 ; CHECK-GI-LABEL: orrimm8b_as_orrimm4h_lsl0:
1579 ; CHECK-GI: // %bb.0:
1580 ; CHECK-GI-NEXT: adrp x8, .LCPI104_0
1581 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI104_0]
1582 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
1583 ; CHECK-GI-NEXT: ret
1584 %val = or <8 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
1585 ret <8 x i8> %val
1586 }
1588 define <8 x i8> @orrimm8b_as_orimm4h_lsl8(<8 x i8> %a) {
1589 ; CHECK-SD-LABEL: orrimm8b_as_orimm4h_lsl8:
1590 ; CHECK-SD: // %bb.0:
1591 ; CHECK-SD-NEXT: orr v0.4h, #255, lsl #8
1592 ; CHECK-SD-NEXT: ret
1593 ;
1594 ; CHECK-GI-LABEL: orrimm8b_as_orimm4h_lsl8:
1595 ; CHECK-GI: // %bb.0:
1596 ; CHECK-GI-NEXT: adrp x8, .LCPI105_0
1597 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI105_0]
1598 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
1599 ; CHECK-GI-NEXT: ret
1600 %val = or <8 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
1601 ret <8 x i8> %val
1602 }
1604 define <16 x i8> @orimm16b_as_orrimm8h_lsl0(<16 x i8> %a) {
1605 ; CHECK-SD-LABEL: orimm16b_as_orrimm8h_lsl0:
1606 ; CHECK-SD: // %bb.0:
1607 ; CHECK-SD-NEXT: orr v0.8h, #255
1608 ; CHECK-SD-NEXT: ret
1609 ;
1610 ; CHECK-GI-LABEL: orimm16b_as_orrimm8h_lsl0:
1611 ; CHECK-GI: // %bb.0:
1612 ; CHECK-GI-NEXT: adrp x8, .LCPI106_0
1613 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI106_0]
1614 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
1615 ; CHECK-GI-NEXT: ret
1616 %val = or <16 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
1617 ret <16 x i8> %val
1618 }
1620 define <16 x i8> @orimm16b_as_orrimm8h_lsl8(<16 x i8> %a) {
1621 ; CHECK-SD-LABEL: orimm16b_as_orrimm8h_lsl8:
1622 ; CHECK-SD: // %bb.0:
1623 ; CHECK-SD-NEXT: orr v0.8h, #255, lsl #8
1624 ; CHECK-SD-NEXT: ret
1625 ;
1626 ; CHECK-GI-LABEL: orimm16b_as_orrimm8h_lsl8:
1627 ; CHECK-GI: // %bb.0:
1628 ; CHECK-GI-NEXT: adrp x8, .LCPI107_0
1629 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI107_0]
1630 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
1631 ; CHECK-GI-NEXT: ret
1632 %val = or <16 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
1633 ret <16 x i8> %val
1634 }
1636 define <8 x i8> @and8imm2s_lsl0(<8 x i8> %a) {
1637 ; CHECK-SD-LABEL: and8imm2s_lsl0:
1638 ; CHECK-SD: // %bb.0:
1639 ; CHECK-SD-NEXT: bic v0.2s, #255
1640 ; CHECK-SD-NEXT: ret
1641 ;
1642 ; CHECK-GI-LABEL: and8imm2s_lsl0:
1643 ; CHECK-GI: // %bb.0:
1644 ; CHECK-GI-NEXT: adrp x8, .LCPI108_0
1645 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI108_0]
1646 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1647 ; CHECK-GI-NEXT: ret
1648 %tmp1 = and <8 x i8> %a, < i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255>
1649 ret <8 x i8> %tmp1
1650 }
1652 define <8 x i8> @and8imm2s_lsl8(<8 x i8> %a) {
1653 ; CHECK-SD-LABEL: and8imm2s_lsl8:
1654 ; CHECK-SD: // %bb.0:
1655 ; CHECK-SD-NEXT: bic v0.2s, #255, lsl #8
1656 ; CHECK-SD-NEXT: ret
1657 ;
1658 ; CHECK-GI-LABEL: and8imm2s_lsl8:
1659 ; CHECK-GI: // %bb.0:
1660 ; CHECK-GI-NEXT: adrp x8, .LCPI109_0
1661 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI109_0]
1662 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1663 ; CHECK-GI-NEXT: ret
1664 %tmp1 = and <8 x i8> %a, < i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255>
1665 ret <8 x i8> %tmp1
1666 }
1668 define <8 x i8> @and8imm2s_lsl16(<8 x i8> %a) {
1669 ; CHECK-SD-LABEL: and8imm2s_lsl16:
1670 ; CHECK-SD: // %bb.0:
1671 ; CHECK-SD-NEXT: bic v0.2s, #255, lsl #16
1672 ; CHECK-SD-NEXT: ret
1673 ;
1674 ; CHECK-GI-LABEL: and8imm2s_lsl16:
1675 ; CHECK-GI: // %bb.0:
1676 ; CHECK-GI-NEXT: adrp x8, .LCPI110_0
1677 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI110_0]
1678 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1679 ; CHECK-GI-NEXT: ret
1680 %tmp1 = and <8 x i8> %a, < i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255>
1681 ret <8 x i8> %tmp1
1682 }
1684 define <8 x i8> @and8imm2s_lsl24(<8 x i8> %a) {
1685 ; CHECK-SD-LABEL: and8imm2s_lsl24:
1686 ; CHECK-SD: // %bb.0:
1687 ; CHECK-SD-NEXT: bic v0.2s, #254, lsl #24
1688 ; CHECK-SD-NEXT: ret
1689 ;
1690 ; CHECK-GI-LABEL: and8imm2s_lsl24:
1691 ; CHECK-GI: // %bb.0:
1692 ; CHECK-GI-NEXT: adrp x8, .LCPI111_0
1693 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI111_0]
1694 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1695 ; CHECK-GI-NEXT: ret
1696 %tmp1 = and <8 x i8> %a, < i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1>
1697 ret <8 x i8> %tmp1
1698 }
1700 define <4 x i16> @and16imm2s_lsl0(<4 x i16> %a) {
1701 ; CHECK-SD-LABEL: and16imm2s_lsl0:
1702 ; CHECK-SD: // %bb.0:
1703 ; CHECK-SD-NEXT: bic v0.2s, #255
1704 ; CHECK-SD-NEXT: ret
1705 ;
1706 ; CHECK-GI-LABEL: and16imm2s_lsl0:
1707 ; CHECK-GI: // %bb.0:
1708 ; CHECK-GI-NEXT: adrp x8, .LCPI112_0
1709 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI112_0]
1710 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1711 ; CHECK-GI-NEXT: ret
1712 %tmp1 = and <4 x i16> %a, < i16 65280, i16 65535, i16 65280, i16 65535>
1713 ret <4 x i16> %tmp1
1714 }
1716 define <4 x i16> @and16imm2s_lsl8(<4 x i16> %a) {
1717 ; CHECK-SD-LABEL: and16imm2s_lsl8:
1718 ; CHECK-SD: // %bb.0:
1719 ; CHECK-SD-NEXT: bic v0.2s, #255, lsl #8
1720 ; CHECK-SD-NEXT: ret
1721 ;
1722 ; CHECK-GI-LABEL: and16imm2s_lsl8:
1723 ; CHECK-GI: // %bb.0:
1724 ; CHECK-GI-NEXT: adrp x8, .LCPI113_0
1725 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI113_0]
1726 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1727 ; CHECK-GI-NEXT: ret
1728 %tmp1 = and <4 x i16> %a, < i16 255, i16 65535, i16 255, i16 65535>
1729 ret <4 x i16> %tmp1
1730 }
1732 define <4 x i16> @and16imm2s_lsl16(<4 x i16> %a) {
1733 ; CHECK-SD-LABEL: and16imm2s_lsl16:
1734 ; CHECK-SD: // %bb.0:
1735 ; CHECK-SD-NEXT: bic v0.2s, #255, lsl #16
1736 ; CHECK-SD-NEXT: ret
1737 ;
1738 ; CHECK-GI-LABEL: and16imm2s_lsl16:
1739 ; CHECK-GI: // %bb.0:
1740 ; CHECK-GI-NEXT: adrp x8, .LCPI114_0
1741 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI114_0]
1742 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1743 ; CHECK-GI-NEXT: ret
1744 %tmp1 = and <4 x i16> %a, < i16 65535, i16 65280, i16 65535, i16 65280>
1745 ret <4 x i16> %tmp1
1746 }
1748 define <4 x i16> @and16imm2s_lsl24(<4 x i16> %a) {
1749 ; CHECK-SD-LABEL: and16imm2s_lsl24:
1750 ; CHECK-SD: // %bb.0:
1751 ; CHECK-SD-NEXT: bic v0.2s, #254, lsl #24
1752 ; CHECK-SD-NEXT: ret
1753 ;
1754 ; CHECK-GI-LABEL: and16imm2s_lsl24:
1755 ; CHECK-GI: // %bb.0:
1756 ; CHECK-GI-NEXT: adrp x8, .LCPI115_0
1757 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI115_0]
1758 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1759 ; CHECK-GI-NEXT: ret
1760 %tmp1 = and <4 x i16> %a, < i16 65535, i16 511, i16 65535, i16 511>
1761 ret <4 x i16> %tmp1
1762 }
1765 define <1 x i64> @and64imm2s_lsl0(<1 x i64> %a) {
1766 ; CHECK-SD-LABEL: and64imm2s_lsl0:
1767 ; CHECK-SD: // %bb.0:
1768 ; CHECK-SD-NEXT: bic v0.2s, #255
1769 ; CHECK-SD-NEXT: ret
1770 ;
1771 ; CHECK-GI-LABEL: and64imm2s_lsl0:
1772 ; CHECK-GI: // %bb.0:
1773 ; CHECK-GI-NEXT: fmov x8, d0
1774 ; CHECK-GI-NEXT: and x8, x8, #0xffffff00ffffff00
1775 ; CHECK-GI-NEXT: fmov d0, x8
1776 ; CHECK-GI-NEXT: ret
1777 %tmp1 = and <1 x i64> %a, < i64 -1095216660736>
1778 ret <1 x i64> %tmp1
1779 }
1781 define <1 x i64> @and64imm2s_lsl8(<1 x i64> %a) {
1782 ; CHECK-SD-LABEL: and64imm2s_lsl8:
1783 ; CHECK-SD: // %bb.0:
1784 ; CHECK-SD-NEXT: bic v0.2s, #255, lsl #8
1785 ; CHECK-SD-NEXT: ret
1786 ;
1787 ; CHECK-GI-LABEL: and64imm2s_lsl8:
1788 ; CHECK-GI: // %bb.0:
1789 ; CHECK-GI-NEXT: fmov x8, d0
1790 ; CHECK-GI-NEXT: and x8, x8, #0xffff00ffffff00ff
1791 ; CHECK-GI-NEXT: fmov d0, x8
1792 ; CHECK-GI-NEXT: ret
1793 %tmp1 = and <1 x i64> %a, < i64 -280375465148161>
1794 ret <1 x i64> %tmp1
1795 }
1797 define <1 x i64> @and64imm2s_lsl16(<1 x i64> %a) {
1798 ; CHECK-SD-LABEL: and64imm2s_lsl16:
1799 ; CHECK-SD: // %bb.0:
1800 ; CHECK-SD-NEXT: bic v0.2s, #255, lsl #16
1801 ; CHECK-SD-NEXT: ret
1802 ;
1803 ; CHECK-GI-LABEL: and64imm2s_lsl16:
1804 ; CHECK-GI: // %bb.0:
1805 ; CHECK-GI-NEXT: fmov x8, d0
1806 ; CHECK-GI-NEXT: and x8, x8, #0xff00ffffff00ffff
1807 ; CHECK-GI-NEXT: fmov d0, x8
1808 ; CHECK-GI-NEXT: ret
1809 %tmp1 = and <1 x i64> %a, < i64 -71776119077928961>
1810 ret <1 x i64> %tmp1
1811 }
1813 define <1 x i64> @and64imm2s_lsl24(<1 x i64> %a) {
1814 ; CHECK-SD-LABEL: and64imm2s_lsl24:
1815 ; CHECK-SD: // %bb.0:
1816 ; CHECK-SD-NEXT: bic v0.2s, #254, lsl #24
1817 ; CHECK-SD-NEXT: ret
1818 ;
1819 ; CHECK-GI-LABEL: and64imm2s_lsl24:
1820 ; CHECK-GI: // %bb.0:
1821 ; CHECK-GI-NEXT: fmov x8, d0
1822 ; CHECK-GI-NEXT: and x8, x8, #0x1ffffff01ffffff
1823 ; CHECK-GI-NEXT: fmov d0, x8
1824 ; CHECK-GI-NEXT: ret
1825 %tmp1 = and <1 x i64> %a, < i64 144115183814443007>
1826 ret <1 x i64> %tmp1
1827 }
1829 define <16 x i8> @and8imm4s_lsl0(<16 x i8> %a) {
1830 ; CHECK-SD-LABEL: and8imm4s_lsl0:
1831 ; CHECK-SD: // %bb.0:
1832 ; CHECK-SD-NEXT: bic v0.4s, #255
1833 ; CHECK-SD-NEXT: ret
1834 ;
1835 ; CHECK-GI-LABEL: and8imm4s_lsl0:
1836 ; CHECK-GI: // %bb.0:
1837 ; CHECK-GI-NEXT: adrp x8, .LCPI120_0
1838 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI120_0]
1839 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1840 ; CHECK-GI-NEXT: ret
1841 %tmp1 = and <16 x i8> %a, < i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255>
1842 ret <16 x i8> %tmp1
1843 }
1845 define <16 x i8> @and8imm4s_lsl8(<16 x i8> %a) {
1846 ; CHECK-SD-LABEL: and8imm4s_lsl8:
1847 ; CHECK-SD: // %bb.0:
1848 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #8
1849 ; CHECK-SD-NEXT: ret
1850 ;
1851 ; CHECK-GI-LABEL: and8imm4s_lsl8:
1852 ; CHECK-GI: // %bb.0:
1853 ; CHECK-GI-NEXT: adrp x8, .LCPI121_0
1854 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI121_0]
1855 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1856 ; CHECK-GI-NEXT: ret
1857 %tmp1 = and <16 x i8> %a, < i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255>
1858 ret <16 x i8> %tmp1
1859 }
1861 define <16 x i8> @and8imm4s_lsl16(<16 x i8> %a) {
1862 ; CHECK-SD-LABEL: and8imm4s_lsl16:
1863 ; CHECK-SD: // %bb.0:
1864 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #16
1865 ; CHECK-SD-NEXT: ret
1866 ;
1867 ; CHECK-GI-LABEL: and8imm4s_lsl16:
1868 ; CHECK-GI: // %bb.0:
1869 ; CHECK-GI-NEXT: adrp x8, .LCPI122_0
1870 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI122_0]
1871 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1872 ; CHECK-GI-NEXT: ret
1873 %tmp1 = and <16 x i8> %a, < i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255>
1874 ret <16 x i8> %tmp1
1875 }
1877 define <16 x i8> @and8imm4s_lsl24(<16 x i8> %a) {
1878 ; CHECK-SD-LABEL: and8imm4s_lsl24:
1879 ; CHECK-SD: // %bb.0:
1880 ; CHECK-SD-NEXT: bic v0.4s, #254, lsl #24
1881 ; CHECK-SD-NEXT: ret
1882 ;
1883 ; CHECK-GI-LABEL: and8imm4s_lsl24:
1884 ; CHECK-GI: // %bb.0:
1885 ; CHECK-GI-NEXT: adrp x8, .LCPI123_0
1886 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI123_0]
1887 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1888 ; CHECK-GI-NEXT: ret
1889 %tmp1 = and <16 x i8> %a, < i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1>
1890 ret <16 x i8> %tmp1
1891 }
1893 define <8 x i16> @and16imm4s_lsl0(<8 x i16> %a) {
1894 ; CHECK-SD-LABEL: and16imm4s_lsl0:
1895 ; CHECK-SD: // %bb.0:
1896 ; CHECK-SD-NEXT: bic v0.4s, #255
1897 ; CHECK-SD-NEXT: ret
1898 ;
1899 ; CHECK-GI-LABEL: and16imm4s_lsl0:
1900 ; CHECK-GI: // %bb.0:
1901 ; CHECK-GI-NEXT: adrp x8, .LCPI124_0
1902 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI124_0]
1903 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1904 ; CHECK-GI-NEXT: ret
1905 %tmp1 = and <8 x i16> %a, < i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535>
1906 ret <8 x i16> %tmp1
1907 }
1909 define <8 x i16> @and16imm4s_lsl8(<8 x i16> %a) {
1910 ; CHECK-SD-LABEL: and16imm4s_lsl8:
1911 ; CHECK-SD: // %bb.0:
1912 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #8
1913 ; CHECK-SD-NEXT: ret
1914 ;
1915 ; CHECK-GI-LABEL: and16imm4s_lsl8:
1916 ; CHECK-GI: // %bb.0:
1917 ; CHECK-GI-NEXT: adrp x8, .LCPI125_0
1918 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI125_0]
1919 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1920 ; CHECK-GI-NEXT: ret
1921 %tmp1 = and <8 x i16> %a, < i16 255, i16 65535, i16 255, i16 65535, i16 255, i16 65535, i16 255, i16 65535>
1922 ret <8 x i16> %tmp1
1923 }
1925 define <8 x i16> @and16imm4s_lsl16(<8 x i16> %a) {
1926 ; CHECK-SD-LABEL: and16imm4s_lsl16:
1927 ; CHECK-SD: // %bb.0:
1928 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #16
1929 ; CHECK-SD-NEXT: ret
1930 ;
1931 ; CHECK-GI-LABEL: and16imm4s_lsl16:
1932 ; CHECK-GI: // %bb.0:
1933 ; CHECK-GI-NEXT: adrp x8, .LCPI126_0
1934 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI126_0]
1935 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1936 ; CHECK-GI-NEXT: ret
1937 %tmp1 = and <8 x i16> %a, < i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280>
1938 ret <8 x i16> %tmp1
1939 }
1941 define <8 x i16> @and16imm4s_lsl24(<8 x i16> %a) {
1942 ; CHECK-SD-LABEL: and16imm4s_lsl24:
1943 ; CHECK-SD: // %bb.0:
1944 ; CHECK-SD-NEXT: bic v0.4s, #254, lsl #24
1945 ; CHECK-SD-NEXT: ret
1946 ;
1947 ; CHECK-GI-LABEL: and16imm4s_lsl24:
1948 ; CHECK-GI: // %bb.0:
1949 ; CHECK-GI-NEXT: adrp x8, .LCPI127_0
1950 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI127_0]
1951 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1952 ; CHECK-GI-NEXT: ret
1953 %tmp1 = and <8 x i16> %a, < i16 65535, i16 511, i16 65535, i16 511, i16 65535, i16 511, i16 65535, i16 511>
1954 ret <8 x i16> %tmp1
1955 }
1957 define <2 x i64> @and64imm4s_lsl0(<2 x i64> %a) {
1958 ; CHECK-SD-LABEL: and64imm4s_lsl0:
1959 ; CHECK-SD: // %bb.0:
1960 ; CHECK-SD-NEXT: bic v0.4s, #255
1961 ; CHECK-SD-NEXT: ret
1962 ;
1963 ; CHECK-GI-LABEL: and64imm4s_lsl0:
1964 ; CHECK-GI: // %bb.0:
1965 ; CHECK-GI-NEXT: movi v1.2d, #0xffffff00ffffff00
1966 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1967 ; CHECK-GI-NEXT: ret
1968 %tmp1 = and <2 x i64> %a, < i64 -1095216660736, i64 -1095216660736>
1969 ret <2 x i64> %tmp1
1970 }
1972 define <2 x i64> @and64imm4s_lsl8(<2 x i64> %a) {
1973 ; CHECK-SD-LABEL: and64imm4s_lsl8:
1974 ; CHECK-SD: // %bb.0:
1975 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #8
1976 ; CHECK-SD-NEXT: ret
1977 ;
1978 ; CHECK-GI-LABEL: and64imm4s_lsl8:
1979 ; CHECK-GI: // %bb.0:
1980 ; CHECK-GI-NEXT: movi v1.2d, #0xffff00ffffff00ff
1981 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1982 ; CHECK-GI-NEXT: ret
1983 %tmp1 = and <2 x i64> %a, < i64 -280375465148161, i64 -280375465148161>
1984 ret <2 x i64> %tmp1
1985 }
1987 define <2 x i64> @and64imm4s_lsl16(<2 x i64> %a) {
1988 ; CHECK-SD-LABEL: and64imm4s_lsl16:
1989 ; CHECK-SD: // %bb.0:
1990 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #16
1991 ; CHECK-SD-NEXT: ret
1992 ;
1993 ; CHECK-GI-LABEL: and64imm4s_lsl16:
1994 ; CHECK-GI: // %bb.0:
1995 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ffffff00ffff
1996 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1997 ; CHECK-GI-NEXT: ret
1998 %tmp1 = and <2 x i64> %a, < i64 -71776119077928961, i64 -71776119077928961>
1999 ret <2 x i64> %tmp1
2000 }
2002 define <2 x i64> @and64imm4s_lsl24(<2 x i64> %a) {
2003 ; CHECK-SD-LABEL: and64imm4s_lsl24:
2004 ; CHECK-SD: // %bb.0:
2005 ; CHECK-SD-NEXT: bic v0.4s, #254, lsl #24
2006 ; CHECK-SD-NEXT: ret
2007 ;
2008 ; CHECK-GI-LABEL: and64imm4s_lsl24:
2009 ; CHECK-GI: // %bb.0:
2010 ; CHECK-GI-NEXT: mvni v1.4s, #254, lsl #24
2011 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2012 ; CHECK-GI-NEXT: ret
2013 %tmp1 = and <2 x i64> %a, < i64 144115183814443007, i64 144115183814443007>
2014 ret <2 x i64> %tmp1
2015 }
2017 define <8 x i8> @and8imm4h_lsl0(<8 x i8> %a) {
2018 ; CHECK-SD-LABEL: and8imm4h_lsl0:
2019 ; CHECK-SD: // %bb.0:
2020 ; CHECK-SD-NEXT: bic v0.4h, #255
2021 ; CHECK-SD-NEXT: ret
2022 ;
2023 ; CHECK-GI-LABEL: and8imm4h_lsl0:
2024 ; CHECK-GI: // %bb.0:
2025 ; CHECK-GI-NEXT: adrp x8, .LCPI132_0
2026 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI132_0]
2027 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
2028 ; CHECK-GI-NEXT: ret
2029 %tmp1 = and <8 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
2030 ret <8 x i8> %tmp1
2031 }
2033 define <8 x i8> @and8imm4h_lsl8(<8 x i8> %a) {
2034 ; CHECK-SD-LABEL: and8imm4h_lsl8:
2035 ; CHECK-SD: // %bb.0:
2036 ; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
2037 ; CHECK-SD-NEXT: ret
2038 ;
2039 ; CHECK-GI-LABEL: and8imm4h_lsl8:
2040 ; CHECK-GI: // %bb.0:
2041 ; CHECK-GI-NEXT: adrp x8, .LCPI133_0
2042 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI133_0]
2043 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
2044 ; CHECK-GI-NEXT: ret
2045 %tmp1 = and <8 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
2046 ret <8 x i8> %tmp1
2047 }
2049 define <2 x i32> @and16imm4h_lsl0(<2 x i32> %a) {
2050 ; CHECK-SD-LABEL: and16imm4h_lsl0:
2051 ; CHECK-SD: // %bb.0:
2052 ; CHECK-SD-NEXT: bic v0.4h, #255
2053 ; CHECK-SD-NEXT: ret
2054 ;
2055 ; CHECK-GI-LABEL: and16imm4h_lsl0:
2056 ; CHECK-GI: // %bb.0:
2057 ; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff00
2058 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
2059 ; CHECK-GI-NEXT: ret
2060 %tmp1 = and <2 x i32> %a, < i32 4278255360, i32 4278255360>
2061 ret <2 x i32> %tmp1
2062 }
2064 define <2 x i32> @and16imm4h_lsl8(<2 x i32> %a) {
2065 ; CHECK-SD-LABEL: and16imm4h_lsl8:
2066 ; CHECK-SD: // %bb.0:
2067 ; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
2068 ; CHECK-SD-NEXT: ret
2069 ;
2070 ; CHECK-GI-LABEL: and16imm4h_lsl8:
2071 ; CHECK-GI: // %bb.0:
2072 ; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff
2073 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
2074 ; CHECK-GI-NEXT: ret
2075 %tmp1 = and <2 x i32> %a, < i32 16711935, i32 16711935>
2076 ret <2 x i32> %tmp1
2077 }
2079 define <1 x i64> @and64imm4h_lsl0(<1 x i64> %a) {
2080 ; CHECK-SD-LABEL: and64imm4h_lsl0:
2081 ; CHECK-SD: // %bb.0:
2082 ; CHECK-SD-NEXT: bic v0.4h, #255
2083 ; CHECK-SD-NEXT: ret
2084 ;
2085 ; CHECK-GI-LABEL: and64imm4h_lsl0:
2086 ; CHECK-GI: // %bb.0:
2087 ; CHECK-GI-NEXT: fmov x8, d0
2088 ; CHECK-GI-NEXT: and x8, x8, #0xff00ff00ff00ff00
2089 ; CHECK-GI-NEXT: fmov d0, x8
2090 ; CHECK-GI-NEXT: ret
2091 %tmp1 = and <1 x i64> %a, < i64 -71777214294589696>
2092 ret <1 x i64> %tmp1
2093 }
2095 define <1 x i64> @and64imm4h_lsl8(<1 x i64> %a) {
2096 ; CHECK-SD-LABEL: and64imm4h_lsl8:
2097 ; CHECK-SD: // %bb.0:
2098 ; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
2099 ; CHECK-SD-NEXT: ret
2100 ;
2101 ; CHECK-GI-LABEL: and64imm4h_lsl8:
2102 ; CHECK-GI: // %bb.0:
2103 ; CHECK-GI-NEXT: fmov x8, d0
2104 ; CHECK-GI-NEXT: and x8, x8, #0xff00ff00ff00ff
2105 ; CHECK-GI-NEXT: fmov d0, x8
2106 ; CHECK-GI-NEXT: ret
2107 %tmp1 = and <1 x i64> %a, < i64 71777214294589695>
2108 ret <1 x i64> %tmp1
2109 }
2111 define <16 x i8> @and8imm8h_lsl0(<16 x i8> %a) {
2112 ; CHECK-SD-LABEL: and8imm8h_lsl0:
2113 ; CHECK-SD: // %bb.0:
2114 ; CHECK-SD-NEXT: bic v0.8h, #255
2115 ; CHECK-SD-NEXT: ret
2116 ;
2117 ; CHECK-GI-LABEL: and8imm8h_lsl0:
2118 ; CHECK-GI: // %bb.0:
2119 ; CHECK-GI-NEXT: adrp x8, .LCPI138_0
2120 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI138_0]
2121 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2122 ; CHECK-GI-NEXT: ret
2123 %tmp1 = and <16 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255 >
2124 ret <16 x i8> %tmp1
2125 }
2127 define <16 x i8> @and8imm8h_lsl8(<16 x i8> %a) {
2128 ; CHECK-SD-LABEL: and8imm8h_lsl8:
2129 ; CHECK-SD: // %bb.0:
2130 ; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8
2131 ; CHECK-SD-NEXT: ret
2132 ;
2133 ; CHECK-GI-LABEL: and8imm8h_lsl8:
2134 ; CHECK-GI: // %bb.0:
2135 ; CHECK-GI-NEXT: adrp x8, .LCPI139_0
2136 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI139_0]
2137 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2138 ; CHECK-GI-NEXT: ret
2139 %tmp1 = and <16 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0 >
2140 ret <16 x i8> %tmp1
2141 }
2143 define <4 x i32> @and16imm8h_lsl0(<4 x i32> %a) {
2144 ; CHECK-SD-LABEL: and16imm8h_lsl0:
2145 ; CHECK-SD: // %bb.0:
2146 ; CHECK-SD-NEXT: bic v0.8h, #255
2147 ; CHECK-SD-NEXT: ret
2148 ;
2149 ; CHECK-GI-LABEL: and16imm8h_lsl0:
2150 ; CHECK-GI: // %bb.0:
2151 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff00
2152 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2153 ; CHECK-GI-NEXT: ret
2154 %tmp1 = and <4 x i32> %a, < i32 4278255360, i32 4278255360, i32 4278255360, i32 4278255360>
2155 ret <4 x i32> %tmp1
2156 }
2158 define <4 x i32> @and16imm8h_lsl8(<4 x i32> %a) {
2159 ; CHECK-SD-LABEL: and16imm8h_lsl8:
2160 ; CHECK-SD: // %bb.0:
2161 ; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8
2162 ; CHECK-SD-NEXT: ret
2163 ;
2164 ; CHECK-GI-LABEL: and16imm8h_lsl8:
2165 ; CHECK-GI: // %bb.0:
2166 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff
2167 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2168 ; CHECK-GI-NEXT: ret
2169 %tmp1 = and <4 x i32> %a, < i32 16711935, i32 16711935, i32 16711935, i32 16711935>
2170 ret <4 x i32> %tmp1
2171 }
2173 define <2 x i64> @and64imm8h_lsl0(<2 x i64> %a) {
2174 ; CHECK-SD-LABEL: and64imm8h_lsl0:
2175 ; CHECK-SD: // %bb.0:
2176 ; CHECK-SD-NEXT: bic v0.8h, #255
2177 ; CHECK-SD-NEXT: ret
2178 ;
2179 ; CHECK-GI-LABEL: and64imm8h_lsl0:
2180 ; CHECK-GI: // %bb.0:
2181 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff00
2182 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2183 ; CHECK-GI-NEXT: ret
2184 %tmp1 = and <2 x i64> %a, < i64 -71777214294589696, i64 -71777214294589696>
2185 ret <2 x i64> %tmp1
2186 }
2188 define <2 x i64> @and64imm8h_lsl8(<2 x i64> %a) {
2189 ; CHECK-SD-LABEL: and64imm8h_lsl8:
2190 ; CHECK-SD: // %bb.0:
2191 ; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8
2192 ; CHECK-SD-NEXT: ret
2193 ;
2194 ; CHECK-GI-LABEL: and64imm8h_lsl8:
2195 ; CHECK-GI: // %bb.0:
2196 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff
2197 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2198 ; CHECK-GI-NEXT: ret
2199 %tmp1 = and <2 x i64> %a, < i64 71777214294589695, i64 71777214294589695>
2200 ret <2 x i64> %tmp1
2201 }
2203 define <8 x i16> @bic_shifted_knownbits(<8 x i16> %v) {
2204 ; CHECK-SD-LABEL: bic_shifted_knownbits:
2205 ; CHECK-SD: // %bb.0: // %entry
2206 ; CHECK-SD-NEXT: ushr v0.8h, v0.8h, #9
2207 ; CHECK-SD-NEXT: bic v0.8h, #126
2208 ; CHECK-SD-NEXT: ret
2209 ;
2210 ; CHECK-GI-LABEL: bic_shifted_knownbits:
2211 ; CHECK-GI: // %bb.0: // %entry
2212 ; CHECK-GI-NEXT: movi v1.8h, #1
2213 ; CHECK-GI-NEXT: ushr v0.8h, v0.8h, #9
2214 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2215 ; CHECK-GI-NEXT: ret
2216 entry:
2217 %vshr_n = lshr <8 x i16> %v, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
2218 %and.i = and <8 x i16> %vshr_n, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
2219 ret <8 x i16> %and.i
2220 }
2222 define <8 x i32> @bic_shifted_knownbits2(<8 x i16> %v) {
2223 ; CHECK-SD-LABEL: bic_shifted_knownbits2:
2224 ; CHECK-SD: // %bb.0: // %entry
2225 ; CHECK-SD-NEXT: ushll v2.4s, v0.4h, #0
2226 ; CHECK-SD-NEXT: ushll2 v1.4s, v0.8h, #0
2227 ; CHECK-SD-NEXT: bic v2.4s, #255, lsl #8
2228 ; CHECK-SD-NEXT: bic v1.4s, #255, lsl #8
2229 ; CHECK-SD-NEXT: mov v0.16b, v2.16b
2230 ; CHECK-SD-NEXT: ret
2231 ;
2232 ; CHECK-GI-LABEL: bic_shifted_knownbits2:
2233 ; CHECK-GI: // %bb.0: // %entry
2234 ; CHECK-GI-NEXT: adrp x8, .LCPI145_0
2235 ; CHECK-GI-NEXT: ushll v1.4s, v0.4h, #0
2236 ; CHECK-GI-NEXT: ushll2 v2.4s, v0.8h, #0
2237 ; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI145_0]
2238 ; CHECK-GI-NEXT: and v0.16b, v1.16b, v3.16b
2239 ; CHECK-GI-NEXT: and v1.16b, v2.16b, v3.16b
2240 ; CHECK-GI-NEXT: ret
2241 entry:
2242 %vshr_n = zext <8 x i16> %v to <8 x i32>
2243 %and.i = and <8 x i32> %vshr_n, <i32 4293918975, i32 4293918975, i32 4293918975, i32 4293918975, i32 4293918975, i32 4293918975, i32 4293918975, i32 4293918975>
2244 ret <8 x i32> %and.i
2245 }
2247 define <8 x i32> @bic_shifted_knownbits3(<8 x i16> %v) {
2248 ; CHECK-SD-LABEL: bic_shifted_knownbits3:
2249 ; CHECK-SD: // %bb.0:
2250 ; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8
2251 ; CHECK-SD-NEXT: ushll2 v1.4s, v0.8h, #0
2252 ; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
2253 ; CHECK-SD-NEXT: ret
2254 ;
2255 ; CHECK-GI-LABEL: bic_shifted_knownbits3:
2256 ; CHECK-GI: // %bb.0:
2257 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff
2258 ; CHECK-GI-NEXT: and v1.16b, v0.16b, v1.16b
2259 ; CHECK-GI-NEXT: ushll v0.4s, v1.4h, #0
2260 ; CHECK-GI-NEXT: ushll2 v1.4s, v1.8h, #0
2261 ; CHECK-GI-NEXT: ret
2262 %a = and <8 x i16> %v, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
2263 %and.i = zext <8 x i16> %a to <8 x i32>
2264 ret <8 x i32> %and.i
2265 }
2268 define <8 x i32> @bic_shifted_knownbits4(<8 x i32> %v) {
2269 ; CHECK-SD-LABEL: bic_shifted_knownbits4:
2270 ; CHECK-SD: // %bb.0: // %entry
2271 ; CHECK-SD-NEXT: shl v1.4s, v1.4s, #8
2272 ; CHECK-SD-NEXT: shl v0.4s, v0.4s, #8
2273 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #8
2274 ; CHECK-SD-NEXT: bic v1.4s, #255, lsl #8
2275 ; CHECK-SD-NEXT: ret
2276 ;
2277 ; CHECK-GI-LABEL: bic_shifted_knownbits4:
2278 ; CHECK-GI: // %bb.0: // %entry
2279 ; CHECK-GI-NEXT: movi v2.2d, #0xffff0000ffff0000
2280 ; CHECK-GI-NEXT: shl v0.4s, v0.4s, #8
2281 ; CHECK-GI-NEXT: shl v1.4s, v1.4s, #8
2282 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b
2283 ; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b
2284 ; CHECK-GI-NEXT: ret
2285 entry:
2286 %vshr_n = shl <8 x i32> %v, <i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
2287 %and.i = and <8 x i32> %vshr_n, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>
2288 ret <8 x i32> %and.i
2289 }
2291 define <8 x i8> @orr8imm2s_lsl0(<8 x i8> %a) {
2292 ; CHECK-SD-LABEL: orr8imm2s_lsl0:
2293 ; CHECK-SD: // %bb.0:
2294 ; CHECK-SD-NEXT: orr v0.2s, #255
2295 ; CHECK-SD-NEXT: ret
2296 ;
2297 ; CHECK-GI-LABEL: orr8imm2s_lsl0:
2298 ; CHECK-GI: // %bb.0:
2299 ; CHECK-GI-NEXT: adrp x8, .LCPI148_0
2300 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI148_0]
2301 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2302 ; CHECK-GI-NEXT: ret
2303 %tmp1 = or <8 x i8> %a, < i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0>
2304 ret <8 x i8> %tmp1
2305 }
2307 define <8 x i8> @orr8imm2s_lsl8(<8 x i8> %a) {
2308 ; CHECK-SD-LABEL: orr8imm2s_lsl8:
2309 ; CHECK-SD: // %bb.0:
2310 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #8
2311 ; CHECK-SD-NEXT: ret
2312 ;
2313 ; CHECK-GI-LABEL: orr8imm2s_lsl8:
2314 ; CHECK-GI: // %bb.0:
2315 ; CHECK-GI-NEXT: adrp x8, .LCPI149_0
2316 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI149_0]
2317 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2318 ; CHECK-GI-NEXT: ret
2319 %tmp1 = or <8 x i8> %a, < i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0>
2320 ret <8 x i8> %tmp1
2321 }
2323 define <8 x i8> @orr8imm2s_lsl16(<8 x i8> %a) {
2324 ; CHECK-SD-LABEL: orr8imm2s_lsl16:
2325 ; CHECK-SD: // %bb.0:
2326 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #16
2327 ; CHECK-SD-NEXT: ret
2328 ;
2329 ; CHECK-GI-LABEL: orr8imm2s_lsl16:
2330 ; CHECK-GI: // %bb.0:
2331 ; CHECK-GI-NEXT: adrp x8, .LCPI150_0
2332 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI150_0]
2333 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2334 ; CHECK-GI-NEXT: ret
2335 %tmp1 = or <8 x i8> %a, < i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0>
2336 ret <8 x i8> %tmp1
2337 }
2339 define <8 x i8> @orr8imm2s_lsl24(<8 x i8> %a) {
2340 ; CHECK-SD-LABEL: orr8imm2s_lsl24:
2341 ; CHECK-SD: // %bb.0:
2342 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #24
2343 ; CHECK-SD-NEXT: ret
2344 ;
2345 ; CHECK-GI-LABEL: orr8imm2s_lsl24:
2346 ; CHECK-GI: // %bb.0:
2347 ; CHECK-GI-NEXT: adrp x8, .LCPI151_0
2348 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI151_0]
2349 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2350 ; CHECK-GI-NEXT: ret
2351 %tmp1 = or <8 x i8> %a, < i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255>
2352 ret <8 x i8> %tmp1
2353 }
2355 define <4 x i16> @orr16imm2s_lsl0(<4 x i16> %a) {
2356 ; CHECK-SD-LABEL: orr16imm2s_lsl0:
2357 ; CHECK-SD: // %bb.0:
2358 ; CHECK-SD-NEXT: orr v0.2s, #255
2359 ; CHECK-SD-NEXT: ret
2360 ;
2361 ; CHECK-GI-LABEL: orr16imm2s_lsl0:
2362 ; CHECK-GI: // %bb.0:
2363 ; CHECK-GI-NEXT: adrp x8, .LCPI152_0
2364 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI152_0]
2365 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2366 ; CHECK-GI-NEXT: ret
2367 %tmp1 = or <4 x i16> %a, < i16 255, i16 0, i16 255, i16 0>
2368 ret <4 x i16> %tmp1
2369 }
2371 define <4 x i16> @orr16imm2s_lsl8(<4 x i16> %a) {
2372 ; CHECK-SD-LABEL: orr16imm2s_lsl8:
2373 ; CHECK-SD: // %bb.0:
2374 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #8
2375 ; CHECK-SD-NEXT: ret
2376 ;
2377 ; CHECK-GI-LABEL: orr16imm2s_lsl8:
2378 ; CHECK-GI: // %bb.0:
2379 ; CHECK-GI-NEXT: adrp x8, .LCPI153_0
2380 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI153_0]
2381 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2382 ; CHECK-GI-NEXT: ret
2383 %tmp1 = or <4 x i16> %a, < i16 65280, i16 0, i16 65280, i16 0>
2384 ret <4 x i16> %tmp1
2385 }
2387 define <4 x i16> @orr16imm2s_lsl16(<4 x i16> %a) {
2388 ; CHECK-SD-LABEL: orr16imm2s_lsl16:
2389 ; CHECK-SD: // %bb.0:
2390 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #16
2391 ; CHECK-SD-NEXT: ret
2392 ;
2393 ; CHECK-GI-LABEL: orr16imm2s_lsl16:
2394 ; CHECK-GI: // %bb.0:
2395 ; CHECK-GI-NEXT: adrp x8, .LCPI154_0
2396 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI154_0]
2397 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2398 ; CHECK-GI-NEXT: ret
2399 %tmp1 = or <4 x i16> %a, < i16 0, i16 255, i16 0, i16 255>
2400 ret <4 x i16> %tmp1
2401 }
2403 define <4 x i16> @orr16imm2s_lsl24(<4 x i16> %a) {
2404 ; CHECK-SD-LABEL: orr16imm2s_lsl24:
2405 ; CHECK-SD: // %bb.0:
2406 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #24
2407 ; CHECK-SD-NEXT: ret
2408 ;
2409 ; CHECK-GI-LABEL: orr16imm2s_lsl24:
2410 ; CHECK-GI: // %bb.0:
2411 ; CHECK-GI-NEXT: adrp x8, .LCPI155_0
2412 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI155_0]
2413 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2414 ; CHECK-GI-NEXT: ret
2415 %tmp1 = or <4 x i16> %a, < i16 0, i16 65280, i16 0, i16 65280>
2416 ret <4 x i16> %tmp1
2417 }
2419 define <1 x i64> @orr64imm2s_lsl0(<1 x i64> %a) {
2420 ; CHECK-SD-LABEL: orr64imm2s_lsl0:
2421 ; CHECK-SD: // %bb.0:
2422 ; CHECK-SD-NEXT: orr v0.2s, #255
2423 ; CHECK-SD-NEXT: ret
2424 ;
2425 ; CHECK-GI-LABEL: orr64imm2s_lsl0:
2426 ; CHECK-GI: // %bb.0:
2427 ; CHECK-GI-NEXT: fmov x8, d0
2428 ; CHECK-GI-NEXT: orr x8, x8, #0xff000000ff
2429 ; CHECK-GI-NEXT: fmov d0, x8
2430 ; CHECK-GI-NEXT: ret
2431 %tmp1 = or <1 x i64> %a, < i64 1095216660735>
2432 ret <1 x i64> %tmp1
2433 }
2435 define <1 x i64> @orr64imm2s_lsl8(<1 x i64> %a) {
2436 ; CHECK-SD-LABEL: orr64imm2s_lsl8:
2437 ; CHECK-SD: // %bb.0:
2438 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #8
2439 ; CHECK-SD-NEXT: ret
2440 ;
2441 ; CHECK-GI-LABEL: orr64imm2s_lsl8:
2442 ; CHECK-GI: // %bb.0:
2443 ; CHECK-GI-NEXT: fmov x8, d0
2444 ; CHECK-GI-NEXT: orr x8, x8, #0xff000000ff00
2445 ; CHECK-GI-NEXT: fmov d0, x8
2446 ; CHECK-GI-NEXT: ret
2447 %tmp1 = or <1 x i64> %a, < i64 280375465148160>
2448 ret <1 x i64> %tmp1
2449 }
2451 define <1 x i64> @orr64imm2s_lsl16(<1 x i64> %a) {
2452 ; CHECK-SD-LABEL: orr64imm2s_lsl16:
2453 ; CHECK-SD: // %bb.0:
2454 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #16
2455 ; CHECK-SD-NEXT: ret
2456 ;
2457 ; CHECK-GI-LABEL: orr64imm2s_lsl16:
2458 ; CHECK-GI: // %bb.0:
2459 ; CHECK-GI-NEXT: fmov x8, d0
2460 ; CHECK-GI-NEXT: orr x8, x8, #0xff000000ff0000
2461 ; CHECK-GI-NEXT: fmov d0, x8
2462 ; CHECK-GI-NEXT: ret
2463 %tmp1 = or <1 x i64> %a, < i64 71776119077928960>
2464 ret <1 x i64> %tmp1
2465 }
2467 define <1 x i64> @orr64imm2s_lsl24(<1 x i64> %a) {
2468 ; CHECK-SD-LABEL: orr64imm2s_lsl24:
2469 ; CHECK-SD: // %bb.0:
2470 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #24
2471 ; CHECK-SD-NEXT: ret
2472 ;
2473 ; CHECK-GI-LABEL: orr64imm2s_lsl24:
2474 ; CHECK-GI: // %bb.0:
2475 ; CHECK-GI-NEXT: fmov x8, d0
2476 ; CHECK-GI-NEXT: orr x8, x8, #0xff000000ff000000
2477 ; CHECK-GI-NEXT: fmov d0, x8
2478 ; CHECK-GI-NEXT: ret
2479 %tmp1 = or <1 x i64> %a, < i64 -72057589759737856>
2480 ret <1 x i64> %tmp1
2481 }
2483 define <16 x i8> @orr8imm4s_lsl0(<16 x i8> %a) {
2484 ; CHECK-SD-LABEL: orr8imm4s_lsl0:
2485 ; CHECK-SD: // %bb.0:
2486 ; CHECK-SD-NEXT: orr v0.4s, #255
2487 ; CHECK-SD-NEXT: ret
2488 ;
2489 ; CHECK-GI-LABEL: orr8imm4s_lsl0:
2490 ; CHECK-GI: // %bb.0:
2491 ; CHECK-GI-NEXT: adrp x8, .LCPI160_0
2492 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI160_0]
2493 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2494 ; CHECK-GI-NEXT: ret
2495 %tmp1 = or <16 x i8> %a, < i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0>
2496 ret <16 x i8> %tmp1
2497 }
2499 define <16 x i8> @orr8imm4s_lsl8(<16 x i8> %a) {
2500 ; CHECK-SD-LABEL: orr8imm4s_lsl8:
2501 ; CHECK-SD: // %bb.0:
2502 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #8
2503 ; CHECK-SD-NEXT: ret
2504 ;
2505 ; CHECK-GI-LABEL: orr8imm4s_lsl8:
2506 ; CHECK-GI: // %bb.0:
2507 ; CHECK-GI-NEXT: adrp x8, .LCPI161_0
2508 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI161_0]
2509 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2510 ; CHECK-GI-NEXT: ret
2511 %tmp1 = or <16 x i8> %a, < i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0>
2512 ret <16 x i8> %tmp1
2513 }
2515 define <16 x i8> @orr8imm4s_lsl16(<16 x i8> %a) {
2516 ; CHECK-SD-LABEL: orr8imm4s_lsl16:
2517 ; CHECK-SD: // %bb.0:
2518 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #16
2519 ; CHECK-SD-NEXT: ret
2520 ;
2521 ; CHECK-GI-LABEL: orr8imm4s_lsl16:
2522 ; CHECK-GI: // %bb.0:
2523 ; CHECK-GI-NEXT: adrp x8, .LCPI162_0
2524 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI162_0]
2525 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2526 ; CHECK-GI-NEXT: ret
2527 %tmp1 = or <16 x i8> %a, < i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0>
2528 ret <16 x i8> %tmp1
2529 }
2531 define <16 x i8> @orr8imm4s_lsl24(<16 x i8> %a) {
2532 ; CHECK-SD-LABEL: orr8imm4s_lsl24:
2533 ; CHECK-SD: // %bb.0:
2534 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #24
2535 ; CHECK-SD-NEXT: ret
2536 ;
2537 ; CHECK-GI-LABEL: orr8imm4s_lsl24:
2538 ; CHECK-GI: // %bb.0:
2539 ; CHECK-GI-NEXT: adrp x8, .LCPI163_0
2540 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI163_0]
2541 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2542 ; CHECK-GI-NEXT: ret
2543 %tmp1 = or <16 x i8> %a, < i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255>
2544 ret <16 x i8> %tmp1
2545 }
2547 define <8 x i16> @orr16imm4s_lsl0(<8 x i16> %a) {
2548 ; CHECK-SD-LABEL: orr16imm4s_lsl0:
2549 ; CHECK-SD: // %bb.0:
2550 ; CHECK-SD-NEXT: orr v0.4s, #255
2551 ; CHECK-SD-NEXT: ret
2552 ;
2553 ; CHECK-GI-LABEL: orr16imm4s_lsl0:
2554 ; CHECK-GI: // %bb.0:
2555 ; CHECK-GI-NEXT: adrp x8, .LCPI164_0
2556 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI164_0]
2557 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2558 ; CHECK-GI-NEXT: ret
2559 %tmp1 = or <8 x i16> %a, < i16 255, i16 0, i16 255, i16 0, i16 255, i16 0, i16 255, i16 0>
2560 ret <8 x i16> %tmp1
2561 }
2563 define <8 x i16> @orr16imm4s_lsl8(<8 x i16> %a) {
2564 ; CHECK-SD-LABEL: orr16imm4s_lsl8:
2565 ; CHECK-SD: // %bb.0:
2566 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #8
2567 ; CHECK-SD-NEXT: ret
2568 ;
2569 ; CHECK-GI-LABEL: orr16imm4s_lsl8:
2570 ; CHECK-GI: // %bb.0:
2571 ; CHECK-GI-NEXT: adrp x8, .LCPI165_0
2572 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI165_0]
2573 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2574 ; CHECK-GI-NEXT: ret
2575 %tmp1 = or <8 x i16> %a, < i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0>
2576 ret <8 x i16> %tmp1
2577 }
2579 define <8 x i16> @orr16imm4s_lsl16(<8 x i16> %a) {
2580 ; CHECK-SD-LABEL: orr16imm4s_lsl16:
2581 ; CHECK-SD: // %bb.0:
2582 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #16
2583 ; CHECK-SD-NEXT: ret
2584 ;
2585 ; CHECK-GI-LABEL: orr16imm4s_lsl16:
2586 ; CHECK-GI: // %bb.0:
2587 ; CHECK-GI-NEXT: adrp x8, .LCPI166_0
2588 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI166_0]
2589 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2590 ; CHECK-GI-NEXT: ret
2591 %tmp1 = or <8 x i16> %a, < i16 0, i16 255, i16 0, i16 255, i16 0, i16 255, i16 0, i16 255>
2592 ret <8 x i16> %tmp1
2593 }
2595 define <8 x i16> @orr16imm4s_lsl24(<8 x i16> %a) {
2596 ; CHECK-SD-LABEL: orr16imm4s_lsl24:
2597 ; CHECK-SD: // %bb.0:
2598 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #24
2599 ; CHECK-SD-NEXT: ret
2600 ;
2601 ; CHECK-GI-LABEL: orr16imm4s_lsl24:
2602 ; CHECK-GI: // %bb.0:
2603 ; CHECK-GI-NEXT: adrp x8, .LCPI167_0
2604 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI167_0]
2605 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2606 ; CHECK-GI-NEXT: ret
2607 %tmp1 = or <8 x i16> %a, < i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280>
2608 ret <8 x i16> %tmp1
2609 }
2611 define <2 x i64> @orr64imm4s_lsl0(<2 x i64> %a) {
2612 ; CHECK-SD-LABEL: orr64imm4s_lsl0:
2613 ; CHECK-SD: // %bb.0:
2614 ; CHECK-SD-NEXT: orr v0.4s, #255
2615 ; CHECK-SD-NEXT: ret
2616 ;
2617 ; CHECK-GI-LABEL: orr64imm4s_lsl0:
2618 ; CHECK-GI: // %bb.0:
2619 ; CHECK-GI-NEXT: movi v1.2d, #0x0000ff000000ff
2620 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2621 ; CHECK-GI-NEXT: ret
2622 %tmp1 = or <2 x i64> %a, < i64 1095216660735, i64 1095216660735>
2623 ret <2 x i64> %tmp1
2624 }
2626 define <2 x i64> @orr64imm4s_lsl8(<2 x i64> %a) {
2627 ; CHECK-SD-LABEL: orr64imm4s_lsl8:
2628 ; CHECK-SD: // %bb.0:
2629 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #8
2630 ; CHECK-SD-NEXT: ret
2631 ;
2632 ; CHECK-GI-LABEL: orr64imm4s_lsl8:
2633 ; CHECK-GI: // %bb.0:
2634 ; CHECK-GI-NEXT: movi v1.2d, #0x00ff000000ff00
2635 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2636 ; CHECK-GI-NEXT: ret
2637 %tmp1 = or <2 x i64> %a, < i64 280375465148160, i64 280375465148160>
2638 ret <2 x i64> %tmp1
2639 }
2641 define <2 x i64> @orr64imm4s_lsl16(<2 x i64> %a) {
2642 ; CHECK-SD-LABEL: orr64imm4s_lsl16:
2643 ; CHECK-SD: // %bb.0:
2644 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #16
2645 ; CHECK-SD-NEXT: ret
2646 ;
2647 ; CHECK-GI-LABEL: orr64imm4s_lsl16:
2648 ; CHECK-GI: // %bb.0:
2649 ; CHECK-GI-NEXT: movi v1.2d, #0xff000000ff0000
2650 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2651 ; CHECK-GI-NEXT: ret
2652 %tmp1 = or <2 x i64> %a, < i64 71776119077928960, i64 71776119077928960>
2653 ret <2 x i64> %tmp1
2654 }
2656 define <2 x i64> @orr64imm4s_lsl24(<2 x i64> %a) {
2657 ; CHECK-SD-LABEL: orr64imm4s_lsl24:
2658 ; CHECK-SD: // %bb.0:
2659 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #24
2660 ; CHECK-SD-NEXT: ret
2661 ;
2662 ; CHECK-GI-LABEL: orr64imm4s_lsl24:
2663 ; CHECK-GI: // %bb.0:
2664 ; CHECK-GI-NEXT: movi v1.2d, #0xff000000ff000000
2665 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2666 ; CHECK-GI-NEXT: ret
2667 %tmp1 = or <2 x i64> %a, < i64 -72057589759737856, i64 -72057589759737856>
2668 ret <2 x i64> %tmp1
2669 }
2671 define <8 x i8> @orr8imm4h_lsl0(<8 x i8> %a) {
2672 ; CHECK-SD-LABEL: orr8imm4h_lsl0:
2673 ; CHECK-SD: // %bb.0:
2674 ; CHECK-SD-NEXT: orr v0.4h, #255
2675 ; CHECK-SD-NEXT: ret
2676 ;
2677 ; CHECK-GI-LABEL: orr8imm4h_lsl0:
2678 ; CHECK-GI: // %bb.0:
2679 ; CHECK-GI-NEXT: adrp x8, .LCPI172_0
2680 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI172_0]
2681 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2682 ; CHECK-GI-NEXT: ret
2683 %tmp1 = or <8 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
2684 ret <8 x i8> %tmp1
2685 }
2687 define <8 x i8> @orr8imm4h_lsl8(<8 x i8> %a) {
2688 ; CHECK-SD-LABEL: orr8imm4h_lsl8:
2689 ; CHECK-SD: // %bb.0:
2690 ; CHECK-SD-NEXT: orr v0.4h, #255, lsl #8
2691 ; CHECK-SD-NEXT: ret
2692 ;
2693 ; CHECK-GI-LABEL: orr8imm4h_lsl8:
2694 ; CHECK-GI: // %bb.0:
2695 ; CHECK-GI-NEXT: adrp x8, .LCPI173_0
2696 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI173_0]
2697 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2698 ; CHECK-GI-NEXT: ret
2699 %tmp1 = or <8 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
2700 ret <8 x i8> %tmp1
2701 }
2703 define <2 x i32> @orr16imm4h_lsl0(<2 x i32> %a) {
2704 ; CHECK-SD-LABEL: orr16imm4h_lsl0:
2705 ; CHECK-SD: // %bb.0:
2706 ; CHECK-SD-NEXT: orr v0.4h, #255
2707 ; CHECK-SD-NEXT: ret
2708 ;
2709 ; CHECK-GI-LABEL: orr16imm4h_lsl0:
2710 ; CHECK-GI: // %bb.0:
2711 ; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff
2712 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2713 ; CHECK-GI-NEXT: ret
2714 %tmp1 = or <2 x i32> %a, < i32 16711935, i32 16711935>
2715 ret <2 x i32> %tmp1
2716 }
2718 define <2 x i32> @orr16imm4h_lsl8(<2 x i32> %a) {
2719 ; CHECK-SD-LABEL: orr16imm4h_lsl8:
2720 ; CHECK-SD: // %bb.0:
2721 ; CHECK-SD-NEXT: orr v0.4h, #255, lsl #8
2722 ; CHECK-SD-NEXT: ret
2723 ;
2724 ; CHECK-GI-LABEL: orr16imm4h_lsl8:
2725 ; CHECK-GI: // %bb.0:
2726 ; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff00
2727 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2728 ; CHECK-GI-NEXT: ret
2729 %tmp1 = or <2 x i32> %a, < i32 4278255360, i32 4278255360>
2730 ret <2 x i32> %tmp1
2731 }
2733 define <1 x i64> @orr64imm4h_lsl0(<1 x i64> %a) {
2734 ; CHECK-SD-LABEL: orr64imm4h_lsl0:
2735 ; CHECK-SD: // %bb.0:
2736 ; CHECK-SD-NEXT: orr v0.4h, #255
2737 ; CHECK-SD-NEXT: ret
2738 ;
2739 ; CHECK-GI-LABEL: orr64imm4h_lsl0:
2740 ; CHECK-GI: // %bb.0:
2741 ; CHECK-GI-NEXT: fmov x8, d0
2742 ; CHECK-GI-NEXT: orr x8, x8, #0xff00ff00ff00ff
2743 ; CHECK-GI-NEXT: fmov d0, x8
2744 ; CHECK-GI-NEXT: ret
2745 %tmp1 = or <1 x i64> %a, < i64 71777214294589695>
2746 ret <1 x i64> %tmp1
2747 }
2749 define <1 x i64> @orr64imm4h_lsl8(<1 x i64> %a) {
2750 ; CHECK-SD-LABEL: orr64imm4h_lsl8:
2751 ; CHECK-SD: // %bb.0:
2752 ; CHECK-SD-NEXT: orr v0.4h, #255, lsl #8
2753 ; CHECK-SD-NEXT: ret
2754 ;
2755 ; CHECK-GI-LABEL: orr64imm4h_lsl8:
2756 ; CHECK-GI: // %bb.0:
2757 ; CHECK-GI-NEXT: fmov x8, d0
2758 ; CHECK-GI-NEXT: orr x8, x8, #0xff00ff00ff00ff00
2759 ; CHECK-GI-NEXT: fmov d0, x8
2760 ; CHECK-GI-NEXT: ret
2761 %tmp1 = or <1 x i64> %a, < i64 -71777214294589696>
2762 ret <1 x i64> %tmp1
2763 }
2765 define <16 x i8> @orr8imm8h_lsl0(<16 x i8> %a) {
2766 ; CHECK-SD-LABEL: orr8imm8h_lsl0:
2767 ; CHECK-SD: // %bb.0:
2768 ; CHECK-SD-NEXT: orr v0.8h, #255
2769 ; CHECK-SD-NEXT: ret
2770 ;
2771 ; CHECK-GI-LABEL: orr8imm8h_lsl0:
2772 ; CHECK-GI: // %bb.0:
2773 ; CHECK-GI-NEXT: adrp x8, .LCPI178_0
2774 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI178_0]
2775 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2776 ; CHECK-GI-NEXT: ret
2777 %tmp1 = or <16 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
2778 ret <16 x i8> %tmp1
2779 }
2781 define <16 x i8> @orr8imm8h_lsl8(<16 x i8> %a) {
2782 ; CHECK-SD-LABEL: orr8imm8h_lsl8:
2783 ; CHECK-SD: // %bb.0:
2784 ; CHECK-SD-NEXT: orr v0.8h, #255, lsl #8
2785 ; CHECK-SD-NEXT: ret
2786 ;
2787 ; CHECK-GI-LABEL: orr8imm8h_lsl8:
2788 ; CHECK-GI: // %bb.0:
2789 ; CHECK-GI-NEXT: adrp x8, .LCPI179_0
2790 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI179_0]
2791 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2792 ; CHECK-GI-NEXT: ret
2793 %tmp1 = or <16 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
2794 ret <16 x i8> %tmp1
2795 }
2797 define <4 x i32> @orr16imm8h_lsl0(<4 x i32> %a) {
2798 ; CHECK-SD-LABEL: orr16imm8h_lsl0:
2799 ; CHECK-SD: // %bb.0:
2800 ; CHECK-SD-NEXT: orr v0.8h, #255
2801 ; CHECK-SD-NEXT: ret
2802 ;
2803 ; CHECK-GI-LABEL: orr16imm8h_lsl0:
2804 ; CHECK-GI: // %bb.0:
2805 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff
2806 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2807 ; CHECK-GI-NEXT: ret
2808 %tmp1 = or <4 x i32> %a, < i32 16711935, i32 16711935, i32 16711935, i32 16711935>
2809 ret <4 x i32> %tmp1
2810 }
2812 define <4 x i32> @orr16imm8h_lsl8(<4 x i32> %a) {
2813 ; CHECK-SD-LABEL: orr16imm8h_lsl8:
2814 ; CHECK-SD: // %bb.0:
2815 ; CHECK-SD-NEXT: orr v0.8h, #255, lsl #8
2816 ; CHECK-SD-NEXT: ret
2817 ;
2818 ; CHECK-GI-LABEL: orr16imm8h_lsl8:
2819 ; CHECK-GI: // %bb.0:
2820 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff00
2821 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2822 ; CHECK-GI-NEXT: ret
2823 %tmp1 = or <4 x i32> %a, < i32 4278255360, i32 4278255360, i32 4278255360, i32 4278255360>
2824 ret <4 x i32> %tmp1
2825 }
2827 define <2 x i64> @orr64imm8h_lsl0(<2 x i64> %a) {
2828 ; CHECK-SD-LABEL: orr64imm8h_lsl0:
2829 ; CHECK-SD: // %bb.0:
2830 ; CHECK-SD-NEXT: orr v0.8h, #255
2831 ; CHECK-SD-NEXT: ret
2832 ;
2833 ; CHECK-GI-LABEL: orr64imm8h_lsl0:
2834 ; CHECK-GI: // %bb.0:
2835 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff
2836 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2837 ; CHECK-GI-NEXT: ret
2838 %tmp1 = or <2 x i64> %a, < i64 71777214294589695, i64 71777214294589695>
2839 ret <2 x i64> %tmp1
2840 }
2842 define <2 x i64> @orr64imm8h_lsl8(<2 x i64> %a) {
2843 ; CHECK-SD-LABEL: orr64imm8h_lsl8:
2844 ; CHECK-SD: // %bb.0:
2845 ; CHECK-SD-NEXT: orr v0.8h, #255, lsl #8
2846 ; CHECK-SD-NEXT: ret
2847 ;
2848 ; CHECK-GI-LABEL: orr64imm8h_lsl8:
2849 ; CHECK-GI: // %bb.0:
2850 ; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff00
2851 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2852 ; CHECK-GI-NEXT: ret
2853 %tmp1 = or <2 x i64> %a, < i64 -71777214294589696, i64 -71777214294589696>
2854 ret <2 x i64> %tmp1
2855 }