[clang][modules] Don't prevent translation of FW_Private includes when explicitly...
[llvm-project.git] / llvm / test / TableGen / GlobalISelCombinerEmitter / match-table-typeof.td
blob496d86aeef2d10a98f78303b7f2ed95083ef4603
1 // RUN: llvm-tblgen -I %p/../../../include -gen-global-isel-combiner \
2 // RUN:     -combiners=MyCombiner %s | \
3 // RUN: FileCheck %s
5 include "llvm/Target/Target.td"
6 include "llvm/Target/GlobalISel/Combine.td"
8 def MyTargetISA : InstrInfo;
9 def MyTarget : Target { let InstructionSet = MyTargetISA; }
11 def Test0 : GICombineRule<
12   (defs root:$dst),
13   (match (G_MUL $dst, $src, -1)),
14   (apply (G_SUB $dst, (GITypeOf<"$src"> 0), $tmp),
15          (G_CONSTANT GITypeOf<"$dst">:$tmp, (GITypeOf<"$src"> 42)))>;
17 // CHECK:      const int64_t *GenMyCombiner::getMatchTable() const {
18 // CHECK-NEXT:   constexpr static int64_t MatchTable0[] = {
19 // CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 0*/ 57, // Rule ID 0 //
20 // CHECK-NEXT:       GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled,
21 // CHECK-NEXT:       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL,
22 // CHECK-NEXT:       // MIs[0] dst
23 // CHECK-NEXT:       GIM_RecordRegType, /*MI*/0, /*Op*/0, /*TempTypeIdx*/-1,
24 // CHECK-NEXT:       // MIs[0] src
25 // CHECK-NEXT:       GIM_RecordRegType, /*MI*/0, /*Op*/1, /*TempTypeIdx*/-2,
26 // CHECK-NEXT:       // MIs[0] Operand 2
27 // CHECK-NEXT:       GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
28 // CHECK-NEXT:       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/-2,
29 // CHECK-NEXT:       GIR_BuildConstant, /*TempRegID*/1, /*Val*/0,
30 // CHECK-NEXT:       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/-1,
31 // CHECK-NEXT:       // Combiner Rule #0: Test0
32 // CHECK-NEXT:       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::G_CONSTANT,
33 // CHECK-NEXT:       GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
34 // CHECK-NEXT:       GIR_AddCImm, /*InsnID*/0, /*Type*/-2, /*Imm*/42,
35 // CHECK-NEXT:       GIR_EraseFromParent, /*InsnID*/0,
36 // CHECK-NEXT:       GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::G_SUB,
37 // CHECK-NEXT:       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // dst
38 // CHECK-NEXT:       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
39 // CHECK-NEXT:       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
40 // CHECK-NEXT:       GIR_Done,
41 // CHECK-NEXT:     // Label 0: @57
42 // CHECK-NEXT:     GIM_Reject,
43 // CHECK-NEXT:     };
44 // CHECK-NEXT:   return MatchTable0;
45 // CHECK-NEXT: }
47 def MyCombiner: GICombiner<"GenMyCombiner", [
48   Test0
49 ]>;