clang/test/CodeGen/attr-target-version.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals --include-generated-funcs --global-value-regex ".*"
   2 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -o - %s | FileCheck %s
   3 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature -fmv -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK-NOFMV
   4
   5 int __attribute__((target_version("rng+flagm+fp16fml"))) fmv(void) { return 1; }
   6 int __attribute__((target_version("flagm2+sme-i16i64"))) fmv(void) { return 2; }
   7 int __attribute__((target_version("lse+sha2"))) fmv(void) { return 3; }
   8 int __attribute__((target_version("dotprod+ls64"))) fmv(void) { return 4; }
   9 int __attribute__((target_version("fp16fml+memtag"))) fmv(void) { return 5; }
  10 int __attribute__((target_version("fp+aes"))) fmv(void) { return 6; }
  11 int __attribute__((target_version("crc+ls64"))) fmv(void) { return 7; }
  12 int __attribute__((target_version("bti"))) fmv(void) { return 8; }
  13 int __attribute__((target_version("sme2"))) fmv(void) { return 9; }
  14 int __attribute__((target_version("default"))) fmv(void) { return 0; }
  15 int __attribute__((target_version("ls64+simd"))) fmv_one(void) { return 1; }
  16 int __attribute__((target_version("dpb"))) fmv_one(void) { return 2; }
  17 int __attribute__((target_version("default"))) fmv_one(void) { return 0; }
  18 int __attribute__((target_version("fp"))) fmv_two(void) { return 1; }
  19 int __attribute__((target_version("simd"))) fmv_two(void) { return 2; }
  20 int __attribute__((target_version("fp16+simd"))) fmv_two(void) { return 4; }
  21 int __attribute__((target_version("default"))) fmv_two(void) { return 0; }
  22 int foo() {
  23   return fmv()+fmv_one()+fmv_two();
  24 }
  25
  26 inline int __attribute__((target_version("sha2+aes+f64mm"))) fmv_inline(void) { return 1; }
  27 inline int __attribute__((target_version("fp16+fcma+rdma+sme+ fp16 "))) fmv_inline(void) { return 2; }
  28 inline int __attribute__((target_version("sha3+i8mm+f32mm"))) fmv_inline(void) { return 12; }
  29 inline int __attribute__((target_version("dit+bf16"))) fmv_inline(void) { return 8; }
  30 inline int __attribute__((target_version("dpb+rcpc2 "))) fmv_inline(void) { return 6; }
  31 inline int __attribute__((target_version(" dpb2 + jscvt"))) fmv_inline(void) { return 7; }
  32 inline int __attribute__((target_version("rcpc+frintts"))) fmv_inline(void) { return 3; }
  33 inline int __attribute__((target_version("sve+bf16"))) fmv_inline(void) { return 4; }
  34 inline int __attribute__((target_version("sve2-aes+sve2-sha3"))) fmv_inline(void) { return 5; }
  35 inline int __attribute__((target_version("sve2+sve2-aes+sve2-bitperm"))) fmv_inline(void) { return 9; }
  36 inline int __attribute__((target_version("sve2-sm4+memtag"))) fmv_inline(void) { return 10; }
  37 inline int __attribute__((target_version("memtag+rcpc3+mops"))) fmv_inline(void) { return 11; }
  38 inline int __attribute__((target_version("aes+dotprod"))) fmv_inline(void) { return 13; }
  39 inline int __attribute__((target_version("simd+fp16fml"))) fmv_inline(void) { return 14; }
  40 inline int __attribute__((target_version("fp+sm4"))) fmv_inline(void) { return 15; }
  41 inline int __attribute__((target_version("lse+rdm"))) fmv_inline(void) { return 16; }
  42 inline int __attribute__((target_version("default"))) fmv_inline(void) { return 3; }
  43
  44 __attribute__((target_version("ls64"))) int fmv_e(void);
  45 int fmv_e(void) { return 20; }
  46
  47 static __attribute__((target_version("sb"))) inline int fmv_d(void);
  48 static __attribute__((target_version("default"))) inline int fmv_d(void);
  49
  50 int __attribute__((target_version("default"))) fmv_default(void) { return 111; }
  51 int fmv_default(void);
  52
  53 void fmv_c(void);
  54 void __attribute__((target_version("ssbs"))) fmv_c(void){};
  55 void __attribute__((target_version("default"))) fmv_c(void){};
  56
  57 int goo() {
  58   fmv_inline();
  59   fmv_e();
  60   fmv_d();
  61   fmv_c();
  62   return fmv_default();
  63 }
  64 static inline int __attribute__((target_version("sb"))) fmv_d(void) { return 0; }
  65 static inline int __attribute__((target_version(" default "))) fmv_d(void) { return 1; }
  66
  67 static void func(void) {}
  68 inline __attribute__((target_version("default"))) void recb(void) { func(); }
  69 inline __attribute__((target_version("default"))) void reca(void) { recb(); }
  70 void recur(void) { reca(); }
  71
  72 int __attribute__((target_version("default"))) main(void) {
  73   recur();
  74   return goo();
  75 }
  76
  77 typedef int (*Fptr)();
  78 void f(Fptr);
  79 int hoo(void) {
  80   f(fmv);
  81   Fptr fp1 = &fmv;
  82   Fptr fp2 = fmv;
  83   return fp1() + fp2();
  84 }
  85
  86 // This should generate one target version but no resolver.
  87 __attribute__((target_version("default"))) int unused_with_forward_default_decl(void);
  88 __attribute__((target_version("mops"))) int unused_with_forward_default_decl(void) { return 0; }
  89
  90 // This should also generate one target version but no resolver.
  91 extern int unused_with_implicit_extern_forward_default_decl(void);
  92 __attribute__((target_version("dotprod")))
  93 int unused_with_implicit_extern_forward_default_decl(void) { return 0; }
  94
  95 // This should also generate one target version but no resolver.
  96 __attribute__((target_version("aes"))) int unused_with_default_decl(void) { return 0; }
  97 __attribute__((target_version("default"))) int unused_with_default_decl(void);
  98
  99 // This should generate two target versions and the resolver.
 100 __attribute__((target_version("sve"))) int unused_with_default_def(void) { return 0; }
 101 __attribute__((target_version("default"))) int unused_with_default_def(void) { return 1; }
 102
 103 // This should also generate two target versions and the resolver.
 104 __attribute__((target_version("fp16"))) int unused_with_implicit_default_def(void) { return 0; }
 105 int unused_with_implicit_default_def(void) { return 1; }
 106
 107 // This should also generate two target versions and the resolver.
 108 int unused_with_implicit_forward_default_def(void) { return 0; }
 109 __attribute__((target_version("lse"))) int unused_with_implicit_forward_default_def(void) { return 1; }
 110
 111 // This should generate a target version despite the default not being declared.
 112 __attribute__((target_version("rdm"))) int unused_without_default(void) { return 0; }
 113
 114 // These shouldn't generate anything.
 115 int unused_version_declarations(void);
 116 __attribute__((target_version("jscvt"))) int unused_version_declarations(void);
 117 __attribute__((target_version("rdma"))) int unused_version_declarations(void);
 118
 119 // These should generate the default (mangled) version and the resolver.
 120 int default_def_with_version_decls(void) { return 0; }
 121 __attribute__((target_version("jscvt"))) int default_def_with_version_decls(void);
 122 __attribute__((target_version("rdma"))) int default_def_with_version_decls(void);
 123
 124 // The following is guarded because in NOFMV we get errors for calling undeclared functions.
 125 #ifdef __HAVE_FUNCTION_MULTI_VERSIONING
 126 // This should generate a default declaration, two target versions but no resolver.
 127 __attribute__((target_version("jscvt"))) int used_def_without_default_decl(void) { return 1; }
 128 __attribute__((target_version("rdma"))) int used_def_without_default_decl(void) { return 2; }
 129
 130 // This should generate a default declaration but no resolver.
 131 __attribute__((target_version("jscvt"))) int used_decl_without_default_decl(void);
 132 __attribute__((target_version("rdma"))) int used_decl_without_default_decl(void);
 133
 134 int caller(void) { return used_def_without_default_decl() + used_decl_without_default_decl(); }
 135 #endif
 136
 137 //.
 138 // CHECK: @__aarch64_cpu_features = external dso_local global { i64 }
 139 // CHECK: @fmv = weak_odr ifunc i32 (), ptr @fmv.resolver
 140 // CHECK: @fmv_one = weak_odr ifunc i32 (), ptr @fmv_one.resolver
 141 // CHECK: @fmv_two = weak_odr ifunc i32 (), ptr @fmv_two.resolver
 142 // CHECK: @fmv_e = weak_odr ifunc i32 (), ptr @fmv_e.resolver
 143 // CHECK: @fmv_d = internal ifunc i32 (), ptr @fmv_d.resolver
 144 // CHECK: @fmv_c = weak_odr ifunc void (), ptr @fmv_c.resolver
 145 // CHECK: @fmv_inline = weak_odr ifunc i32 (), ptr @fmv_inline.resolver
 146 // CHECK: @unused_with_default_def = weak_odr ifunc i32 (), ptr @unused_with_default_def.resolver
 147 // CHECK: @unused_with_implicit_default_def = weak_odr ifunc i32 (), ptr @unused_with_implicit_default_def.resolver
 148 // CHECK: @unused_with_implicit_forward_default_def = weak_odr ifunc i32 (), ptr @unused_with_implicit_forward_default_def.resolver
 149 // CHECK: @default_def_with_version_decls = weak_odr ifunc i32 (), ptr @default_def_with_version_decls.resolver
 150 //.
 151 // CHECK: Function Attrs: noinline nounwind optnone
 152 // CHECK-LABEL: define {{[^@]+}}@fmv._MflagmMfp16fmlMrng
 153 // CHECK-SAME: () #[[ATTR0:[0-9]+]] {
 154 // CHECK-NEXT:  entry:
 155 // CHECK-NEXT:    ret i32 1
 156 //
 157 //
 158 // CHECK: Function Attrs: noinline nounwind optnone
 159 // CHECK-LABEL: define {{[^@]+}}@fmv._Mflagm2Msme-i16i64
 160 // CHECK-SAME: () #[[ATTR1:[0-9]+]] {
 161 // CHECK-NEXT:  entry:
 162 // CHECK-NEXT:    ret i32 2
 163 //
 164 //
 165 // CHECK: Function Attrs: noinline nounwind optnone
 166 // CHECK-LABEL: define {{[^@]+}}@fmv._MlseMsha2
 167 // CHECK-SAME: () #[[ATTR2:[0-9]+]] {
 168 // CHECK-NEXT:  entry:
 169 // CHECK-NEXT:    ret i32 3
 170 //
 171 //
 172 // CHECK: Function Attrs: noinline nounwind optnone
 173 // CHECK-LABEL: define {{[^@]+}}@fmv._MdotprodMls64
 174 // CHECK-SAME: () #[[ATTR3:[0-9]+]] {
 175 // CHECK-NEXT:  entry:
 176 // CHECK-NEXT:    ret i32 4
 177 //
 178 //
 179 // CHECK: Function Attrs: noinline nounwind optnone
 180 // CHECK-LABEL: define {{[^@]+}}@fmv._Mfp16fmlMmemtag
 181 // CHECK-SAME: () #[[ATTR4:[0-9]+]] {
 182 // CHECK-NEXT:  entry:
 183 // CHECK-NEXT:    ret i32 5
 184 //
 185 //
 186 // CHECK: Function Attrs: noinline nounwind optnone
 187 // CHECK-LABEL: define {{[^@]+}}@fmv._MaesMfp
 188 // CHECK-SAME: () #[[ATTR5:[0-9]+]] {
 189 // CHECK-NEXT:  entry:
 190 // CHECK-NEXT:    ret i32 6
 191 //
 192 //
 193 // CHECK: Function Attrs: noinline nounwind optnone
 194 // CHECK-LABEL: define {{[^@]+}}@fmv._McrcMls64
 195 // CHECK-SAME: () #[[ATTR6:[0-9]+]] {
 196 // CHECK-NEXT:  entry:
 197 // CHECK-NEXT:    ret i32 7
 198 //
 199 //
 200 // CHECK: Function Attrs: noinline nounwind optnone
 201 // CHECK-LABEL: define {{[^@]+}}@fmv._Mbti
 202 // CHECK-SAME: () #[[ATTR7:[0-9]+]] {
 203 // CHECK-NEXT:  entry:
 204 // CHECK-NEXT:    ret i32 8
 205 //
 206 //
 207 // CHECK: Function Attrs: noinline nounwind optnone
 208 // CHECK-LABEL: define {{[^@]+}}@fmv._Msme2
 209 // CHECK-SAME: () #[[ATTR8:[0-9]+]] {
 210 // CHECK-NEXT:  entry:
 211 // CHECK-NEXT:    ret i32 9
 212 //
 213 //
 214 // CHECK: Function Attrs: noinline nounwind optnone
 215 // CHECK-LABEL: define {{[^@]+}}@fmv.default
 216 // CHECK-SAME: () #[[ATTR9:[0-9]+]] {
 217 // CHECK-NEXT:  entry:
 218 // CHECK-NEXT:    ret i32 0
 219 //
 220 //
 221 // CHECK: Function Attrs: noinline nounwind optnone
 222 // CHECK-LABEL: define {{[^@]+}}@fmv_one._Mls64Msimd
 223 // CHECK-SAME: () #[[ATTR10:[0-9]+]] {
 224 // CHECK-NEXT:  entry:
 225 // CHECK-NEXT:    ret i32 1
 226 //
 227 //
 228 // CHECK: Function Attrs: noinline nounwind optnone
 229 // CHECK-LABEL: define {{[^@]+}}@fmv_one._Mdpb
 230 // CHECK-SAME: () #[[ATTR11:[0-9]+]] {
 231 // CHECK-NEXT:  entry:
 232 // CHECK-NEXT:    ret i32 2
 233 //
 234 //
 235 // CHECK: Function Attrs: noinline nounwind optnone
 236 // CHECK-LABEL: define {{[^@]+}}@fmv_one.default
 237 // CHECK-SAME: () #[[ATTR9]] {
 238 // CHECK-NEXT:  entry:
 239 // CHECK-NEXT:    ret i32 0
 240 //
 241 //
 242 // CHECK: Function Attrs: noinline nounwind optnone
 243 // CHECK-LABEL: define {{[^@]+}}@fmv_two._Mfp
 244 // CHECK-SAME: () #[[ATTR12:[0-9]+]] {
 245 // CHECK-NEXT:  entry:
 246 // CHECK-NEXT:    ret i32 1
 247 //
 248 //
 249 // CHECK: Function Attrs: noinline nounwind optnone
 250 // CHECK-LABEL: define {{[^@]+}}@fmv_two._Msimd
 251 // CHECK-SAME: () #[[ATTR13:[0-9]+]] {
 252 // CHECK-NEXT:  entry:
 253 // CHECK-NEXT:    ret i32 2
 254 //
 255 //
 256 // CHECK: Function Attrs: noinline nounwind optnone
 257 // CHECK-LABEL: define {{[^@]+}}@fmv_two._Mfp16Msimd
 258 // CHECK-SAME: () #[[ATTR14:[0-9]+]] {
 259 // CHECK-NEXT:  entry:
 260 // CHECK-NEXT:    ret i32 4
 261 //
 262 //
 263 // CHECK: Function Attrs: noinline nounwind optnone
 264 // CHECK-LABEL: define {{[^@]+}}@fmv_two.default
 265 // CHECK-SAME: () #[[ATTR9]] {
 266 // CHECK-NEXT:  entry:
 267 // CHECK-NEXT:    ret i32 0
 268 //
 269 //
 270 // CHECK: Function Attrs: noinline nounwind optnone
 271 // CHECK-LABEL: define {{[^@]+}}@foo
 272 // CHECK-SAME: () #[[ATTR15:[0-9]+]] {
 273 // CHECK-NEXT:  entry:
 274 // CHECK-NEXT:    [[CALL:%.*]] = call i32 @fmv()
 275 // CHECK-NEXT:    [[CALL1:%.*]] = call i32 @fmv_one()
 276 // CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]
 277 // CHECK-NEXT:    [[CALL2:%.*]] = call i32 @fmv_two()
 278 // CHECK-NEXT:    [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]]
 279 // CHECK-NEXT:    ret i32 [[ADD3]]
 280 //
 281 //
 282 // CHECK: Function Attrs: noinline nounwind optnone
 283 // CHECK-LABEL: define {{[^@]+}}@fmv_e.default
 284 // CHECK-SAME: () #[[ATTR9]] {
 285 // CHECK-NEXT:  entry:
 286 // CHECK-NEXT:    ret i32 20
 287 //
 288 //
 289 // CHECK: Function Attrs: noinline nounwind optnone
 290 // CHECK-LABEL: define {{[^@]+}}@fmv_c._Mssbs
 291 // CHECK-SAME: () #[[ATTR16:[0-9]+]] {
 292 // CHECK-NEXT:  entry:
 293 // CHECK-NEXT:    ret void
 294 //
 295 //
 296 // CHECK: Function Attrs: noinline nounwind optnone
 297 // CHECK-LABEL: define {{[^@]+}}@fmv_c.default
 298 // CHECK-SAME: () #[[ATTR9]] {
 299 // CHECK-NEXT:  entry:
 300 // CHECK-NEXT:    ret void
 301 //
 302 //
 303 // CHECK: Function Attrs: noinline nounwind optnone
 304 // CHECK-LABEL: define {{[^@]+}}@goo
 305 // CHECK-SAME: () #[[ATTR15]] {
 306 // CHECK-NEXT:  entry:
 307 // CHECK-NEXT:    [[CALL:%.*]] = call i32 @fmv_inline()
 308 // CHECK-NEXT:    [[CALL1:%.*]] = call i32 @fmv_e()
 309 // CHECK-NEXT:    [[CALL2:%.*]] = call i32 @fmv_d()
 310 // CHECK-NEXT:    call void @fmv_c()
 311 // CHECK-NEXT:    [[CALL3:%.*]] = call i32 @fmv_default()
 312 // CHECK-NEXT:    ret i32 [[CALL3]]
 313 //
 314 //
 315 // CHECK: Function Attrs: noinline nounwind optnone
 316 // CHECK-LABEL: define {{[^@]+}}@fmv_default
 317 // CHECK-SAME: () #[[ATTR9]] {
 318 // CHECK-NEXT:  entry:
 319 // CHECK-NEXT:    ret i32 111
 320 //
 321 //
 322 // CHECK: Function Attrs: noinline nounwind optnone
 323 // CHECK-LABEL: define {{[^@]+}}@recur
 324 // CHECK-SAME: () #[[ATTR15]] {
 325 // CHECK-NEXT:  entry:
 326 // CHECK-NEXT:    call void @reca()
 327 // CHECK-NEXT:    ret void
 328 //
 329 //
 330 // CHECK: Function Attrs: noinline nounwind optnone
 331 // CHECK-LABEL: define {{[^@]+}}@hoo
 332 // CHECK-SAME: () #[[ATTR15]] {
 333 // CHECK-NEXT:  entry:
 334 // CHECK-NEXT:    [[FP1:%.*]] = alloca ptr, align 8
 335 // CHECK-NEXT:    [[FP2:%.*]] = alloca ptr, align 8
 336 // CHECK-NEXT:    call void @f(ptr noundef @fmv)
 337 // CHECK-NEXT:    store ptr @fmv, ptr [[FP1]], align 8
 338 // CHECK-NEXT:    store ptr @fmv, ptr [[FP2]], align 8
 339 // CHECK-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[FP1]], align 8
 340 // CHECK-NEXT:    [[CALL:%.*]] = call i32 [[TMP0]]()
 341 // CHECK-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[FP2]], align 8
 342 // CHECK-NEXT:    [[CALL1:%.*]] = call i32 [[TMP1]]()
 343 // CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]
 344 // CHECK-NEXT:    ret i32 [[ADD]]
 345 //
 346 //
 347 // CHECK: Function Attrs: noinline nounwind optnone
 348 // CHECK-LABEL: define {{[^@]+}}@unused_with_forward_default_decl._Mmops
 349 // CHECK-SAME: () #[[ATTR19:[0-9]+]] {
 350 // CHECK-NEXT:  entry:
 351 // CHECK-NEXT:    ret i32 0
 352 //
 353 //
 354 // CHECK: Function Attrs: noinline nounwind optnone
 355 // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_extern_forward_default_decl._Mdotprod
 356 // CHECK-SAME: () #[[ATTR20:[0-9]+]] {
 357 // CHECK-NEXT:  entry:
 358 // CHECK-NEXT:    ret i32 0
 359 //
 360 //
 361 // CHECK: Function Attrs: noinline nounwind optnone
 362 // CHECK-LABEL: define {{[^@]+}}@unused_with_default_decl._Maes
 363 // CHECK-SAME: () #[[ATTR5]] {
 364 // CHECK-NEXT:  entry:
 365 // CHECK-NEXT:    ret i32 0
 366 //
 367 //
 368 // CHECK: Function Attrs: noinline nounwind optnone
 369 // CHECK-LABEL: define {{[^@]+}}@unused_with_default_def._Msve
 370 // CHECK-SAME: () #[[ATTR21:[0-9]+]] {
 371 // CHECK-NEXT:  entry:
 372 // CHECK-NEXT:    ret i32 0
 373 //
 374 //
 375 // CHECK: Function Attrs: noinline nounwind optnone
 376 // CHECK-LABEL: define {{[^@]+}}@unused_with_default_def.default
 377 // CHECK-SAME: () #[[ATTR9]] {
 378 // CHECK-NEXT:  entry:
 379 // CHECK-NEXT:    ret i32 1
 380 //
 381 //
 382 // CHECK: Function Attrs: noinline nounwind optnone
 383 // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_default_def._Mfp16
 384 // CHECK-SAME: () #[[ATTR22:[0-9]+]] {
 385 // CHECK-NEXT:  entry:
 386 // CHECK-NEXT:    ret i32 0
 387 //
 388 //
 389 // CHECK: Function Attrs: noinline nounwind optnone
 390 // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_default_def.default
 391 // CHECK-SAME: () #[[ATTR9]] {
 392 // CHECK-NEXT:  entry:
 393 // CHECK-NEXT:    ret i32 1
 394 //
 395 //
 396 // CHECK: Function Attrs: noinline nounwind optnone
 397 // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_forward_default_def.default
 398 // CHECK-SAME: () #[[ATTR15]] {
 399 // CHECK-NEXT:  entry:
 400 // CHECK-NEXT:    ret i32 0
 401 //
 402 //
 403 // CHECK: Function Attrs: noinline nounwind optnone
 404 // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_forward_default_def._Mlse
 405 // CHECK-SAME: () #[[ATTR23:[0-9]+]] {
 406 // CHECK-NEXT:  entry:
 407 // CHECK-NEXT:    ret i32 1
 408 //
 409 //
 410 // CHECK: Function Attrs: noinline nounwind optnone
 411 // CHECK-LABEL: define {{[^@]+}}@unused_without_default._Mrdm
 412 // CHECK-SAME: () #[[ATTR24:[0-9]+]] {
 413 // CHECK-NEXT:  entry:
 414 // CHECK-NEXT:    ret i32 0
 415 //
 416 //
 417 // CHECK: Function Attrs: noinline nounwind optnone
 418 // CHECK-LABEL: define {{[^@]+}}@default_def_with_version_decls.default
 419 // CHECK-SAME: () #[[ATTR15]] {
 420 // CHECK-NEXT:  entry:
 421 // CHECK-NEXT:    ret i32 0
 422 //
 423 //
 424 // CHECK: Function Attrs: noinline nounwind optnone
 425 // CHECK-LABEL: define {{[^@]+}}@used_def_without_default_decl._Mjscvt
 426 // CHECK-SAME: () #[[ATTR26:[0-9]+]] {
 427 // CHECK-NEXT:  entry:
 428 // CHECK-NEXT:    ret i32 1
 429 //
 430 //
 431 // CHECK: Function Attrs: noinline nounwind optnone
 432 // CHECK-LABEL: define {{[^@]+}}@used_def_without_default_decl._Mrdm
 433 // CHECK-SAME: () #[[ATTR24]] {
 434 // CHECK-NEXT:  entry:
 435 // CHECK-NEXT:    ret i32 2
 436 //
 437 //
 438 // CHECK: Function Attrs: noinline nounwind optnone
 439 // CHECK-LABEL: define {{[^@]+}}@caller
 440 // CHECK-SAME: () #[[ATTR15]] {
 441 // CHECK-NEXT:  entry:
 442 // CHECK-NEXT:    [[CALL:%.*]] = call i32 @used_def_without_default_decl()
 443 // CHECK-NEXT:    [[CALL1:%.*]] = call i32 @used_decl_without_default_decl()
 444 // CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]
 445 // CHECK-NEXT:    ret i32 [[ADD]]
 446 //
 447 //
 448 // CHECK: Function Attrs: noinline nounwind optnone
 449 // CHECK-LABEL: define {{[^@]+}}@main
 450 // CHECK-SAME: () #[[ATTR9]] {
 451 // CHECK-NEXT:  entry:
 452 // CHECK-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 453 // CHECK-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 454 // CHECK-NEXT:    call void @recur()
 455 // CHECK-NEXT:    [[CALL:%.*]] = call i32 @goo()
 456 // CHECK-NEXT:    ret i32 [[CALL]]
 457 //
 458 //
 459 // CHECK-LABEL: define {{[^@]+}}@fmv.resolver() comdat {
 460 // CHECK-NEXT:  resolver_entry:
 461 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 462 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 463 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 11
 464 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 11
 465 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 466 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 467 // CHECK:       resolver_return:
 468 // CHECK-NEXT:    ret ptr @fmv._MflagmMfp16fmlMrng
 469 // CHECK:       resolver_else:
 470 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 471 // CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 72057594037927940
 472 // CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 72057594037927940
 473 // CHECK-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
 474 // CHECK-NEXT:    br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 475 // CHECK:       resolver_return1:
 476 // CHECK-NEXT:    ret ptr @fmv._Mflagm2Msme-i16i64
 477 // CHECK:       resolver_else2:
 478 // CHECK-NEXT:    [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 479 // CHECK-NEXT:    [[TMP9:%.*]] = and i64 [[TMP8]], 9007199254741008
 480 // CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 9007199254741008
 481 // CHECK-NEXT:    [[TMP11:%.*]] = and i1 true, [[TMP10]]
 482 // CHECK-NEXT:    br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
 483 // CHECK:       resolver_return3:
 484 // CHECK-NEXT:    ret ptr @fmv._MdotprodMls64
 485 // CHECK:       resolver_else4:
 486 // CHECK-NEXT:    [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 487 // CHECK-NEXT:    [[TMP13:%.*]] = and i64 [[TMP12]], 9007199254742016
 488 // CHECK-NEXT:    [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 9007199254742016
 489 // CHECK-NEXT:    [[TMP15:%.*]] = and i1 true, [[TMP14]]
 490 // CHECK-NEXT:    br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]]
 491 // CHECK:       resolver_return5:
 492 // CHECK-NEXT:    ret ptr @fmv._McrcMls64
 493 // CHECK:       resolver_else6:
 494 // CHECK-NEXT:    [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 495 // CHECK-NEXT:    [[TMP17:%.*]] = and i64 [[TMP16]], 17592186044424
 496 // CHECK-NEXT:    [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 17592186044424
 497 // CHECK-NEXT:    [[TMP19:%.*]] = and i1 true, [[TMP18]]
 498 // CHECK-NEXT:    br i1 [[TMP19]], label [[RESOLVER_RETURN7:%.*]], label [[RESOLVER_ELSE8:%.*]]
 499 // CHECK:       resolver_return7:
 500 // CHECK-NEXT:    ret ptr @fmv._Mfp16fmlMmemtag
 501 // CHECK:       resolver_else8:
 502 // CHECK-NEXT:    [[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 503 // CHECK-NEXT:    [[TMP21:%.*]] = and i64 [[TMP20]], 33024
 504 // CHECK-NEXT:    [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 33024
 505 // CHECK-NEXT:    [[TMP23:%.*]] = and i1 true, [[TMP22]]
 506 // CHECK-NEXT:    br i1 [[TMP23]], label [[RESOLVER_RETURN9:%.*]], label [[RESOLVER_ELSE10:%.*]]
 507 // CHECK:       resolver_return9:
 508 // CHECK-NEXT:    ret ptr @fmv._MaesMfp
 509 // CHECK:       resolver_else10:
 510 // CHECK-NEXT:    [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 511 // CHECK-NEXT:    [[TMP25:%.*]] = and i64 [[TMP24]], 4224
 512 // CHECK-NEXT:    [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 4224
 513 // CHECK-NEXT:    [[TMP27:%.*]] = and i1 true, [[TMP26]]
 514 // CHECK-NEXT:    br i1 [[TMP27]], label [[RESOLVER_RETURN11:%.*]], label [[RESOLVER_ELSE12:%.*]]
 515 // CHECK:       resolver_return11:
 516 // CHECK-NEXT:    ret ptr @fmv._MlseMsha2
 517 // CHECK:       resolver_else12:
 518 // CHECK-NEXT:    [[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 519 // CHECK-NEXT:    [[TMP29:%.*]] = and i64 [[TMP28]], 144115188075855872
 520 // CHECK-NEXT:    [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 144115188075855872
 521 // CHECK-NEXT:    [[TMP31:%.*]] = and i1 true, [[TMP30]]
 522 // CHECK-NEXT:    br i1 [[TMP31]], label [[RESOLVER_RETURN13:%.*]], label [[RESOLVER_ELSE14:%.*]]
 523 // CHECK:       resolver_return13:
 524 // CHECK-NEXT:    ret ptr @fmv._Msme2
 525 // CHECK:       resolver_else14:
 526 // CHECK-NEXT:    [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 527 // CHECK-NEXT:    [[TMP33:%.*]] = and i64 [[TMP32]], 1125899906842624
 528 // CHECK-NEXT:    [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 1125899906842624
 529 // CHECK-NEXT:    [[TMP35:%.*]] = and i1 true, [[TMP34]]
 530 // CHECK-NEXT:    br i1 [[TMP35]], label [[RESOLVER_RETURN15:%.*]], label [[RESOLVER_ELSE16:%.*]]
 531 // CHECK:       resolver_return15:
 532 // CHECK-NEXT:    ret ptr @fmv._Mbti
 533 // CHECK:       resolver_else16:
 534 // CHECK-NEXT:    ret ptr @fmv.default
 535 //
 536 //
 537 // CHECK-LABEL: define {{[^@]+}}@fmv_one.resolver() comdat {
 538 // CHECK-NEXT:  resolver_entry:
 539 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 540 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 541 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 9007199254741504
 542 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 9007199254741504
 543 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 544 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 545 // CHECK:       resolver_return:
 546 // CHECK-NEXT:    ret ptr @fmv_one._Mls64Msimd
 547 // CHECK:       resolver_else:
 548 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 549 // CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 262144
 550 // CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 262144
 551 // CHECK-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
 552 // CHECK-NEXT:    br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 553 // CHECK:       resolver_return1:
 554 // CHECK-NEXT:    ret ptr @fmv_one._Mdpb
 555 // CHECK:       resolver_else2:
 556 // CHECK-NEXT:    ret ptr @fmv_one.default
 557 //
 558 //
 559 // CHECK-LABEL: define {{[^@]+}}@fmv_two.resolver() comdat {
 560 // CHECK-NEXT:  resolver_entry:
 561 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 562 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 563 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 66048
 564 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 66048
 565 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 566 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 567 // CHECK:       resolver_return:
 568 // CHECK-NEXT:    ret ptr @fmv_two._Mfp16Msimd
 569 // CHECK:       resolver_else:
 570 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 571 // CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 512
 572 // CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 512
 573 // CHECK-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
 574 // CHECK-NEXT:    br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 575 // CHECK:       resolver_return1:
 576 // CHECK-NEXT:    ret ptr @fmv_two._Msimd
 577 // CHECK:       resolver_else2:
 578 // CHECK-NEXT:    [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 579 // CHECK-NEXT:    [[TMP9:%.*]] = and i64 [[TMP8]], 256
 580 // CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 256
 581 // CHECK-NEXT:    [[TMP11:%.*]] = and i1 true, [[TMP10]]
 582 // CHECK-NEXT:    br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
 583 // CHECK:       resolver_return3:
 584 // CHECK-NEXT:    ret ptr @fmv_two._Mfp
 585 // CHECK:       resolver_else4:
 586 // CHECK-NEXT:    ret ptr @fmv_two.default
 587 //
 588 //
 589 // CHECK-LABEL: define {{[^@]+}}@fmv_e.resolver() comdat {
 590 // CHECK-NEXT:  resolver_entry:
 591 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 592 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 593 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 9007199254740992
 594 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 9007199254740992
 595 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 596 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 597 // CHECK:       resolver_return:
 598 // CHECK-NEXT:    ret ptr @fmv_e._Mls64
 599 // CHECK:       resolver_else:
 600 // CHECK-NEXT:    ret ptr @fmv_e.default
 601 //
 602 //
 603 // CHECK: Function Attrs: noinline nounwind optnone
 604 // CHECK-LABEL: define {{[^@]+}}@fmv_d._Msb
 605 // CHECK-SAME: () #[[ATTR28:[0-9]+]] {
 606 // CHECK-NEXT:  entry:
 607 // CHECK-NEXT:    ret i32 0
 608 //
 609 //
 610 // CHECK: Function Attrs: noinline nounwind optnone
 611 // CHECK-LABEL: define {{[^@]+}}@fmv_d.default
 612 // CHECK-SAME: () #[[ATTR9]] {
 613 // CHECK-NEXT:  entry:
 614 // CHECK-NEXT:    ret i32 1
 615 //
 616 //
 617 // CHECK-LABEL: define {{[^@]+}}@fmv_d.resolver() {
 618 // CHECK-NEXT:  resolver_entry:
 619 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 620 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 621 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 70368744177664
 622 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 70368744177664
 623 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 624 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 625 // CHECK:       resolver_return:
 626 // CHECK-NEXT:    ret ptr @fmv_d._Msb
 627 // CHECK:       resolver_else:
 628 // CHECK-NEXT:    ret ptr @fmv_d.default
 629 //
 630 //
 631 // CHECK-LABEL: define {{[^@]+}}@fmv_c.resolver() comdat {
 632 // CHECK-NEXT:  resolver_entry:
 633 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 634 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 635 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 562949953421312
 636 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 562949953421312
 637 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 638 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 639 // CHECK:       resolver_return:
 640 // CHECK-NEXT:    ret ptr @fmv_c._Mssbs
 641 // CHECK:       resolver_else:
 642 // CHECK-NEXT:    ret ptr @fmv_c.default
 643 //
 644 //
 645 // CHECK: Function Attrs: noinline nounwind optnone
 646 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MaesMf64mmMsha2
 647 // CHECK-SAME: () #[[ATTR29:[0-9]+]] {
 648 // CHECK-NEXT:  entry:
 649 // CHECK-NEXT:    ret i32 1
 650 //
 651 //
 652 // CHECK: Function Attrs: noinline nounwind optnone
 653 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfcmaMfp16MrdmMsme
 654 // CHECK-SAME: () #[[ATTR30:[0-9]+]] {
 655 // CHECK-NEXT:  entry:
 656 // CHECK-NEXT:    ret i32 2
 657 //
 658 //
 659 // CHECK: Function Attrs: noinline nounwind optnone
 660 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mf32mmMi8mmMsha3
 661 // CHECK-SAME: () #[[ATTR31:[0-9]+]] {
 662 // CHECK-NEXT:  entry:
 663 // CHECK-NEXT:    ret i32 12
 664 //
 665 //
 666 // CHECK: Function Attrs: noinline nounwind optnone
 667 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mbf16Mdit
 668 // CHECK-SAME: () #[[ATTR32:[0-9]+]] {
 669 // CHECK-NEXT:  entry:
 670 // CHECK-NEXT:    ret i32 8
 671 //
 672 //
 673 // CHECK: Function Attrs: noinline nounwind optnone
 674 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MdpbMrcpc2
 675 // CHECK-SAME: () #[[ATTR33:[0-9]+]] {
 676 // CHECK-NEXT:  entry:
 677 // CHECK-NEXT:    ret i32 6
 678 //
 679 //
 680 // CHECK: Function Attrs: noinline nounwind optnone
 681 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mdpb2Mjscvt
 682 // CHECK-SAME: () #[[ATTR34:[0-9]+]] {
 683 // CHECK-NEXT:  entry:
 684 // CHECK-NEXT:    ret i32 7
 685 //
 686 //
 687 // CHECK: Function Attrs: noinline nounwind optnone
 688 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfrinttsMrcpc
 689 // CHECK-SAME: () #[[ATTR35:[0-9]+]] {
 690 // CHECK-NEXT:  entry:
 691 // CHECK-NEXT:    ret i32 3
 692 //
 693 //
 694 // CHECK: Function Attrs: noinline nounwind optnone
 695 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mbf16Msve
 696 // CHECK-SAME: () #[[ATTR36:[0-9]+]] {
 697 // CHECK-NEXT:  entry:
 698 // CHECK-NEXT:    ret i32 4
 699 //
 700 //
 701 // CHECK: Function Attrs: noinline nounwind optnone
 702 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msve2-aesMsve2-sha3
 703 // CHECK-SAME: () #[[ATTR37:[0-9]+]] {
 704 // CHECK-NEXT:  entry:
 705 // CHECK-NEXT:    ret i32 5
 706 //
 707 //
 708 // CHECK: Function Attrs: noinline nounwind optnone
 709 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msve2Msve2-aesMsve2-bitperm
 710 // CHECK-SAME: () #[[ATTR38:[0-9]+]] {
 711 // CHECK-NEXT:  entry:
 712 // CHECK-NEXT:    ret i32 9
 713 //
 714 //
 715 // CHECK: Function Attrs: noinline nounwind optnone
 716 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MmemtagMsve2-sm4
 717 // CHECK-SAME: () #[[ATTR39:[0-9]+]] {
 718 // CHECK-NEXT:  entry:
 719 // CHECK-NEXT:    ret i32 10
 720 //
 721 //
 722 // CHECK: Function Attrs: noinline nounwind optnone
 723 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MmemtagMmopsMrcpc3
 724 // CHECK-SAME: () #[[ATTR40:[0-9]+]] {
 725 // CHECK-NEXT:  entry:
 726 // CHECK-NEXT:    ret i32 11
 727 //
 728 //
 729 // CHECK: Function Attrs: noinline nounwind optnone
 730 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MaesMdotprod
 731 // CHECK-SAME: () #[[ATTR41:[0-9]+]] {
 732 // CHECK-NEXT:  entry:
 733 // CHECK-NEXT:    ret i32 13
 734 //
 735 //
 736 // CHECK: Function Attrs: noinline nounwind optnone
 737 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mfp16fmlMsimd
 738 // CHECK-SAME: () #[[ATTR42:[0-9]+]] {
 739 // CHECK-NEXT:  entry:
 740 // CHECK-NEXT:    ret i32 14
 741 //
 742 //
 743 // CHECK: Function Attrs: noinline nounwind optnone
 744 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfpMsm4
 745 // CHECK-SAME: () #[[ATTR43:[0-9]+]] {
 746 // CHECK-NEXT:  entry:
 747 // CHECK-NEXT:    ret i32 15
 748 //
 749 //
 750 // CHECK: Function Attrs: noinline nounwind optnone
 751 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MlseMrdm
 752 // CHECK-SAME: () #[[ATTR44:[0-9]+]] {
 753 // CHECK-NEXT:  entry:
 754 // CHECK-NEXT:    ret i32 16
 755 //
 756 //
 757 // CHECK: Function Attrs: noinline nounwind optnone
 758 // CHECK-LABEL: define {{[^@]+}}@fmv_inline.default
 759 // CHECK-SAME: () #[[ATTR9]] {
 760 // CHECK-NEXT:  entry:
 761 // CHECK-NEXT:    ret i32 3
 762 //
 763 //
 764 // CHECK-LABEL: define {{[^@]+}}@fmv_inline.resolver() comdat {
 765 // CHECK-NEXT:  resolver_entry:
 766 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 767 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 768 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 4398048673856
 769 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4398048673856
 770 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 771 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 772 // CHECK:       resolver_return:
 773 // CHECK-NEXT:    ret ptr @fmv_inline._MfcmaMfp16MrdmMsme
 774 // CHECK:       resolver_else:
 775 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 776 // CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 864708720641179648
 777 // CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 864708720641179648
 778 // CHECK-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
 779 // CHECK-NEXT:    br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 780 // CHECK:       resolver_return1:
 781 // CHECK-NEXT:    ret ptr @fmv_inline._MmemtagMmopsMrcpc3
 782 // CHECK:       resolver_else2:
 783 // CHECK-NEXT:    [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 784 // CHECK-NEXT:    [[TMP9:%.*]] = and i64 [[TMP8]], 893353197568
 785 // CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 893353197568
 786 // CHECK-NEXT:    [[TMP11:%.*]] = and i1 true, [[TMP10]]
 787 // CHECK-NEXT:    br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
 788 // CHECK:       resolver_return3:
 789 // CHECK-NEXT:    ret ptr @fmv_inline._Msve2Msve2-aesMsve2-bitperm
 790 // CHECK:       resolver_else4:
 791 // CHECK-NEXT:    [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 792 // CHECK-NEXT:    [[TMP13:%.*]] = and i64 [[TMP12]], 34359775232
 793 // CHECK-NEXT:    [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 34359775232
 794 // CHECK-NEXT:    [[TMP15:%.*]] = and i1 true, [[TMP14]]
 795 // CHECK-NEXT:    br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]]
 796 // CHECK:       resolver_return5:
 797 // CHECK-NEXT:    ret ptr @fmv_inline._MaesMf64mmMsha2
 798 // CHECK:       resolver_else6:
 799 // CHECK-NEXT:    [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 800 // CHECK-NEXT:    [[TMP17:%.*]] = and i64 [[TMP16]], 17246986240
 801 // CHECK-NEXT:    [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 17246986240
 802 // CHECK-NEXT:    [[TMP19:%.*]] = and i1 true, [[TMP18]]
 803 // CHECK-NEXT:    br i1 [[TMP19]], label [[RESOLVER_RETURN7:%.*]], label [[RESOLVER_ELSE8:%.*]]
 804 // CHECK:       resolver_return7:
 805 // CHECK-NEXT:    ret ptr @fmv_inline._Mf32mmMi8mmMsha3
 806 // CHECK:       resolver_else8:
 807 // CHECK-NEXT:    [[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 808 // CHECK-NEXT:    [[TMP21:%.*]] = and i64 [[TMP20]], 19791209299968
 809 // CHECK-NEXT:    [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 19791209299968
 810 // CHECK-NEXT:    [[TMP23:%.*]] = and i1 true, [[TMP22]]
 811 // CHECK-NEXT:    br i1 [[TMP23]], label [[RESOLVER_RETURN9:%.*]], label [[RESOLVER_ELSE10:%.*]]
 812 // CHECK:       resolver_return9:
 813 // CHECK-NEXT:    ret ptr @fmv_inline._MmemtagMsve2-sm4
 814 // CHECK:       resolver_else10:
 815 // CHECK-NEXT:    [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 816 // CHECK-NEXT:    [[TMP25:%.*]] = and i64 [[TMP24]], 1374389534720
 817 // CHECK-NEXT:    [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 1374389534720
 818 // CHECK-NEXT:    [[TMP27:%.*]] = and i1 true, [[TMP26]]
 819 // CHECK-NEXT:    br i1 [[TMP27]], label [[RESOLVER_RETURN11:%.*]], label [[RESOLVER_ELSE12:%.*]]
 820 // CHECK:       resolver_return11:
 821 // CHECK-NEXT:    ret ptr @fmv_inline._Msve2-aesMsve2-sha3
 822 // CHECK:       resolver_else12:
 823 // CHECK-NEXT:    [[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 824 // CHECK-NEXT:    [[TMP29:%.*]] = and i64 [[TMP28]], 1207959552
 825 // CHECK-NEXT:    [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 1207959552
 826 // CHECK-NEXT:    [[TMP31:%.*]] = and i1 true, [[TMP30]]
 827 // CHECK-NEXT:    br i1 [[TMP31]], label [[RESOLVER_RETURN13:%.*]], label [[RESOLVER_ELSE14:%.*]]
 828 // CHECK:       resolver_return13:
 829 // CHECK-NEXT:    ret ptr @fmv_inline._Mbf16Msve
 830 // CHECK:       resolver_else14:
 831 // CHECK-NEXT:    [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 832 // CHECK-NEXT:    [[TMP33:%.*]] = and i64 [[TMP32]], 134348800
 833 // CHECK-NEXT:    [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 134348800
 834 // CHECK-NEXT:    [[TMP35:%.*]] = and i1 true, [[TMP34]]
 835 // CHECK-NEXT:    br i1 [[TMP35]], label [[RESOLVER_RETURN15:%.*]], label [[RESOLVER_ELSE16:%.*]]
 836 // CHECK:       resolver_return15:
 837 // CHECK-NEXT:    ret ptr @fmv_inline._Mbf16Mdit
 838 // CHECK:       resolver_else16:
 839 // CHECK-NEXT:    [[TMP36:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 840 // CHECK-NEXT:    [[TMP37:%.*]] = and i64 [[TMP36]], 20971520
 841 // CHECK-NEXT:    [[TMP38:%.*]] = icmp eq i64 [[TMP37]], 20971520
 842 // CHECK-NEXT:    [[TMP39:%.*]] = and i1 true, [[TMP38]]
 843 // CHECK-NEXT:    br i1 [[TMP39]], label [[RESOLVER_RETURN17:%.*]], label [[RESOLVER_ELSE18:%.*]]
 844 // CHECK:       resolver_return17:
 845 // CHECK-NEXT:    ret ptr @fmv_inline._MfrinttsMrcpc
 846 // CHECK:       resolver_else18:
 847 // CHECK-NEXT:    [[TMP40:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 848 // CHECK-NEXT:    [[TMP41:%.*]] = and i64 [[TMP40]], 8650752
 849 // CHECK-NEXT:    [[TMP42:%.*]] = icmp eq i64 [[TMP41]], 8650752
 850 // CHECK-NEXT:    [[TMP43:%.*]] = and i1 true, [[TMP42]]
 851 // CHECK-NEXT:    br i1 [[TMP43]], label [[RESOLVER_RETURN19:%.*]], label [[RESOLVER_ELSE20:%.*]]
 852 // CHECK:       resolver_return19:
 853 // CHECK-NEXT:    ret ptr @fmv_inline._MdpbMrcpc2
 854 // CHECK:       resolver_else20:
 855 // CHECK-NEXT:    [[TMP44:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 856 // CHECK-NEXT:    [[TMP45:%.*]] = and i64 [[TMP44]], 1572864
 857 // CHECK-NEXT:    [[TMP46:%.*]] = icmp eq i64 [[TMP45]], 1572864
 858 // CHECK-NEXT:    [[TMP47:%.*]] = and i1 true, [[TMP46]]
 859 // CHECK-NEXT:    br i1 [[TMP47]], label [[RESOLVER_RETURN21:%.*]], label [[RESOLVER_ELSE22:%.*]]
 860 // CHECK:       resolver_return21:
 861 // CHECK-NEXT:    ret ptr @fmv_inline._Mdpb2Mjscvt
 862 // CHECK:       resolver_else22:
 863 // CHECK-NEXT:    [[TMP48:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 864 // CHECK-NEXT:    [[TMP49:%.*]] = and i64 [[TMP48]], 520
 865 // CHECK-NEXT:    [[TMP50:%.*]] = icmp eq i64 [[TMP49]], 520
 866 // CHECK-NEXT:    [[TMP51:%.*]] = and i1 true, [[TMP50]]
 867 // CHECK-NEXT:    br i1 [[TMP51]], label [[RESOLVER_RETURN23:%.*]], label [[RESOLVER_ELSE24:%.*]]
 868 // CHECK:       resolver_return23:
 869 // CHECK-NEXT:    ret ptr @fmv_inline._Mfp16fmlMsimd
 870 // CHECK:       resolver_else24:
 871 // CHECK-NEXT:    [[TMP52:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 872 // CHECK-NEXT:    [[TMP53:%.*]] = and i64 [[TMP52]], 32784
 873 // CHECK-NEXT:    [[TMP54:%.*]] = icmp eq i64 [[TMP53]], 32784
 874 // CHECK-NEXT:    [[TMP55:%.*]] = and i1 true, [[TMP54]]
 875 // CHECK-NEXT:    br i1 [[TMP55]], label [[RESOLVER_RETURN25:%.*]], label [[RESOLVER_ELSE26:%.*]]
 876 // CHECK:       resolver_return25:
 877 // CHECK-NEXT:    ret ptr @fmv_inline._MaesMdotprod
 878 // CHECK:       resolver_else26:
 879 // CHECK-NEXT:    [[TMP56:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 880 // CHECK-NEXT:    [[TMP57:%.*]] = and i64 [[TMP56]], 192
 881 // CHECK-NEXT:    [[TMP58:%.*]] = icmp eq i64 [[TMP57]], 192
 882 // CHECK-NEXT:    [[TMP59:%.*]] = and i1 true, [[TMP58]]
 883 // CHECK-NEXT:    br i1 [[TMP59]], label [[RESOLVER_RETURN27:%.*]], label [[RESOLVER_ELSE28:%.*]]
 884 // CHECK:       resolver_return27:
 885 // CHECK-NEXT:    ret ptr @fmv_inline._MlseMrdm
 886 // CHECK:       resolver_else28:
 887 // CHECK-NEXT:    [[TMP60:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 888 // CHECK-NEXT:    [[TMP61:%.*]] = and i64 [[TMP60]], 288
 889 // CHECK-NEXT:    [[TMP62:%.*]] = icmp eq i64 [[TMP61]], 288
 890 // CHECK-NEXT:    [[TMP63:%.*]] = and i1 true, [[TMP62]]
 891 // CHECK-NEXT:    br i1 [[TMP63]], label [[RESOLVER_RETURN29:%.*]], label [[RESOLVER_ELSE30:%.*]]
 892 // CHECK:       resolver_return29:
 893 // CHECK-NEXT:    ret ptr @fmv_inline._MfpMsm4
 894 // CHECK:       resolver_else30:
 895 // CHECK-NEXT:    ret ptr @fmv_inline.default
 896 //
 897 //
 898 // CHECK-LABEL: define {{[^@]+}}@unused_with_default_def.resolver() comdat {
 899 // CHECK-NEXT:  resolver_entry:
 900 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 901 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 902 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 1073741824
 903 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1073741824
 904 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 905 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 906 // CHECK:       resolver_return:
 907 // CHECK-NEXT:    ret ptr @unused_with_default_def._Msve
 908 // CHECK:       resolver_else:
 909 // CHECK-NEXT:    ret ptr @unused_with_default_def.default
 910 //
 911 //
 912 // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_default_def.resolver() comdat {
 913 // CHECK-NEXT:  resolver_entry:
 914 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 915 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 916 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 65536
 917 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 65536
 918 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 919 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 920 // CHECK:       resolver_return:
 921 // CHECK-NEXT:    ret ptr @unused_with_implicit_default_def._Mfp16
 922 // CHECK:       resolver_else:
 923 // CHECK-NEXT:    ret ptr @unused_with_implicit_default_def.default
 924 //
 925 //
 926 // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_forward_default_def.resolver() comdat {
 927 // CHECK-NEXT:  resolver_entry:
 928 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 929 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 930 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 128
 931 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 128
 932 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 933 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 934 // CHECK:       resolver_return:
 935 // CHECK-NEXT:    ret ptr @unused_with_implicit_forward_default_def._Mlse
 936 // CHECK:       resolver_else:
 937 // CHECK-NEXT:    ret ptr @unused_with_implicit_forward_default_def.default
 938 //
 939 //
 940 // CHECK-LABEL: define {{[^@]+}}@default_def_with_version_decls.resolver() comdat {
 941 // CHECK-NEXT:  resolver_entry:
 942 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 943 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 944 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 1048576
 945 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1048576
 946 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 947 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 948 // CHECK:       resolver_return:
 949 // CHECK-NEXT:    ret ptr @default_def_with_version_decls._Mjscvt
 950 // CHECK:       resolver_else:
 951 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 952 // CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 64
 953 // CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 64
 954 // CHECK-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
 955 // CHECK-NEXT:    br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 956 // CHECK:       resolver_return1:
 957 // CHECK-NEXT:    ret ptr @default_def_with_version_decls._Mrdm
 958 // CHECK:       resolver_else2:
 959 // CHECK-NEXT:    ret ptr @default_def_with_version_decls.default
 960 //
 961 //
 962 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
 963 // CHECK-NOFMV-LABEL: define {{[^@]+}}@foo
 964 // CHECK-NOFMV-SAME: () #[[ATTR0:[0-9]+]] {
 965 // CHECK-NOFMV-NEXT:  entry:
 966 // CHECK-NOFMV-NEXT:    [[CALL:%.*]] = call i32 @fmv()
 967 // CHECK-NOFMV-NEXT:    [[CALL1:%.*]] = call i32 @fmv_one()
 968 // CHECK-NOFMV-NEXT:    [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]
 969 // CHECK-NOFMV-NEXT:    [[CALL2:%.*]] = call i32 @fmv_two()
 970 // CHECK-NOFMV-NEXT:    [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]]
 971 // CHECK-NOFMV-NEXT:    ret i32 [[ADD3]]
 972 //
 973 //
 974 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
 975 // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv
 976 // CHECK-NOFMV-SAME: () #[[ATTR1:[0-9]+]] {
 977 // CHECK-NOFMV-NEXT:  entry:
 978 // CHECK-NOFMV-NEXT:    ret i32 0
 979 //
 980 //
 981 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
 982 // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_one
 983 // CHECK-NOFMV-SAME: () #[[ATTR1]] {
 984 // CHECK-NOFMV-NEXT:  entry:
 985 // CHECK-NOFMV-NEXT:    ret i32 0
 986 //
 987 //
 988 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
 989 // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_two
 990 // CHECK-NOFMV-SAME: () #[[ATTR1]] {
 991 // CHECK-NOFMV-NEXT:  entry:
 992 // CHECK-NOFMV-NEXT:    ret i32 0
 993 //
 994 //
 995 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
 996 // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_e
 997 // CHECK-NOFMV-SAME: () #[[ATTR0]] {
 998 // CHECK-NOFMV-NEXT:  entry:
 999 // CHECK-NOFMV-NEXT:    ret i32 20
1000 //
1001 //
1002 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
1003 // CHECK-NOFMV-LABEL: define {{[^@]+}}@goo
1004 // CHECK-NOFMV-SAME: () #[[ATTR0]] {
1005 // CHECK-NOFMV-NEXT:  entry:
1006 // CHECK-NOFMV-NEXT:    [[CALL:%.*]] = call i32 @fmv_inline()
1007 // CHECK-NOFMV-NEXT:    [[CALL1:%.*]] = call i32 @fmv_e()
1008 // CHECK-NOFMV-NEXT:    [[CALL2:%.*]] = call i32 @fmv_d()
1009 // CHECK-NOFMV-NEXT:    call void @fmv_c()
1010 // CHECK-NOFMV-NEXT:    [[CALL3:%.*]] = call i32 @fmv_default()
1011 // CHECK-NOFMV-NEXT:    ret i32 [[CALL3]]
1012 //
1013 //
1014 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
1015 // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_d
1016 // CHECK-NOFMV-SAME: () #[[ATTR1]] {
1017 // CHECK-NOFMV-NEXT:  entry:
1018 // CHECK-NOFMV-NEXT:    ret i32 1
1019 //
1020 //
1021 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
1022 // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_c
1023 // CHECK-NOFMV-SAME: () #[[ATTR1]] {
1024 // CHECK-NOFMV-NEXT:  entry:
1025 // CHECK-NOFMV-NEXT:    ret void
1026 //
1027 //
1028 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
1029 // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_default
1030 // CHECK-NOFMV-SAME: () #[[ATTR1]] {
1031 // CHECK-NOFMV-NEXT:  entry:
1032 // CHECK-NOFMV-NEXT:    ret i32 111
1033 //
1034 //
1035 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
1036 // CHECK-NOFMV-LABEL: define {{[^@]+}}@recur
1037 // CHECK-NOFMV-SAME: () #[[ATTR0]] {
1038 // CHECK-NOFMV-NEXT:  entry:
1039 // CHECK-NOFMV-NEXT:    call void @reca()
1040 // CHECK-NOFMV-NEXT:    ret void
1041 //
1042 //
1043 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
1044 // CHECK-NOFMV-LABEL: define {{[^@]+}}@hoo
1045 // CHECK-NOFMV-SAME: () #[[ATTR0]] {
1046 // CHECK-NOFMV-NEXT:  entry:
1047 // CHECK-NOFMV-NEXT:    [[FP1:%.*]] = alloca ptr, align 8
1048 // CHECK-NOFMV-NEXT:    [[FP2:%.*]] = alloca ptr, align 8
1049 // CHECK-NOFMV-NEXT:    call void @f(ptr noundef @fmv)
1050 // CHECK-NOFMV-NEXT:    store ptr @fmv, ptr [[FP1]], align 8
1051 // CHECK-NOFMV-NEXT:    store ptr @fmv, ptr [[FP2]], align 8
1052 // CHECK-NOFMV-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[FP1]], align 8
1053 // CHECK-NOFMV-NEXT:    [[CALL:%.*]] = call i32 [[TMP0]]()
1054 // CHECK-NOFMV-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[FP2]], align 8
1055 // CHECK-NOFMV-NEXT:    [[CALL1:%.*]] = call i32 [[TMP1]]()
1056 // CHECK-NOFMV-NEXT:    [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]
1057 // CHECK-NOFMV-NEXT:    ret i32 [[ADD]]
1058 //
1059 //
1060 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
1061 // CHECK-NOFMV-LABEL: define {{[^@]+}}@unused_with_implicit_default_def
1062 // CHECK-NOFMV-SAME: () #[[ATTR0]] {
1063 // CHECK-NOFMV-NEXT:  entry:
1064 // CHECK-NOFMV-NEXT:    ret i32 1
1065 //
1066 //
1067 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
1068 // CHECK-NOFMV-LABEL: define {{[^@]+}}@unused_with_implicit_forward_default_def
1069 // CHECK-NOFMV-SAME: () #[[ATTR0]] {
1070 // CHECK-NOFMV-NEXT:  entry:
1071 // CHECK-NOFMV-NEXT:    ret i32 0
1072 //
1073 //
1074 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
1075 // CHECK-NOFMV-LABEL: define {{[^@]+}}@default_def_with_version_decls
1076 // CHECK-NOFMV-SAME: () #[[ATTR0]] {
1077 // CHECK-NOFMV-NEXT:  entry:
1078 // CHECK-NOFMV-NEXT:    ret i32 0
1079 //
1080 //
1081 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
1082 // CHECK-NOFMV-LABEL: define {{[^@]+}}@main
1083 // CHECK-NOFMV-SAME: () #[[ATTR1]] {
1084 // CHECK-NOFMV-NEXT:  entry:
1085 // CHECK-NOFMV-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1086 // CHECK-NOFMV-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1087 // CHECK-NOFMV-NEXT:    call void @recur()
1088 // CHECK-NOFMV-NEXT:    [[CALL:%.*]] = call i32 @goo()
1089 // CHECK-NOFMV-NEXT:    ret i32 [[CALL]]
1090 //
1091 //
1092 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
1093 // CHECK-NOFMV-LABEL: define {{[^@]+}}@unused_with_default_def
1094 // CHECK-NOFMV-SAME: () #[[ATTR1]] {
1095 // CHECK-NOFMV-NEXT:  entry:
1096 // CHECK-NOFMV-NEXT:    ret i32 1
1097 //
1098 //.
1099 // CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
1100 // CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
1101 //.
1102 // CHECK-NOFMV: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
1103 // CHECK-NOFMV: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
1104 //.