Fix test failures introduced by PR #113697 (#116941)
[llvm-project.git] / llvm / unittests / TargetParser / Host.cpp
blob5e2edcef09bf8cf60c3e7a9d532a3c0adc446d4b
1 //========- unittests/Support/Host.cpp - Host.cpp tests --------------========//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
9 #include "llvm/TargetParser/Host.h"
10 #include "llvm/ADT/SmallVector.h"
11 #include "llvm/Config/config.h"
12 #include "llvm/Support/FileSystem.h"
13 #include "llvm/Support/Path.h"
14 #include "llvm/Support/Program.h"
15 #include "llvm/Support/Threading.h"
16 #include "llvm/TargetParser/Triple.h"
18 #include "gtest/gtest.h"
20 #define ASSERT_NO_ERROR(x) \
21 if (std::error_code ASSERT_NO_ERROR_ec = x) { \
22 SmallString<128> MessageStorage; \
23 raw_svector_ostream Message(MessageStorage); \
24 Message << #x ": did not return errc::success.\n" \
25 << "error number: " << ASSERT_NO_ERROR_ec.value() << "\n" \
26 << "error message: " << ASSERT_NO_ERROR_ec.message() << "\n"; \
27 GTEST_FATAL_FAILURE_(MessageStorage.c_str()); \
28 } else { \
31 using namespace llvm;
33 TEST(getLinuxHostCPUName, ARM) {
34 StringRef CortexA9ProcCpuinfo = R"(
35 processor : 0
36 model name : ARMv7 Processor rev 10 (v7l)
37 BogoMIPS : 1393.66
38 Features : half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpd32
39 CPU implementer : 0x41
40 CPU architecture: 7
41 CPU variant : 0x2
42 CPU part : 0xc09
43 CPU revision : 10
45 processor : 1
46 model name : ARMv7 Processor rev 10 (v7l)
47 BogoMIPS : 1393.66
48 Features : half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpd32
49 CPU implementer : 0x41
50 CPU architecture: 7
51 CPU variant : 0x2
52 CPU part : 0xc09
53 CPU revision : 10
55 Hardware : Generic OMAP4 (Flattened Device Tree)
56 Revision : 0000
57 Serial : 0000000000000000
58 )";
60 EXPECT_EQ(sys::detail::getHostCPUNameForARM(CortexA9ProcCpuinfo),
61 "cortex-a9");
62 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
63 "CPU part : 0xc0f"),
64 "cortex-a15");
65 // Verify that both CPU implementer and CPU part are checked:
66 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x40\n"
67 "CPU part : 0xc0f"),
68 "generic");
69 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n"
70 "CPU part : 0x06f"),
71 "krait");
74 TEST(getLinuxHostCPUName, AArch64) {
75 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
76 "CPU part : 0xd03"),
77 "cortex-a53");
78 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
79 "CPU part : 0xd05"),
80 "cortex-a55");
82 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
83 "CPU part : 0xd40"),
84 "neoverse-v1");
85 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
86 "CPU part : 0xd4f"),
87 "neoverse-v2");
88 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
89 "CPU part : 0xd84"),
90 "neoverse-v3");
91 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
92 "CPU part : 0xd0c"),
93 "neoverse-n1");
94 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
95 "CPU part : 0xd49"),
96 "neoverse-n2");
97 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
98 "CPU part : 0xd8e"),
99 "neoverse-n3");
100 // Verify that both CPU implementer and CPU part are checked:
101 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x40\n"
102 "CPU part : 0xd03"),
103 "generic");
104 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n"
105 "CPU part : 0x201"),
106 "kryo");
107 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n"
108 "CPU part : 0x800"),
109 "cortex-a73");
110 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n"
111 "CPU part : 0x801"),
112 "cortex-a73");
113 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
114 "CPU part : 0xd46"),
115 "cortex-a510");
116 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
117 "CPU part : 0xd47"),
118 "cortex-a710");
119 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
120 "CPU part : 0xd48"),
121 "cortex-x2");
122 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n"
123 "CPU part : 0xc00"),
124 "falkor");
125 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n"
126 "CPU part : 0xc01"),
127 "saphira");
128 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x6d\n"
129 "CPU part : 0xd49"),
130 "neoverse-n2");
131 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0xc0\n"
132 "CPU part : 0xac3"),
133 "ampere1");
134 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0xc0\n"
135 "CPU part : 0xac4"),
136 "ampere1a");
137 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0xc0\n"
138 "CPU part : 0xac5"),
139 "ampere1b");
140 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n"
141 "CPU part : 0x001"),
142 "oryon-1");
144 // MSM8992/4 weirdness
145 StringRef MSM8992ProcCpuInfo = R"(
146 Processor : AArch64 Processor rev 3 (aarch64)
147 processor : 0
148 processor : 1
149 processor : 2
150 processor : 3
151 processor : 4
152 processor : 5
153 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32
154 CPU implementer : 0x41
155 CPU architecture: 8
156 CPU variant : 0x0
157 CPU part : 0xd03
158 CPU revision : 3
160 Hardware : Qualcomm Technologies, Inc MSM8992
163 EXPECT_EQ(sys::detail::getHostCPUNameForARM(MSM8992ProcCpuInfo),
164 "cortex-a53");
166 // Exynos big.LITTLE weirdness
167 const std::string ExynosProcCpuInfo = R"(
168 processor : 0
169 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32
170 CPU implementer : 0x41
171 CPU architecture: 8
172 CPU variant : 0x0
173 CPU part : 0xd05
175 processor : 1
176 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32
177 CPU implementer : 0x53
178 CPU architecture: 8
181 // Verify default for Exynos.
182 EXPECT_EQ(sys::detail::getHostCPUNameForARM(ExynosProcCpuInfo +
183 "CPU variant : 0xc\n"
184 "CPU part : 0xafe"),
185 "exynos-m3");
186 // Verify Exynos M3.
187 EXPECT_EQ(sys::detail::getHostCPUNameForARM(ExynosProcCpuInfo +
188 "CPU variant : 0x1\n"
189 "CPU part : 0x002"),
190 "exynos-m3");
191 // Verify Exynos M4.
192 EXPECT_EQ(sys::detail::getHostCPUNameForARM(ExynosProcCpuInfo +
193 "CPU variant : 0x1\n"
194 "CPU part : 0x003"),
195 "exynos-m4");
197 const std::string ThunderX2T99ProcCpuInfo = R"(
198 processor : 0
199 BogoMIPS : 400.00
200 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
201 CPU implementer : 0x43
202 CPU architecture: 8
203 CPU variant : 0x1
204 CPU part : 0x0af
207 // Verify different versions of ThunderX2T99.
208 EXPECT_EQ(sys::detail::getHostCPUNameForARM(ThunderX2T99ProcCpuInfo +
209 "CPU implementer : 0x42\n"
210 "CPU part : 0x516"),
211 "thunderx2t99");
213 EXPECT_EQ(sys::detail::getHostCPUNameForARM(ThunderX2T99ProcCpuInfo +
214 "CPU implementer : 0x42\n"
215 "CPU part : 0x0516"),
216 "thunderx2t99");
218 EXPECT_EQ(sys::detail::getHostCPUNameForARM(ThunderX2T99ProcCpuInfo +
219 "CPU implementer : 0x43\n"
220 "CPU part : 0x516"),
221 "thunderx2t99");
223 EXPECT_EQ(sys::detail::getHostCPUNameForARM(ThunderX2T99ProcCpuInfo +
224 "CPU implementer : 0x43\n"
225 "CPU part : 0x0516"),
226 "thunderx2t99");
228 EXPECT_EQ(sys::detail::getHostCPUNameForARM(ThunderX2T99ProcCpuInfo +
229 "CPU implementer : 0x42\n"
230 "CPU part : 0xaf"),
231 "thunderx2t99");
233 EXPECT_EQ(sys::detail::getHostCPUNameForARM(ThunderX2T99ProcCpuInfo +
234 "CPU implementer : 0x42\n"
235 "CPU part : 0x0af"),
236 "thunderx2t99");
238 EXPECT_EQ(sys::detail::getHostCPUNameForARM(ThunderX2T99ProcCpuInfo +
239 "CPU implementer : 0x43\n"
240 "CPU part : 0xaf"),
241 "thunderx2t99");
243 EXPECT_EQ(sys::detail::getHostCPUNameForARM(ThunderX2T99ProcCpuInfo +
244 "CPU implementer : 0x43\n"
245 "CPU part : 0x0af"),
246 "thunderx2t99");
248 // Verify ThunderXT88.
249 const std::string ThunderXT88ProcCpuInfo = R"(
250 processor : 0
251 BogoMIPS : 200.00
252 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32
253 CPU implementer : 0x43
254 CPU architecture: 8
255 CPU variant : 0x1
256 CPU part : 0x0a1
259 EXPECT_EQ(sys::detail::getHostCPUNameForARM(ThunderXT88ProcCpuInfo +
260 "CPU implementer : 0x43\n"
261 "CPU part : 0x0a1"),
262 "thunderxt88");
264 EXPECT_EQ(sys::detail::getHostCPUNameForARM(ThunderXT88ProcCpuInfo +
265 "CPU implementer : 0x43\n"
266 "CPU part : 0xa1"),
267 "thunderxt88");
269 // Verify HiSilicon processors.
270 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x48\n"
271 "CPU part : 0xd01"),
272 "tsv110");
274 // Verify A64FX.
275 const std::string A64FXProcCpuInfo = R"(
276 processor : 0
277 BogoMIPS : 200.00
278 Features : fp asimd evtstrm sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm fcma dcpop sve
279 CPU implementer : 0x46
280 CPU architecture: 8
281 CPU variant : 0x1
282 CPU part : 0x001
285 EXPECT_EQ(sys::detail::getHostCPUNameForARM(A64FXProcCpuInfo), "a64fx");
287 // Verify Nvidia Carmel.
288 const std::string CarmelProcCpuInfo = R"(
289 processor : 0
290 model name : ARMv8 Processor rev 0 (v8l)
291 BogoMIPS : 62.50
292 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm dcpop
293 CPU implementer : 0x4e
294 CPU architecture: 8
295 CPU variant : 0x0
296 CPU part : 0x004
297 CPU revision : 0
300 EXPECT_EQ(sys::detail::getHostCPUNameForARM(CarmelProcCpuInfo), "carmel");
302 // Snapdragon mixed implementer quirk
303 const std::string Snapdragon865ProcCPUInfo = R"(
304 processor : 0
305 BogoMIPS : 38.40
306 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
307 CPU implementer : 0x51
308 CPU architecture: 8
309 CPU variant : 0xd
310 CPU part : 0x805
311 CPU revision : 14
312 processor : 1
313 processor : 2
314 processor : 3
315 processor : 4
316 processor : 5
317 processor : 6
318 BogoMIPS : 38.40
319 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
320 CPU implementer : 0x41
321 CPU architecture: 8
322 CPU variant : 0x1
323 CPU part : 0xd0d
324 CPU revision : 0
326 EXPECT_EQ(sys::detail::getHostCPUNameForARM(Snapdragon865ProcCPUInfo), "cortex-a77");
329 TEST(getLinuxHostCPUName, s390x) {
330 SmallVector<std::string> ModelIDs(
331 {"3931", "8561", "3906", "2964", "2827", "2817", "2097", "2064"});
332 SmallVector<std::string> VectorSupport({"", "vx"});
333 SmallVector<StringRef> ExpectedCPUs;
335 // Model Id: 3931
336 ExpectedCPUs.push_back("zEC12");
337 ExpectedCPUs.push_back("z16");
339 // Model Id: 8561
340 ExpectedCPUs.push_back("zEC12");
341 ExpectedCPUs.push_back("z15");
343 // Model Id: 3906
344 ExpectedCPUs.push_back("zEC12");
345 ExpectedCPUs.push_back("z14");
347 // Model Id: 2964
348 ExpectedCPUs.push_back("zEC12");
349 ExpectedCPUs.push_back("z13");
351 // Model Id: 2827
352 ExpectedCPUs.push_back("zEC12");
353 ExpectedCPUs.push_back("zEC12");
355 // Model Id: 2817
356 ExpectedCPUs.push_back("z196");
357 ExpectedCPUs.push_back("z196");
359 // Model Id: 2097
360 ExpectedCPUs.push_back("z10");
361 ExpectedCPUs.push_back("z10");
363 // Model Id: 2064
364 ExpectedCPUs.push_back("generic");
365 ExpectedCPUs.push_back("generic");
367 const std::string DummyBaseVectorInfo =
368 "features : esan3 zarch stfle msa ldisp eimm dfp edat etf3eh highgprs "
369 "te ";
370 const std::string DummyBaseMachineInfo =
371 "processor 0: version = FF, identification = 059C88, machine = ";
373 int CheckIndex = 0;
374 for (size_t I = 0; I < ModelIDs.size(); I++) {
375 for (size_t J = 0; J < VectorSupport.size(); J++) {
376 const std::string DummyCPUInfo = DummyBaseVectorInfo + VectorSupport[J] +
377 "\n" + DummyBaseMachineInfo +
378 ModelIDs[I];
379 EXPECT_EQ(sys::detail::getHostCPUNameForS390x(DummyCPUInfo),
380 ExpectedCPUs[CheckIndex++]);
385 TEST(getLinuxHostCPUName, RISCV) {
386 const StringRef SifiveU74MCProcCPUInfo = R"(
387 processor : 0
388 hart : 2
389 isa : rv64imafdc
390 mmu : sv39
391 uarch : sifive,u74-mc
393 EXPECT_EQ(sys::detail::getHostCPUNameForRISCV(SifiveU74MCProcCPUInfo),
394 "sifive-u74");
395 EXPECT_EQ(
396 sys::detail::getHostCPUNameForRISCV("uarch : sifive,bullet0\n"),
397 "sifive-u74");
400 static bool runAndGetCommandOutput(
401 const char *ExePath, ArrayRef<llvm::StringRef> argv,
402 std::unique_ptr<char[]> &Buffer, off_t &Size) {
403 bool Success = false;
404 [ExePath, argv, &Buffer, &Size, &Success] {
405 using namespace llvm::sys;
406 SmallString<128> TestDirectory;
407 ASSERT_NO_ERROR(fs::createUniqueDirectory("host_test", TestDirectory));
409 SmallString<128> OutputFile(TestDirectory);
410 path::append(OutputFile, "out");
411 StringRef OutputPath = OutputFile.str();
413 const std::optional<StringRef> Redirects[] = {
414 /*STDIN=*/std::nullopt, /*STDOUT=*/OutputPath, /*STDERR=*/std::nullopt};
415 int RetCode =
416 ExecuteAndWait(ExePath, argv, /*env=*/std::nullopt, Redirects);
417 ASSERT_EQ(0, RetCode);
419 int FD = 0;
420 ASSERT_NO_ERROR(fs::openFileForRead(OutputPath, FD));
421 Size = ::lseek(FD, 0, SEEK_END);
422 ASSERT_NE(-1, Size);
423 ::lseek(FD, 0, SEEK_SET);
424 Buffer = std::make_unique<char[]>(Size);
425 ASSERT_EQ(::read(FD, Buffer.get(), Size), Size);
426 ::close(FD);
428 ASSERT_NO_ERROR(fs::remove(OutputPath));
429 ASSERT_NO_ERROR(fs::remove(TestDirectory.str()));
430 Success = true;
431 }();
432 return Success;
435 TEST(HostTest, DummyRunAndGetCommandOutputUse) {
436 // Suppress defined-but-not-used warnings when the tests using the helper are
437 // disabled.
438 (void)&runAndGetCommandOutput;
441 TEST(HostTest, getMacOSHostVersion) {
442 llvm::Triple HostTriple(llvm::sys::getProcessTriple());
443 if (!HostTriple.isMacOSX())
444 GTEST_SKIP();
446 const char *SwVersPath = "/usr/bin/sw_vers";
447 StringRef argv[] = {SwVersPath, "-productVersion"};
448 std::unique_ptr<char[]> Buffer;
449 off_t Size;
450 ASSERT_EQ(runAndGetCommandOutput(SwVersPath, argv, Buffer, Size), true);
451 StringRef SystemVersionStr = StringRef(Buffer.get(), Size).rtrim();
453 // Ensure that the two versions match.
454 VersionTuple SystemVersion;
455 ASSERT_EQ(llvm::Triple((Twine("x86_64-apple-macos") + SystemVersionStr))
456 .getMacOSXVersion(SystemVersion),
457 true);
458 VersionTuple HostVersion;
459 ASSERT_EQ(HostTriple.getMacOSXVersion(HostVersion), true);
461 if (SystemVersion.getMajor() > 10) {
462 // Don't compare the 'Minor' and 'Micro' versions, as they're always '0' for
463 // the 'Darwin' triples on 11.x.
464 ASSERT_EQ(SystemVersion.getMajor(), HostVersion.getMajor());
465 } else {
466 // Don't compare the 'Micro' version, as it's always '0' for the 'Darwin'
467 // triples.
468 ASSERT_EQ(SystemVersion.getMajor(), HostVersion.getMajor());
469 ASSERT_EQ(SystemVersion.getMinor(), HostVersion.getMinor());
473 // Helper to return AIX system version. Must return void to use ASSERT_*.
474 static void getAIXSystemVersion(VersionTuple &SystemVersion) {
475 const char *ExePath = "/usr/bin/oslevel";
476 StringRef argv[] = {ExePath};
477 std::unique_ptr<char[]> Buffer;
478 off_t Size;
479 ASSERT_EQ(runAndGetCommandOutput(ExePath, argv, Buffer, Size), true);
480 StringRef SystemVersionStr = StringRef(Buffer.get(), Size).rtrim();
482 SystemVersion =
483 llvm::Triple((Twine("powerpc-ibm-aix") + SystemVersionStr))
484 .getOSVersion();
487 TEST(HostTest, AIXHostVersionDetect) {
488 llvm::Triple HostTriple(llvm::sys::getProcessTriple());
489 if (HostTriple.getOS() != Triple::AIX)
490 GTEST_SKIP();
492 llvm::Triple ConfiguredHostTriple(LLVM_HOST_TRIPLE);
493 ASSERT_EQ(ConfiguredHostTriple.getOS(), Triple::AIX);
495 VersionTuple SystemVersion;
496 getAIXSystemVersion(SystemVersion);
498 // Ensure that the host triple version (major) and release (minor) numbers,
499 // unless explicitly configured, match with those of the current system.
500 auto SysMajor = SystemVersion.getMajor();
501 auto SysMinor = SystemVersion.getMinor();
502 VersionTuple HostVersion = HostTriple.getOSVersion();
503 if (ConfiguredHostTriple.getOSMajorVersion()) {
504 // Explicitly configured, force a match. We do it this way so the
505 // asserts are always executed.
506 SysMajor = HostVersion.getMajor();
507 SysMinor = HostVersion.getMinor();
509 ASSERT_EQ(SysMajor, HostVersion.getMajor());
510 ASSERT_EQ(SysMinor, HostVersion.getMinor());
513 TEST(HostTest, AIXTargetVersionDetect) {
514 llvm::Triple TargetTriple(llvm::sys::getDefaultTargetTriple());
515 if (TargetTriple.getOS() != Triple::AIX)
516 GTEST_SKIP();
518 // Ensure that the target triple version (major) and release (minor) numbers
519 // match with those of the current system.
520 llvm::Triple ConfiguredTargetTriple(LLVM_DEFAULT_TARGET_TRIPLE);
521 if (ConfiguredTargetTriple.getOSMajorVersion())
522 GTEST_SKIP(); // The version was configured explicitly; skip.
524 VersionTuple SystemVersion;
525 getAIXSystemVersion(SystemVersion);
526 VersionTuple TargetVersion = TargetTriple.getOSVersion();
527 ASSERT_EQ(SystemVersion.getMajor(), TargetVersion.getMajor());
528 ASSERT_EQ(SystemVersion.getMinor(), TargetVersion.getMinor());
531 TEST(HostTest, AIXHostCPUDetect) {
532 llvm::Triple HostTriple(llvm::sys::getProcessTriple());
533 if (HostTriple.getOS() != Triple::AIX)
534 GTEST_SKIP();
536 // Return a value based on the current processor implementation mode.
537 const char *ExePath = "/usr/sbin/getsystype";
538 StringRef argv[] = {ExePath, "-i"};
539 std::unique_ptr<char[]> Buffer;
540 off_t Size;
541 ASSERT_EQ(runAndGetCommandOutput(ExePath, argv, Buffer, Size), true);
542 StringRef CPU(Buffer.get(), Size);
543 StringRef MCPU = StringSwitch<const char *>(CPU)
544 .Case("POWER 4\n", "pwr4")
545 .Case("POWER 5\n", "pwr5")
546 .Case("POWER 6\n", "pwr6")
547 .Case("POWER 7\n", "pwr7")
548 .Case("POWER 8\n", "pwr8")
549 .Case("POWER 9\n", "pwr9")
550 .Case("POWER 10\n", "pwr10")
551 .Case("POWER 11\n", "pwr11")
552 .Default("unknown");
554 StringRef HostCPU = sys::getHostCPUName();
556 // Just do the comparison on the base implementation mode.
557 if (HostCPU == "970")
558 HostCPU = StringRef("pwr4");
559 else
560 HostCPU = HostCPU.rtrim('x');
562 EXPECT_EQ(HostCPU, MCPU);