clang/lib/Basic/Targets/SystemZ.h

   1 //===--- SystemZ.h - Declare SystemZ target feature support -----*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file declares SystemZ TargetInfo objects.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_SYSTEMZ_H
  14 #define LLVM_CLANG_LIB_BASIC_TARGETS_SYSTEMZ_H
  15
  16 #include "clang/Basic/TargetInfo.h"
  17 #include "clang/Basic/TargetOptions.h"
  18 #include "llvm/ADT/Triple.h"
  19 #include "llvm/Support/Compiler.h"
  20
  21 namespace clang {
  22 namespace targets {
  23
  24 class LLVM_LIBRARY_VISIBILITY SystemZTargetInfo : public TargetInfo {
  25
  26   static const Builtin::Info BuiltinInfo[];
  27   static const char *const GCCRegNames[];
  28   std::string CPU;
  29   int ISARevision;
  30   bool HasTransactionalExecution;
  31   bool HasVector;
  32   bool SoftFloat;
  33
  34 public:
  35   SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
  36       : TargetInfo(Triple), CPU("z10"), ISARevision(8),
  37         HasTransactionalExecution(false), HasVector(false), SoftFloat(false) {
  38     IntMaxType = SignedLong;
  39     Int64Type = SignedLong;
  40     TLSSupported = true;
  41     IntWidth = IntAlign = 32;
  42     LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
  43     Int128Align = 64;
  44     PointerWidth = PointerAlign = 64;
  45     LongDoubleWidth = 128;
  46     LongDoubleAlign = 64;
  47     LongDoubleFormat = &llvm::APFloat::IEEEquad();
  48     DefaultAlignForAttributeAligned = 64;
  49     MinGlobalAlign = 16;
  50     if (Triple.isOSzOS()) {
  51       // All vector types are default aligned on an 8-byte boundary, even if the
  52       // vector facility is not available. That is different from Linux.
  53       MaxVectorAlign = 64;
  54       // Compared to Linux/ELF, the data layout differs only in that name
  55       // mangling is GOFF.
  56       resetDataLayout(
  57           "E-m:l-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64");
  58     } else
  59       resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64"
  60                       "-v128:64-a:8:16-n32:64");
  61     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
  62     HasStrictFP = true;
  63   }
  64
  65   void getTargetDefines(const LangOptions &Opts,
  66                         MacroBuilder &Builder) const override;
  67
  68   ArrayRef<Builtin::Info> getTargetBuiltins() const override;
  69
  70   ArrayRef<const char *> getGCCRegNames() const override;
  71
  72   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
  73     // No aliases.
  74     return None;
  75   }
  76
  77   ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override;
  78
  79   bool isSPRegName(StringRef RegName) const override {
  80     return RegName.equals("r15");
  81   }
  82
  83   bool validateAsmConstraint(const char *&Name,
  84                              TargetInfo::ConstraintInfo &info) const override;
  85
  86   std::string convertConstraint(const char *&Constraint) const override {
  87     switch (Constraint[0]) {
  88     case 'p': // Keep 'p' constraint.
  89       return std::string("p");
  90     case 'Z':
  91       switch (Constraint[1]) {
  92       case 'Q': // Address with base and unsigned 12-bit displacement
  93       case 'R': // Likewise, plus an index
  94       case 'S': // Address with base and signed 20-bit displacement
  95       case 'T': // Likewise, plus an index
  96         // "^" hints llvm that this is a 2 letter constraint.
  97         // "Constraint++" is used to promote the string iterator
  98         // to the next constraint.
  99         return std::string("^") + std::string(Constraint++, 2);
 100       default:
 101         break;
 102       }
 103       break;
 104     default:
 105       break;
 106     }
 107     return TargetInfo::convertConstraint(Constraint);
 108   }
 109
 110   const char *getClobbers() const override {
 111     // FIXME: Is this really right?
 112     return "";
 113   }
 114
 115   BuiltinVaListKind getBuiltinVaListKind() const override {
 116     return TargetInfo::SystemZBuiltinVaList;
 117   }
 118
 119   int getISARevision(StringRef Name) const;
 120
 121   bool isValidCPUName(StringRef Name) const override {
 122     return getISARevision(Name) != -1;
 123   }
 124
 125   void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
 126
 127   bool isValidTuneCPUName(StringRef Name) const override {
 128     return isValidCPUName(Name);
 129   }
 130
 131   void fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const override {
 132     fillValidCPUList(Values);
 133   }
 134
 135   bool setCPU(const std::string &Name) override {
 136     CPU = Name;
 137     ISARevision = getISARevision(CPU);
 138     return ISARevision != -1;
 139   }
 140
 141   bool
 142   initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
 143                  StringRef CPU,
 144                  const std::vector<std::string> &FeaturesVec) const override {
 145     int ISARevision = getISARevision(CPU);
 146     if (ISARevision >= 10)
 147       Features["transactional-execution"] = true;
 148     if (ISARevision >= 11)
 149       Features["vector"] = true;
 150     if (ISARevision >= 12)
 151       Features["vector-enhancements-1"] = true;
 152     if (ISARevision >= 13)
 153       Features["vector-enhancements-2"] = true;
 154     if (ISARevision >= 14)
 155       Features["nnp-assist"] = true;
 156     return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
 157   }
 158
 159   bool handleTargetFeatures(std::vector<std::string> &Features,
 160                             DiagnosticsEngine &Diags) override {
 161     HasTransactionalExecution = false;
 162     HasVector = false;
 163     SoftFloat = false;
 164     for (const auto &Feature : Features) {
 165       if (Feature == "+transactional-execution")
 166         HasTransactionalExecution = true;
 167       else if (Feature == "+vector")
 168         HasVector = true;
 169       else if (Feature == "+soft-float")
 170         SoftFloat = true;
 171     }
 172     HasVector &= !SoftFloat;
 173
 174     // If we use the vector ABI, vector types are 64-bit aligned. The
 175     // DataLayout string is always set to this alignment as it is not a
 176     // requirement that it follows the alignment emitted by the front end. It
 177     // is assumed generally that the Datalayout should reflect only the
 178     // target triple and not any specific feature.
 179     if (HasVector && !getTriple().isOSzOS())
 180       MaxVectorAlign = 64;
 181
 182     return true;
 183   }
 184
 185   bool hasFeature(StringRef Feature) const override;
 186
 187   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
 188     switch (CC) {
 189     case CC_C:
 190     case CC_Swift:
 191     case CC_OpenCLKernel:
 192       return CCCR_OK;
 193     case CC_SwiftAsync:
 194       return CCCR_Error;
 195     default:
 196       return CCCR_Warning;
 197     }
 198   }
 199
 200   StringRef getABI() const override {
 201     if (HasVector)
 202       return "vector";
 203     return "";
 204   }
 205
 206   const char *getLongDoubleMangling() const override { return "g"; }
 207
 208   bool hasBitIntType() const override { return true; }
 209
 210   int getEHDataRegisterNumber(unsigned RegNo) const override {
 211     return RegNo < 4 ? 6 + RegNo : -1;
 212   }
 213 };
 214 } // namespace targets
 215 } // namespace clang
 216 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_SYSTEMZ_H