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[docs] Fix build-docs.sh
[llvm-project.git] / llvm / unittests / CodeGen / GlobalISel / KnownBitsTest.cpp
blob7eaeb32e461ba0f7da7bdef769ed13c24fa3d256
1 //===- KnownBitsTest.cpp -------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "GISelMITest.h"
10 #include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
11 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
12
13 TEST_F(AArch64GISelMITest, TestKnownBitsCst) {
14 StringRef MIRString = " %3:_(s8) = G_CONSTANT i8 1\n"
15 " %4:_(s8) = COPY %3\n";
16 setUp(MIRString);
17 if (!TM)
18 return;
19 unsigned CopyReg = Copies[Copies.size() - 1];
20 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
21 unsigned SrcReg = FinalCopy->getOperand(1).getReg();
22 unsigned DstReg = FinalCopy->getOperand(0).getReg();
23 GISelKnownBits Info(*MF);
24 KnownBits Res = Info.getKnownBits(SrcReg);
25 EXPECT_EQ((uint64_t)1, Res.One.getZExtValue());
26 EXPECT_EQ((uint64_t)0xfe, Res.Zero.getZExtValue());
27
28 KnownBits Res2 = Info.getKnownBits(DstReg);
29 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
30 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
31 }
32
33 TEST_F(AArch64GISelMITest, TestKnownBitsCstWithClass) {
34 StringRef MIRString = " %10:gpr32 = MOVi32imm 1\n"
35 " %4:_(s32) = COPY %10\n";
36 setUp(MIRString);
37 if (!TM)
38 return;
39 unsigned CopyReg = Copies[Copies.size() - 1];
40 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
41 unsigned SrcReg = FinalCopy->getOperand(1).getReg();
42 unsigned DstReg = FinalCopy->getOperand(0).getReg();
43 GISelKnownBits Info(*MF);
44 KnownBits Res = Info.getKnownBits(SrcReg);
45 // We can't analyze %3 due to the register class constraint. We will get a
46 // default-constructed KnownBits back.
47 EXPECT_EQ((uint64_t)1, Res.getBitWidth());
48 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
49 EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue());
50
51 KnownBits Res2 = Info.getKnownBits(DstReg);
52 // We still don't know the values due to the register class constraint but %4
53 // did reveal the size of %3.
54 EXPECT_EQ((uint64_t)32, Res2.getBitWidth());
55 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
56 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
57 }
58
59 // Check that we are able to track bits through PHIs
60 // and get the intersections of everything we know on each operand.
61 TEST_F(AArch64GISelMITest, TestKnownBitsCstPHI) {
62 StringRef MIRString = " bb.10:\n"
63 " %10:_(s8) = G_CONSTANT i8 3\n"
64 " %11:_(s1) = G_IMPLICIT_DEF\n"
65 " G_BRCOND %11(s1), %bb.11\n"
66 " G_BR %bb.12\n"
67 "\n"
68 " bb.11:\n"
69 " %12:_(s8) = G_CONSTANT i8 2\n"
70 " G_BR %bb.12\n"
71 "\n"
72 " bb.12:\n"
73 " %13:_(s8) = PHI %10(s8), %bb.10, %12(s8), %bb.11\n"
74 " %14:_(s8) = COPY %13\n";
75 setUp(MIRString);
76 if (!TM)
77 return;
78 Register CopyReg = Copies[Copies.size() - 1];
79 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
80 Register SrcReg = FinalCopy->getOperand(1).getReg();
81 Register DstReg = FinalCopy->getOperand(0).getReg();
82 GISelKnownBits Info(*MF);
83 KnownBits Res = Info.getKnownBits(SrcReg);
84 EXPECT_EQ((uint64_t)2, Res.One.getZExtValue());
85 EXPECT_EQ((uint64_t)0xfc, Res.Zero.getZExtValue());
86
87 KnownBits Res2 = Info.getKnownBits(DstReg);
88 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
89 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
90 }
91
92 // Check that we report we know nothing when we hit a
93 // non-generic register.
94 // Note: this could be improved though!
95 TEST_F(AArch64GISelMITest, TestKnownBitsCstPHIToNonGenericReg) {
96 StringRef MIRString = " bb.10:\n"
97 " %10:gpr32 = MOVi32imm 3\n"
98 " %11:_(s1) = G_IMPLICIT_DEF\n"
99 " G_BRCOND %11(s1), %bb.11\n"
100 " G_BR %bb.12\n"
101 "\n"
102 " bb.11:\n"
103 " %12:_(s8) = G_CONSTANT i8 2\n"
104 " G_BR %bb.12\n"
105 "\n"
106 " bb.12:\n"
107 " %13:_(s8) = PHI %10, %bb.10, %12(s8), %bb.11\n"
108 " %14:_(s8) = COPY %13\n";
109 setUp(MIRString);
110 if (!TM)
111 return;
112 Register CopyReg = Copies[Copies.size() - 1];
113 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
114 Register SrcReg = FinalCopy->getOperand(1).getReg();
115 Register DstReg = FinalCopy->getOperand(0).getReg();
116 GISelKnownBits Info(*MF);
117 KnownBits Res = Info.getKnownBits(SrcReg);
118 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
119 EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue());
120
121 KnownBits Res2 = Info.getKnownBits(DstReg);
122 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
123 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
124 }
125
126 // Check that we know nothing when at least one value of a PHI
127 // comes from something we cannot analysis.
128 // This test is not particularly interesting, it is just
129 // here to cover the code that stops the analysis of PHIs
130 // earlier. In that case, we would not even look at the
131 // second incoming value.
132 TEST_F(AArch64GISelMITest, TestKnownBitsUnknownPHI) {
133 StringRef MIRString =
134 " bb.10:\n"
135 " %10:_(s64) = COPY %0\n"
136 " %11:_(s1) = G_IMPLICIT_DEF\n"
137 " G_BRCOND %11(s1), %bb.11\n"
138 " G_BR %bb.12\n"
139 "\n"
140 " bb.11:\n"
141 " %12:_(s64) = G_CONSTANT i64 2\n"
142 " G_BR %bb.12\n"
143 "\n"
144 " bb.12:\n"
145 " %13:_(s64) = PHI %10(s64), %bb.10, %12(s64), %bb.11\n"
146 " %14:_(s64) = COPY %13\n";
147 setUp(MIRString);
148 if (!TM)
149 return;
150 Register CopyReg = Copies[Copies.size() - 1];
151 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
152 Register SrcReg = FinalCopy->getOperand(1).getReg();
153 Register DstReg = FinalCopy->getOperand(0).getReg();
154 GISelKnownBits Info(*MF);
155 KnownBits Res = Info.getKnownBits(SrcReg);
156 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
157 EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue());
158
159 KnownBits Res2 = Info.getKnownBits(DstReg);
160 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
161 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
162 }
163
164 // Check that we manage to process PHIs that loop on themselves.
165 // For now, the analysis just stops and assumes it knows nothing,
166 // eventually we could teach it how to properly track phis that
167 // loop back.
168 TEST_F(AArch64GISelMITest, TestKnownBitsCstPHIWithLoop) {
169 StringRef MIRString =
170 " bb.10:\n"
171 " %10:_(s8) = G_CONSTANT i8 3\n"
172 " %11:_(s1) = G_IMPLICIT_DEF\n"
173 " G_BRCOND %11(s1), %bb.11\n"
174 " G_BR %bb.12\n"
175 "\n"
176 " bb.11:\n"
177 " %12:_(s8) = G_CONSTANT i8 2\n"
178 " G_BR %bb.12\n"
179 "\n"
180 " bb.12:\n"
181 " %13:_(s8) = PHI %10(s8), %bb.10, %12(s8), %bb.11, %14(s8), %bb.12\n"
182 " %14:_(s8) = COPY %13\n"
183 " G_BR %bb.12\n";
184 setUp(MIRString);
185 if (!TM)
186 return;
187 Register CopyReg = Copies[Copies.size() - 1];
188 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
189 Register SrcReg = FinalCopy->getOperand(1).getReg();
190 Register DstReg = FinalCopy->getOperand(0).getReg();
191 GISelKnownBits Info(*MF);
192 KnownBits Res = Info.getKnownBits(SrcReg);
193 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
194 EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue());
195
196 KnownBits Res2 = Info.getKnownBits(DstReg);
197 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
198 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
199 }
200
201 // Check that we don't try to analysis PHIs progression.
202 // Setting a deep enough max depth would allow to effectively simulate
203 // what happens in the loop.
204 // Thus, with a deep enough depth, we could actually figure out
205 // that %14's zero known bits are actually at least what we know
206 // for %10, right shifted by one.
207 // However, this process is super expensive compile-time wise and
208 // we don't want to reach that conclusion while playing with max depth.
209 // For now, the analysis just stops and assumes it knows nothing
210 // on PHIs, but eventually we could teach it how to properly track
211 // phis that loop back without relying on the luck effect of max
212 // depth.
213 TEST_F(AArch64GISelMITest, TestKnownBitsDecreasingCstPHIWithLoop) {
214 StringRef MIRString = " bb.10:\n"
215 " %10:_(s8) = G_CONSTANT i8 5\n"
216 " %11:_(s8) = G_CONSTANT i8 1\n"
217 "\n"
218 " bb.12:\n"
219 " %13:_(s8) = PHI %10(s8), %bb.10, %14(s8), %bb.12\n"
220 " %14:_(s8) = G_LSHR %13, %11\n"
221 " %15:_(s8) = COPY %14\n"
222 " G_BR %bb.12\n";
223 setUp(MIRString);
224 if (!TM)
225 return;
226 Register CopyReg = Copies[Copies.size() - 1];
227 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
228 Register SrcReg = FinalCopy->getOperand(1).getReg();
229 Register DstReg = FinalCopy->getOperand(0).getReg();
230 GISelKnownBits Info(*MF, /*MaxDepth=*/24);
231 KnownBits Res = Info.getKnownBits(SrcReg);
232 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
233 // A single iteration on the PHI (%13) gives:
234 // %10 has known zero of 0xFA
235 // %12 has known zero of 0x80 (we shift right by one so high bit is zero)
236 // Therefore, %14's known zero are 0x80 shifted by one 0xC0.
237 // If we had simulated the loop we could have more zero bits, basically
238 // up to 0xFC (count leading zero of 5, + 1).
239 EXPECT_EQ((uint64_t)0xC0, Res.Zero.getZExtValue());
240
241 KnownBits Res2 = Info.getKnownBits(DstReg);
242 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
243 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
244 }
245
246 TEST_F(AArch64GISelMITest, TestKnownBitsPtrToIntViceVersa) {
247 StringRef MIRString = " %3:_(s16) = G_CONSTANT i16 256\n"
248 " %4:_(p0) = G_INTTOPTR %3\n"
249 " %5:_(s32) = G_PTRTOINT %4\n"
250 " %6:_(s32) = COPY %5\n";
251 setUp(MIRString);
252 if (!TM)
253 return;
254 unsigned CopyReg = Copies[Copies.size() - 1];
255 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
256 unsigned SrcReg = FinalCopy->getOperand(1).getReg();
257 GISelKnownBits Info(*MF);
258 KnownBits Res = Info.getKnownBits(SrcReg);
259 EXPECT_EQ(256u, Res.One.getZExtValue());
260 EXPECT_EQ(0xfffffeffu, Res.Zero.getZExtValue());
261 }
262
263 TEST_F(AArch64GISelMITest, TestKnownBitsAND) {
264 StringRef MIRString = R"(
265 %ptr:_(p0) = G_IMPLICIT_DEF
266 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
267 %mask0:_(s8) = G_CONSTANT i8 52
268 %mask1:_(s8) = G_CONSTANT i8 10
269 %tmp0:_(s8) = G_AND %unknown, %mask0
270 %val0:_(s8) = G_OR %tmp0, %mask1
271 %mask2:_(s8) = G_CONSTANT i8 32
272 %mask3:_(s8) = G_CONSTANT i8 24
273 %tmp1:_(s8) = G_AND %unknown, %mask2
274 %val1:_(s8) = G_OR %tmp1, %mask3
275 %and:_(s8) = G_AND %val0, %val1
276 %copy_and:_(s8) = COPY %and
277 )";
278
279 setUp(MIRString);
280 if (!TM)
281 return;
282
283 Register CopyReg = Copies[Copies.size() - 1];
284 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
285 Register SrcReg = FinalCopy->getOperand(1).getReg();
286 GISelKnownBits Info(*MF);
287 KnownBits Res = Info.getKnownBits(SrcReg);
288 // 00??1?10
289 // & 00?11000
290 // = 00??1000
291 EXPECT_EQ(0x08u, Res.One.getZExtValue());
292 EXPECT_EQ(0xC7u, Res.Zero.getZExtValue());
293 }
294
295 TEST_F(AArch64GISelMITest, TestKnownBitsOR) {
296 StringRef MIRString = R"(
297 %ptr:_(p0) = G_IMPLICIT_DEF
298 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
299 %mask0:_(s8) = G_CONSTANT i8 52
300 %mask1:_(s8) = G_CONSTANT i8 10
301 %tmp0:_(s8) = G_AND %unknown, %mask0
302 %val0:_(s8) = G_OR %tmp0, %mask1
303 %mask2:_(s8) = G_CONSTANT i8 32
304 %mask3:_(s8) = G_CONSTANT i8 24
305 %tmp1:_(s8) = G_AND %unknown, %mask2
306 %val1:_(s8) = G_OR %tmp1, %mask3
307 %or:_(s8) = G_OR %val0, %val1
308 %copy_or:_(s8) = COPY %or
309 )";
310
311 setUp(MIRString);
312 if (!TM)
313 return;
314
315 Register CopyReg = Copies[Copies.size() - 1];
316 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
317 Register SrcReg = FinalCopy->getOperand(1).getReg();
318 GISelKnownBits Info(*MF);
319 KnownBits Res = Info.getKnownBits(SrcReg);
320 // 00??1?10
321 // | 00?11000
322 // = 00?11?10
323 EXPECT_EQ(0x1Au, Res.One.getZExtValue());
324 EXPECT_EQ(0xC1u, Res.Zero.getZExtValue());
325 }
326
327 TEST_F(AArch64GISelMITest, TestKnownBitsXOR) {
328 StringRef MIRString = R"(
329 %ptr:_(p0) = G_IMPLICIT_DEF
330 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
331 %mask0:_(s8) = G_CONSTANT i8 52
332 %mask1:_(s8) = G_CONSTANT i8 10
333 %tmp0:_(s8) = G_AND %unknown, %mask0
334 %val0:_(s8) = G_OR %tmp0, %mask1
335 %mask2:_(s8) = G_CONSTANT i8 32
336 %mask3:_(s8) = G_CONSTANT i8 24
337 %tmp1:_(s8) = G_AND %unknown, %mask2
338 %val1:_(s8) = G_OR %tmp1, %mask3
339 %xor:_(s8) = G_XOR %val0, %val1
340 %copy_xor:_(s8) = COPY %xor
341 )";
342
343 setUp(MIRString);
344 if (!TM)
345 return;
346
347 Register CopyReg = Copies[Copies.size() - 1];
348 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
349 Register SrcReg = FinalCopy->getOperand(1).getReg();
350 GISelKnownBits Info(*MF);
351 KnownBits Res = Info.getKnownBits(SrcReg);
352 // Xor KnowBits does not track if we are doing xor of unknown bit with itself
353 // or negated itself.
354 // 00??1?10
355 // ^ 00?11000
356 // = 00??0?10
357 EXPECT_EQ(0x02u, Res.One.getZExtValue());
358 EXPECT_EQ(0xC9u, Res.Zero.getZExtValue());
359 }
360
361 TEST_F(AArch64GISelMITest, TestKnownBitsXORConstant) {
362 StringRef MIRString = " %3:_(s8) = G_CONSTANT i8 4\n"
363 " %4:_(s8) = G_CONSTANT i8 7\n"
364 " %5:_(s8) = G_XOR %3, %4\n"
365 " %6:_(s8) = COPY %5\n";
366 setUp(MIRString);
367 if (!TM)
368 return;
369 unsigned CopyReg = Copies[Copies.size() - 1];
370 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
371 unsigned SrcReg = FinalCopy->getOperand(1).getReg();
372 GISelKnownBits Info(*MF);
373 KnownBits Res = Info.getKnownBits(SrcReg);
374 EXPECT_EQ(3u, Res.One.getZExtValue());
375 EXPECT_EQ(252u, Res.Zero.getZExtValue());
376 }
377
378 TEST_F(AArch64GISelMITest, TestKnownBitsASHR) {
379 StringRef MIRString = R"(
380 %ptr:_(p0) = G_IMPLICIT_DEF
381 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
382 %mask0:_(s8) = G_CONSTANT i8 38
383 %mask1:_(s8) = G_CONSTANT i8 202
384 %tmp0:_(s8) = G_AND %unknown, %mask0
385 %val0:_(s8) = G_OR %tmp0, %mask1
386 %cst0:_(s8) = G_CONSTANT i8 2
387 %ashr0:_(s8) = G_ASHR %val0, %cst0
388 %copy_ashr0:_(s8) = COPY %ashr0
389
390 %mask2:_(s8) = G_CONSTANT i8 204
391 %mask3:_(s8) = G_CONSTANT i8 18
392 %tmp1:_(s8) = G_AND %unknown, %mask2
393 %val1:_(s8) = G_OR %tmp1, %mask3
394 %ashr1:_(s8) = G_ASHR %val1, %cst0
395 %copy_ashr1:_(s8) = COPY %ashr1
396 )";
397
398 setUp(MIRString);
399 if (!TM)
400 return;
401
402 Register CopyReg0 = Copies[Copies.size() - 2];
403 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
404 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
405 GISelKnownBits Info(*MF);
406 KnownBits Res0 = Info.getKnownBits(SrcReg0);
407 // 11?01??0 >> 2
408 // = 1111?01?
409 EXPECT_EQ(0xF2u, Res0.One.getZExtValue());
410 EXPECT_EQ(0x04u, Res0.Zero.getZExtValue());
411
412 Register CopyReg1 = Copies[Copies.size() - 1];
413 MachineInstr *FinalCopy1 = MRI->getVRegDef(CopyReg1);
414 Register SrcReg1 = FinalCopy1->getOperand(1).getReg();
415 KnownBits Res1 = Info.getKnownBits(SrcReg1);
416 // ??01??10 >> 2
417 // = ????01??
418 EXPECT_EQ(0x04u, Res1.One.getZExtValue());
419 EXPECT_EQ(0x08u, Res1.Zero.getZExtValue());
420 }
421
422 TEST_F(AArch64GISelMITest, TestKnownBitsLSHR) {
423 StringRef MIRString = R"(
424 %ptr:_(p0) = G_IMPLICIT_DEF
425 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
426 %mask0:_(s8) = G_CONSTANT i8 38
427 %mask1:_(s8) = G_CONSTANT i8 202
428 %tmp0:_(s8) = G_AND %unknown, %mask0
429 %val0:_(s8) = G_OR %tmp0, %mask1
430 %cst0:_(s8) = G_CONSTANT i8 2
431 %lshr0:_(s8) = G_LSHR %val0, %cst0
432 %copy_lshr0:_(s8) = COPY %lshr0
433
434 %mask2:_(s8) = G_CONSTANT i8 204
435 %mask3:_(s8) = G_CONSTANT i8 18
436 %tmp1:_(s8) = G_AND %unknown, %mask2
437 %val1:_(s8) = G_OR %tmp1, %mask3
438 %lshr1:_(s8) = G_LSHR %val1, %cst0
439 %copy_lshr1:_(s8) = COPY %lshr1
440 )";
441
442 setUp(MIRString);
443 if (!TM)
444 return;
445
446 Register CopyReg0 = Copies[Copies.size() - 2];
447 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
448 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
449 GISelKnownBits Info(*MF);
450 KnownBits Res0 = Info.getKnownBits(SrcReg0);
451 // 11?01??0 >> 2
452 // = 0011?01?
453 EXPECT_EQ(0x32u, Res0.One.getZExtValue());
454 EXPECT_EQ(0xC4u, Res0.Zero.getZExtValue());
455
456 Register CopyReg1 = Copies[Copies.size() - 1];
457 MachineInstr *FinalCopy1 = MRI->getVRegDef(CopyReg1);
458 Register SrcReg1 = FinalCopy1->getOperand(1).getReg();
459 KnownBits Res1 = Info.getKnownBits(SrcReg1);
460 // ??01??10 >> 2
461 // = 00??01??
462 EXPECT_EQ(0x04u, Res1.One.getZExtValue());
463 EXPECT_EQ(0xC8u, Res1.Zero.getZExtValue());
464 }
465
466 TEST_F(AArch64GISelMITest, TestKnownBitsSHL) {
467 StringRef MIRString = R"(
468 %ptr:_(p0) = G_IMPLICIT_DEF
469 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
470 %mask0:_(s8) = G_CONSTANT i8 51
471 %mask1:_(s8) = G_CONSTANT i8 72
472 %tmp:_(s8) = G_AND %unknown, %mask0
473 %val:_(s8) = G_OR %tmp, %mask1
474 %cst:_(s8) = G_CONSTANT i8 3
475 %shl:_(s8) = G_SHL %val, %cst
476 %copy_shl:_(s8) = COPY %shl
477 )";
478
479 setUp(MIRString);
480 if (!TM)
481 return;
482
483 Register CopyReg = Copies[Copies.size() - 1];
484 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
485 Register SrcReg = FinalCopy->getOperand(1).getReg();
486 GISelKnownBits Info(*MF);
487 KnownBits Res = Info.getKnownBits(SrcReg);
488 // 01??10?? << 3
489 // = ?10??000
490 EXPECT_EQ(0x40u, Res.One.getZExtValue());
491 EXPECT_EQ(0x27u, Res.Zero.getZExtValue());
492 }
493
494 TEST_F(AArch64GISelMITest, TestKnownBitsADD) {
495 StringRef MIRString = R"(
496 %ptr:_(p0) = G_IMPLICIT_DEF
497 %unknown:_(s16) = G_LOAD %ptr(p0) :: (load (s16))
498 %mask0:_(s16) = G_CONSTANT i16 4642
499 %mask1:_(s16) = G_CONSTANT i16 9536
500 %tmp0:_(s16) = G_AND %unknown, %mask0
501 %val0:_(s16) = G_OR %tmp0, %mask1
502 %mask2:_(s16) = G_CONSTANT i16 4096
503 %mask3:_(s16) = G_CONSTANT i16 371
504 %tmp1:_(s16) = G_AND %unknown, %mask2
505 %val1:_(s16) = G_OR %tmp1, %mask3
506 %add:_(s16) = G_ADD %val0, %val1
507 %copy_add:_(s16) = COPY %add
508 )";
509
510 setUp(MIRString);
511 if (!TM)
512 return;
513
514 Register CopyReg = Copies[Copies.size() - 1];
515 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
516 Register SrcReg = FinalCopy->getOperand(1).getReg();
517 GISelKnownBits Info(*MF);
518 KnownBits Res = Info.getKnownBits(SrcReg);
519 // Add KnowBits works out known carry bits first and then calculates result.
520 // 001?01?101?000?0
521 // + 000?000101110011
522 // = 0??????01??10??1
523 EXPECT_EQ(0x0091u, Res.One.getZExtValue());
524 EXPECT_EQ(0x8108u, Res.Zero.getZExtValue());
525 }
526
527 TEST_F(AArch64GISelMITest, TestKnownBitsSUB) {
528 StringRef MIRString = R"(
529 %ptr:_(p0) = G_IMPLICIT_DEF
530 %unknown:_(s16) = G_LOAD %ptr(p0) :: (load (s16))
531 %mask0:_(s16) = G_CONSTANT i16 4642
532 %mask1:_(s16) = G_CONSTANT i16 9536
533 %tmp0:_(s16) = G_AND %unknown, %mask0
534 %val0:_(s16) = G_OR %tmp0, %mask1
535 %mask2:_(s16) = G_CONSTANT i16 4096
536 %mask3:_(s16) = G_CONSTANT i16 371
537 %tmp1:_(s16) = G_AND %unknown, %mask2
538 %val1:_(s16) = G_OR %tmp1, %mask3
539 %sub:_(s16) = G_SUB %val0, %val1
540 %copy_sub:_(s16) = COPY %sub
541 )";
542
543 setUp(MIRString);
544 if (!TM)
545 return;
546
547 Register CopyReg = Copies[Copies.size() - 1];
548 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
549 Register SrcReg = FinalCopy->getOperand(1).getReg();
550 GISelKnownBits Info(*MF);
551 KnownBits Res = Info.getKnownBits(SrcReg);
552 // Sub KnowBits for LHS - RHS use Add KnownBits for LHS + ~RHS + 1.
553 EXPECT_EQ(0x01CDu, Res.One.getZExtValue());
554 EXPECT_EQ(0xC810u, Res.Zero.getZExtValue());
555 }
556
557 TEST_F(AArch64GISelMITest, TestKnownBitsMUL) {
558 StringRef MIRString = R"(
559 %ptr0:_(p0) = G_IMPLICIT_DEF
560 %load0:_(s16) = G_LOAD %ptr0(p0) :: (load (s16))
561 %mask0:_(s16) = G_CONSTANT i16 4
562 %mask1:_(s16) = G_CONSTANT i16 18
563 %tmp:_(s16) = G_AND %load0, %mask0
564 %val0:_(s16) = G_OR %tmp, %mask1
565 %cst:_(s16) = G_CONSTANT i16 12
566 %mul:_(s16) = G_MUL %val0, %cst
567 %copy_mul:_(s16) = COPY %mul
568 )";
569
570 setUp(MIRString);
571 if (!TM)
572 return;
573
574 Register CopyReg = Copies[Copies.size() - 1];
575 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
576 Register SrcReg = FinalCopy->getOperand(1).getReg();
577 GISelKnownBits Info(*MF);
578 KnownBits Res = Info.getKnownBits(SrcReg);
579 // Mul KnowBits are conservatively correct, but not guaranteed to be precise.
580 // Precise for trailing bits up to the first unknown bit.
581 // 00010?10 * 00001100 =
582 // 00010?1000
583 // + 00010?10000
584 // = 0000000010??1000
585 // KB 0000000?????1000
586 EXPECT_EQ(0x0008u, Res.One.getZExtValue());
587 EXPECT_EQ(0xFE07u, Res.Zero.getZExtValue());
588 }
589
590 TEST_F(AArch64GISelMITest, TestKnownBitsICMP) {
591 StringRef MIRString = R"(
592 %cst0:_(s32) = G_CONSTANT i32 0
593 %cst1:_(s32) = G_CONSTANT i32 1
594 %icmp:_(s32) = G_ICMP intpred(ne), %cst0, %cst1
595 %copy_icmp:_(s32) = COPY %icmp
596 )";
597
598 setUp(MIRString);
599 if (!TM)
600 return;
601
602 Register CopyReg = Copies[Copies.size() - 1];
603 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
604 Register SrcReg = FinalCopy->getOperand(1).getReg();
605 GISelKnownBits Info(*MF);
606 KnownBits Res = Info.getKnownBits(SrcReg);
607 // For targets that use 0 or 1 as icmp result in large register set high bits
608 // to 0, does not analyze operands/compare predicate.
609 EXPECT_EQ(0x00000000u, Res.One.getZExtValue());
610 EXPECT_EQ(0xFFFFFFFEu, Res.Zero.getZExtValue());
611 }
612
613 TEST_F(AArch64GISelMITest, TestKnownBitsFCMP) {
614 StringRef MIRString = R"(
615 %cst0:_(s32) = G_FCONSTANT float 0.0
616 %cst1:_(s32) = G_FCONSTANT float 1.0
617 %fcmp:_(s32) = G_FCMP floatpred(one), %cst0, %cst1
618 %copy_fcmp:_(s32) = COPY %fcmp
619 )";
620
621 setUp(MIRString);
622 if (!TM)
623 return;
624
625 Register CopyReg = Copies[Copies.size() - 1];
626 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
627 Register SrcReg = FinalCopy->getOperand(1).getReg();
628 GISelKnownBits Info(*MF);
629 KnownBits Res = Info.getKnownBits(SrcReg);
630 // For targets that use 0 or 1 as fcmp result in large register set high bits
631 // to 0, does not analyze operands/compare predicate.
632 EXPECT_EQ(0x00000000u, Res.One.getZExtValue());
633 EXPECT_EQ(0xFFFFFFFEu, Res.Zero.getZExtValue());
634 }
635
636 TEST_F(AArch64GISelMITest, TestKnownBitsSelect) {
637 StringRef MIRString = R"(
638 %ptr:_(p0) = G_IMPLICIT_DEF
639 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
640 %mask0:_(s8) = G_CONSTANT i8 24
641 %mask1:_(s8) = G_CONSTANT i8 224
642 %tmp0:_(s8) = G_AND %unknown, %mask0
643 %val0:_(s8) = G_OR %tmp0, %mask1
644 %mask2:_(s8) = G_CONSTANT i8 146
645 %mask3:_(s8) = G_CONSTANT i8 36
646 %tmp1:_(s8) = G_AND %unknown, %mask2
647 %val1:_(s8) = G_OR %tmp1, %mask3
648 %cond:_(s1) = G_CONSTANT i1 false
649 %select:_(s8) = G_SELECT %cond, %val0, %val1
650 %copy_select:_(s8) = COPY %select
651 )";
652
653 setUp(MIRString);
654 if (!TM)
655 return;
656
657 Register CopyReg = Copies[Copies.size() - 1];
658 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
659 Register SrcReg = FinalCopy->getOperand(1).getReg();
660 GISelKnownBits Info(*MF);
661 KnownBits Res = Info.getKnownBits(SrcReg);
662 // Select KnownBits takes common bits of LHS and RHS, does not analyze
663 // condition operand.
664 // 111??000
665 // select ?01?01?0
666 // = ??1????0
667 EXPECT_EQ(0x20u, Res.One.getZExtValue());
668 EXPECT_EQ(0x01u, Res.Zero.getZExtValue());
669 }
670
671 TEST_F(AArch64GISelMITest, TestKnownBits) {
672
673 StringRef MIR = " %3:_(s32) = G_TRUNC %0\n"
674 " %4:_(s32) = G_TRUNC %1\n"
675 " %5:_(s32) = G_CONSTANT i32 5\n"
676 " %6:_(s32) = G_CONSTANT i32 24\n"
677 " %7:_(s32) = G_CONSTANT i32 28\n"
678 " %14:_(p0) = G_INTTOPTR %7\n"
679 " %16:_(s32) = G_PTRTOINT %14\n"
680 " %8:_(s32) = G_SHL %3, %5\n"
681 " %9:_(s32) = G_SHL %4, %5\n"
682 " %10:_(s32) = G_OR %8, %6\n"
683 " %11:_(s32) = G_OR %9, %16\n"
684 " %12:_(s32) = G_MUL %10, %11\n"
685 " %13:_(s32) = COPY %12\n";
686 setUp(MIR);
687 if (!TM)
688 return;
689 unsigned CopyReg = Copies[Copies.size() - 1];
690 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
691 unsigned SrcReg = FinalCopy->getOperand(1).getReg();
692 GISelKnownBits Info(*MF);
693 KnownBits Known = Info.getKnownBits(SrcReg);
694 EXPECT_FALSE(Known.hasConflict());
695 EXPECT_EQ(32u, Known.One.getZExtValue());
696 EXPECT_EQ(95u, Known.Zero.getZExtValue());
697 APInt Zeroes = Info.getKnownZeroes(SrcReg);
698 EXPECT_EQ(Known.Zero, Zeroes);
699 }
700
701 TEST_F(AArch64GISelMITest, TestSignBitIsZero) {
702 setUp();
703 if (!TM)
704 return;
705
706 const LLT S32 = LLT::scalar(32);
707 auto SignBit = B.buildConstant(S32, 0x80000000);
708 auto Zero = B.buildConstant(S32, 0);
709
710 GISelKnownBits KnownBits(*MF);
711
712 EXPECT_TRUE(KnownBits.signBitIsZero(Zero.getReg(0)));
713 EXPECT_FALSE(KnownBits.signBitIsZero(SignBit.getReg(0)));
714 }
715
716 TEST_F(AArch64GISelMITest, TestNumSignBitsConstant) {
717 StringRef MIRString = " %3:_(s8) = G_CONSTANT i8 1\n"
718 " %4:_(s8) = COPY %3\n"
719
720 " %5:_(s8) = G_CONSTANT i8 -1\n"
721 " %6:_(s8) = COPY %5\n"
722
723 " %7:_(s8) = G_CONSTANT i8 127\n"
724 " %8:_(s8) = COPY %7\n"
725
726 " %9:_(s8) = G_CONSTANT i8 32\n"
727 " %10:_(s8) = COPY %9\n"
728
729 " %11:_(s8) = G_CONSTANT i8 -32\n"
730 " %12:_(s8) = COPY %11\n";
731 setUp(MIRString);
732 if (!TM)
733 return;
734 Register CopyReg1 = Copies[Copies.size() - 5];
735 Register CopyRegNeg1 = Copies[Copies.size() - 4];
736 Register CopyReg127 = Copies[Copies.size() - 3];
737 Register CopyReg32 = Copies[Copies.size() - 2];
738 Register CopyRegNeg32 = Copies[Copies.size() - 1];
739
740 GISelKnownBits Info(*MF);
741 EXPECT_EQ(7u, Info.computeNumSignBits(CopyReg1));
742 EXPECT_EQ(8u, Info.computeNumSignBits(CopyRegNeg1));
743 EXPECT_EQ(1u, Info.computeNumSignBits(CopyReg127));
744 EXPECT_EQ(2u, Info.computeNumSignBits(CopyReg32));
745 EXPECT_EQ(3u, Info.computeNumSignBits(CopyRegNeg32));
746 }
747
748 TEST_F(AArch64GISelMITest, TestNumSignBitsSext) {
749 StringRef MIRString = " %3:_(p0) = G_IMPLICIT_DEF\n"
750 " %4:_(s8) = G_LOAD %3 :: (load (s8))\n"
751 " %5:_(s32) = G_SEXT %4\n"
752 " %6:_(s32) = COPY %5\n"
753
754 " %7:_(s8) = G_CONSTANT i8 -1\n"
755 " %8:_(s32) = G_SEXT %7\n"
756 " %9:_(s32) = COPY %8\n";
757 setUp(MIRString);
758 if (!TM)
759 return;
760 Register CopySextLoad = Copies[Copies.size() - 2];
761 Register CopySextNeg1 = Copies[Copies.size() - 1];
762
763 GISelKnownBits Info(*MF);
764 EXPECT_EQ(25u, Info.computeNumSignBits(CopySextLoad));
765 EXPECT_EQ(32u, Info.computeNumSignBits(CopySextNeg1));
766 }
767
768 TEST_F(AArch64GISelMITest, TestNumSignBitsSextInReg) {
769 StringRef MIRString = R"(
770 %ptr:_(p0) = G_IMPLICIT_DEF
771 %load4:_(s32) = G_LOAD %ptr :: (load (s32))
772
773 %inreg7:_(s32) = G_SEXT_INREG %load4, 7
774 %copy_inreg7:_(s32) = COPY %inreg7
775
776 %inreg8:_(s32) = G_SEXT_INREG %load4, 8
777 %copy_inreg8:_(s32) = COPY %inreg8
778
779 %inreg9:_(s32) = G_SEXT_INREG %load4, 9
780 %copy_inreg9:_(s32) = COPY %inreg9
781
782 %inreg31:_(s32) = G_SEXT_INREG %load4, 31
783 %copy_inreg31:_(s32) = COPY %inreg31
784
785 %load1:_(s8) = G_LOAD %ptr :: (load (s8))
786 %sext_load1:_(s32) = G_SEXT %load1
787
788 %inreg6_sext:_(s32) = G_SEXT_INREG %sext_load1, 6
789 %copy_inreg6_sext:_(s32) = COPY %inreg6_sext
790
791 %inreg7_sext:_(s32) = G_SEXT_INREG %sext_load1, 7
792 %copy_inreg7_sext:_(s32) = COPY %inreg7_sext
793
794 %inreg8_sext:_(s32) = G_SEXT_INREG %sext_load1, 8
795 %copy_inreg8_sext:_(s32) = COPY %inreg8_sext
796
797 %inreg9_sext:_(s32) = G_SEXT_INREG %sext_load1, 9
798 %copy_inreg9_sext:_(s32) = COPY %inreg9_sext
799
800 %inreg31_sext:_(s32) = G_SEXT_INREG %sext_load1, 31
801 %copy_inreg31_sext:_(s32) = COPY %inreg31_sext
802 )";
803
804 setUp(MIRString);
805 if (!TM)
806 return;
807
808 Register CopyInReg7 = Copies[Copies.size() - 9];
809 Register CopyInReg8 = Copies[Copies.size() - 8];
810 Register CopyInReg9 = Copies[Copies.size() - 7];
811 Register CopyInReg31 = Copies[Copies.size() - 6];
812
813 Register CopyInReg6Sext = Copies[Copies.size() - 5];
814 Register CopyInReg7Sext = Copies[Copies.size() - 4];
815 Register CopyInReg8Sext = Copies[Copies.size() - 3];
816 Register CopyInReg9Sext = Copies[Copies.size() - 2];
817 Register CopyInReg31Sext = Copies[Copies.size() - 1];
818
819 GISelKnownBits Info(*MF);
820 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7));
821 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8));
822 EXPECT_EQ(24u, Info.computeNumSignBits(CopyInReg9));
823 EXPECT_EQ(2u, Info.computeNumSignBits(CopyInReg31));
824
825 EXPECT_EQ(27u, Info.computeNumSignBits(CopyInReg6Sext));
826 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7Sext));
827 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8Sext));
828 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg9Sext));
829 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg31Sext));
830 }
831
832 TEST_F(AArch64GISelMITest, TestNumSignBitsAssertSext) {
833 StringRef MIRString = R"(
834 %ptr:_(p0) = G_IMPLICIT_DEF
835 %load4:_(s32) = G_LOAD %ptr :: (load (s32))
836
837 %assert_sext1:_(s32) = G_ASSERT_SEXT %load4, 1
838 %copy_assert_sext1:_(s32) = COPY %assert_sext1
839
840 %assert_sext7:_(s32) = G_ASSERT_SEXT %load4, 7
841 %copy_assert_sext7:_(s32) = COPY %assert_sext7
842
843 %assert_sext8:_(s32) = G_ASSERT_SEXT %load4, 8
844 %copy_assert_sext8:_(s32) = COPY %assert_sext8
845
846 %assert_sext9:_(s32) = G_ASSERT_SEXT %load4, 9
847 %copy_assert_sext9:_(s32) = COPY %assert_sext9
848
849 %assert_sext31:_(s32) = G_ASSERT_SEXT %load4, 31
850 %copy_assert_sext31:_(s32) = COPY %assert_sext31
851
852 %load1:_(s8) = G_LOAD %ptr :: (load (s8))
853 %sext_load1:_(s32) = G_SEXT %load1
854
855 %assert_sext6_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 6
856 %copy_assert_sext6_sext:_(s32) = COPY %assert_sext6_sext
857
858 %assert_sext7_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 7
859 %copy_assert_sext7_sext:_(s32) = COPY %assert_sext7_sext
860
861 %assert_sext8_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 8
862 %copy_assert_sext8_sext:_(s32) = COPY %assert_sext8_sext
863
864 %assert_sext9_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 9
865 %copy_assert_sext9_sext:_(s32) = COPY %assert_sext9_sext
866
867 %assert_sext31_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 31
868 %copy_assert_sext31_sext:_(s32) = COPY %assert_sext31_sext
869 )";
870
871 setUp(MIRString);
872 if (!TM)
873 return;
874
875 Register CopyInReg1 = Copies[Copies.size() - 10];
876 Register CopyInReg7 = Copies[Copies.size() - 9];
877 Register CopyInReg8 = Copies[Copies.size() - 8];
878 Register CopyInReg9 = Copies[Copies.size() - 7];
879 Register CopyInReg31 = Copies[Copies.size() - 6];
880
881 Register CopyInReg6Sext = Copies[Copies.size() - 5];
882 Register CopyInReg7Sext = Copies[Copies.size() - 4];
883 Register CopyInReg8Sext = Copies[Copies.size() - 3];
884 Register CopyInReg9Sext = Copies[Copies.size() - 2];
885 Register CopyInReg31Sext = Copies[Copies.size() - 1];
886
887 GISelKnownBits Info(*MF);
888 EXPECT_EQ(32u, Info.computeNumSignBits(CopyInReg1));
889 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7));
890 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8));
891 EXPECT_EQ(24u, Info.computeNumSignBits(CopyInReg9));
892 EXPECT_EQ(2u, Info.computeNumSignBits(CopyInReg31));
893
894 EXPECT_EQ(27u, Info.computeNumSignBits(CopyInReg6Sext));
895 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7Sext));
896 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8Sext));
897 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg9Sext));
898 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg31Sext));
899 }
900
901 TEST_F(AArch64GISelMITest, TestNumSignBitsTrunc) {
902 StringRef MIRString = " %3:_(p0) = G_IMPLICIT_DEF\n"
903 " %4:_(s32) = G_LOAD %3 :: (load (s32))\n"
904 " %5:_(s8) = G_TRUNC %4\n"
905 " %6:_(s8) = COPY %5\n"
906
907 " %7:_(s32) = G_CONSTANT i32 -1\n"
908 " %8:_(s8) = G_TRUNC %7\n"
909 " %9:_(s8) = COPY %8\n"
910
911 " %10:_(s32) = G_CONSTANT i32 7\n"
912 " %11:_(s8) = G_TRUNC %10\n"
913 " %12:_(s8) = COPY %11\n";
914 setUp(MIRString);
915 if (!TM)
916 return;
917 Register CopyTruncLoad = Copies[Copies.size() - 3];
918 Register CopyTruncNeg1 = Copies[Copies.size() - 2];
919 Register CopyTrunc7 = Copies[Copies.size() - 1];
920
921 GISelKnownBits Info(*MF);
922 EXPECT_EQ(1u, Info.computeNumSignBits(CopyTruncLoad));
923 EXPECT_EQ(8u, Info.computeNumSignBits(CopyTruncNeg1));
924 EXPECT_EQ(5u, Info.computeNumSignBits(CopyTrunc7));
925 }
926
927 TEST_F(AMDGPUGISelMITest, TestNumSignBitsTrunc) {
928 StringRef MIRString =
929 " %3:_(<4 x s32>) = G_IMPLICIT_DEF\n"
930 " %4:_(s32) = G_IMPLICIT_DEF\n"
931 " %5:_(s32) = G_AMDGPU_BUFFER_LOAD_UBYTE %3, %4, %4, %4, 0, 0, 0 :: (load (s8))\n"
932 " %6:_(s32) = COPY %5\n"
933
934 " %7:_(s32) = G_AMDGPU_BUFFER_LOAD_SBYTE %3, %4, %4, %4, 0, 0, 0 :: (load (s8))\n"
935 " %8:_(s32) = COPY %7\n"
936
937 " %9:_(s32) = G_AMDGPU_BUFFER_LOAD_USHORT %3, %4, %4, %4, 0, 0, 0 :: (load (s16))\n"
938 " %10:_(s32) = COPY %9\n"
939
940 " %11:_(s32) = G_AMDGPU_BUFFER_LOAD_SSHORT %3, %4, %4, %4, 0, 0, 0 :: (load (s16))\n"
941 " %12:_(s32) = COPY %11\n";
942
943 setUp(MIRString);
944 if (!TM)
945 return;
946
947 Register CopyLoadUByte = Copies[Copies.size() - 4];
948 Register CopyLoadSByte = Copies[Copies.size() - 3];
949 Register CopyLoadUShort = Copies[Copies.size() - 2];
950 Register CopyLoadSShort = Copies[Copies.size() - 1];
951
952 GISelKnownBits Info(*MF);
953
954 EXPECT_EQ(24u, Info.computeNumSignBits(CopyLoadUByte));
955 EXPECT_EQ(25u, Info.computeNumSignBits(CopyLoadSByte));
956 EXPECT_EQ(16u, Info.computeNumSignBits(CopyLoadUShort));
957 EXPECT_EQ(17u, Info.computeNumSignBits(CopyLoadSShort));
958 }
959
960 TEST_F(AMDGPUGISelMITest, TestTargetKnownAlign) {
961 StringRef MIRString =
962 " %5:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.dispatch.ptr)\n"
963 " %6:_(p4) = COPY %5\n"
964 " %7:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.queue.ptr)\n"
965 " %8:_(p4) = COPY %7\n"
966 " %9:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)\n"
967 " %10:_(p4) = COPY %9\n"
968 " %11:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.implicitarg.ptr)\n"
969 " %12:_(p4) = COPY %11\n"
970 " %13:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.implicit.buffer.ptr)\n"
971 " %14:_(p4) = COPY %13\n";
972
973 setUp(MIRString);
974 if (!TM)
975 return;
976
977 Register CopyDispatchPtr = Copies[Copies.size() - 5];
978 Register CopyQueuePtr = Copies[Copies.size() - 4];
979 Register CopyKernargSegmentPtr = Copies[Copies.size() - 3];
980 Register CopyImplicitArgPtr = Copies[Copies.size() - 2];
981 Register CopyImplicitBufferPtr = Copies[Copies.size() - 1];
982
983 GISelKnownBits Info(*MF);
984
985 EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyDispatchPtr));
986 EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyQueuePtr));
987 EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyKernargSegmentPtr));
988 EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyImplicitArgPtr));
989 EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyImplicitBufferPtr));
990 }
991
992 TEST_F(AMDGPUGISelMITest, TestIsKnownToBeAPowerOfTwo) {
993
994 StringRef MIRString = R"MIR(
995 %zero:_(s32) = G_CONSTANT i32 0
996 %one:_(s32) = G_CONSTANT i32 1
997 %two:_(s32) = G_CONSTANT i32 2
998 %three:_(s32) = G_CONSTANT i32 3
999 %five:_(s32) = G_CONSTANT i32 5
1000 %copy_zero:_(s32) = COPY %zero
1001 %copy_one:_(s32) = COPY %one
1002 %copy_two:_(s32) = COPY %two
1003 %copy_three:_(s32) = COPY %three
1004
1005 %trunc_two:_(s1) = G_TRUNC %two
1006 %trunc_three:_(s1) = G_TRUNC %three
1007 %trunc_five:_(s1) = G_TRUNC %five
1008
1009 %copy_trunc_two:_(s1) = COPY %trunc_two
1010 %copy_trunc_three:_(s1) = COPY %trunc_three
1011 %copy_trunc_five:_(s1) = COPY %trunc_five
1012
1013 %ptr:_(p1) = G_IMPLICIT_DEF
1014 %shift_amt:_(s32) = G_LOAD %ptr :: (load (s32), addrspace 1)
1015
1016 %shl_1:_(s32) = G_SHL %one, %shift_amt
1017 %copy_shl_1:_(s32) = COPY %shl_1
1018
1019 %shl_2:_(s32) = G_SHL %two, %shift_amt
1020 %copy_shl_2:_(s32) = COPY %shl_2
1021
1022 %not_sign_mask:_(s32) = G_LOAD %ptr :: (load (s32), addrspace 1)
1023 %sign_mask:_(s32) = G_CONSTANT i32 -2147483648
1024
1025 %lshr_not_sign_mask:_(s32) = G_LSHR %not_sign_mask, %shift_amt
1026 %copy_lshr_not_sign_mask:_(s32) = COPY %lshr_not_sign_mask
1027
1028 %lshr_sign_mask:_(s32) = G_LSHR %sign_mask, %shift_amt
1029 %copy_lshr_sign_mask:_(s32) = COPY %lshr_sign_mask
1030
1031 %or_pow2:_(s32) = G_OR %zero, %two
1032 %copy_or_pow2:_(s32) = COPY %or_pow2
1033
1034 )MIR";
1035 setUp(MIRString);
1036 if (!TM)
1037 return;
1038
1039 GISelKnownBits KB(*MF);
1040
1041 Register CopyZero = Copies[Copies.size() - 12];
1042 Register CopyOne = Copies[Copies.size() - 11];
1043 Register CopyTwo = Copies[Copies.size() - 10];
1044 Register CopyThree = Copies[Copies.size() - 9];
1045 Register CopyTruncTwo = Copies[Copies.size() - 8];
1046 Register CopyTruncThree = Copies[Copies.size() - 7];
1047 Register CopyTruncFive = Copies[Copies.size() - 6];
1048
1049 Register CopyShl1 = Copies[Copies.size() - 5];
1050 Register CopyShl2 = Copies[Copies.size() - 4];
1051
1052 Register CopyLShrNotSignMask = Copies[Copies.size() - 3];
1053 Register CopyLShrSignMask = Copies[Copies.size() - 2];
1054 Register CopyOrPow2 = Copies[Copies.size() - 1];
1055
1056 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyZero, *MRI, &KB));
1057 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyOne, *MRI, &KB));
1058 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyTwo, *MRI, &KB));
1059 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyThree, *MRI, &KB));
1060
1061 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyTruncTwo, *MRI, &KB));
1062 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyTruncThree, *MRI, &KB));
1063 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyTruncFive, *MRI, &KB));
1064
1065 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyShl1, *MRI, &KB));
1066 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyShl2, *MRI, &KB));
1067
1068 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyLShrNotSignMask, *MRI, &KB));
1069 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyLShrSignMask, *MRI, &KB));
1070 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyOrPow2, *MRI, &KB));
1071 }
1072
1073 TEST_F(AArch64GISelMITest, TestMetadata) {
1074 StringRef MIRString = " %imp:_(p0) = G_IMPLICIT_DEF\n"
1075 " %load:_(s8) = G_LOAD %imp(p0) :: (load (s8))\n"
1076 " %ext:_(s32) = G_ZEXT %load(s8)\n"
1077 " %cst:_(s32) = G_CONSTANT i32 1\n"
1078 " %and:_(s32) = G_AND %ext, %cst\n"
1079 " %copy:_(s32) = COPY %and(s32)\n";
1080 setUp(MIRString);
1081 if (!TM)
1082 return;
1083
1084 Register CopyReg = Copies[Copies.size() - 1];
1085 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
1086 Register SrcReg = FinalCopy->getOperand(1).getReg();
1087
1088 // We need a load with a metadata range for this to break. Fudge the load in
1089 // the string and replace it with something we can work with.
1090 MachineInstr *And = MRI->getVRegDef(SrcReg);
1091 MachineInstr *Ext = MRI->getVRegDef(And->getOperand(1).getReg());
1092 MachineInstr *Load = MRI->getVRegDef(Ext->getOperand(1).getReg());
1093 IntegerType *Int8Ty = Type::getInt8Ty(Context);
1094
1095 // Value must be in [0, 2)
1096 Metadata *LowAndHigh[] = {
1097 ConstantAsMetadata::get(ConstantInt::get(Int8Ty, 0)),
1098 ConstantAsMetadata::get(ConstantInt::get(Int8Ty, 2))};
1099 auto NewMDNode = MDNode::get(Context, LowAndHigh);
1100 const MachineMemOperand *OldMMO = *Load->memoperands_begin();
1101 MachineMemOperand NewMMO(OldMMO->getPointerInfo(), OldMMO->getFlags(),
1102 OldMMO->getSizeInBits(), OldMMO->getAlign(),
1103 OldMMO->getAAInfo(), NewMDNode);
1104 MachineIRBuilder MIB(*Load);
1105 MIB.buildLoad(Load->getOperand(0), Load->getOperand(1), NewMMO);
1106 Load->eraseFromParent();
1107
1108 GISelKnownBits Info(*MF);
1109 KnownBits Res = Info.getKnownBits(And->getOperand(1).getReg());
1110
1111 // We don't know what the result of the load is, so we don't know any ones.
1112 EXPECT_TRUE(Res.One.isZero());
1113
1114 // We know that the value is in [0, 2). So, we don't know if the first bit
1115 // is 0 or not. However, we do know that every other bit must be 0.
1116 APInt Mask(Res.getBitWidth(), 1);
1117 Mask.flipAllBits();
1118 EXPECT_EQ(Mask.getZExtValue(), Res.Zero.getZExtValue());
1119 }
1120
1121 TEST_F(AArch64GISelMITest, TestKnownBitsExt) {
1122 StringRef MIRString = " %c1:_(s16) = G_CONSTANT i16 1\n"
1123 " %x:_(s16) = G_IMPLICIT_DEF\n"
1124 " %y:_(s16) = G_AND %x, %c1\n"
1125 " %anyext:_(s32) = G_ANYEXT %y(s16)\n"
1126 " %r1:_(s32) = COPY %anyext\n"
1127 " %zext:_(s32) = G_ZEXT %y(s16)\n"
1128 " %r2:_(s32) = COPY %zext\n"
1129 " %sext:_(s32) = G_SEXT %y(s16)\n"
1130 " %r3:_(s32) = COPY %sext\n";
1131 setUp(MIRString);
1132 if (!TM)
1133 return;
1134 Register CopyRegAny = Copies[Copies.size() - 3];
1135 Register CopyRegZ = Copies[Copies.size() - 2];
1136 Register CopyRegS = Copies[Copies.size() - 1];
1137
1138 GISelKnownBits Info(*MF);
1139 MachineInstr *Copy;
1140 Register SrcReg;
1141 KnownBits Res;
1142
1143 Copy = MRI->getVRegDef(CopyRegAny);
1144 SrcReg = Copy->getOperand(1).getReg();
1145 Res = Info.getKnownBits(SrcReg);
1146 EXPECT_EQ((uint64_t)32, Res.getBitWidth());
1147 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
1148 EXPECT_EQ((uint64_t)0x0000fffe, Res.Zero.getZExtValue());
1149
1150 Copy = MRI->getVRegDef(CopyRegZ);
1151 SrcReg = Copy->getOperand(1).getReg();
1152 Res = Info.getKnownBits(SrcReg);
1153 EXPECT_EQ((uint64_t)32, Res.getBitWidth());
1154 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
1155 EXPECT_EQ((uint64_t)0xfffffffe, Res.Zero.getZExtValue());
1156
1157 Copy = MRI->getVRegDef(CopyRegS);
1158 SrcReg = Copy->getOperand(1).getReg();
1159 Res = Info.getKnownBits(SrcReg);
1160 EXPECT_EQ((uint64_t)32, Res.getBitWidth());
1161 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
1162 EXPECT_EQ((uint64_t)0xfffffffe, Res.Zero.getZExtValue());
1163 }
1164
1165 TEST_F(AArch64GISelMITest, TestKnownBitsSextInReg) {
1166 StringRef MIRString = R"(
1167 ; 000...0001
1168 %one:_(s32) = G_CONSTANT i32 1
1169
1170 ; 000...0010
1171 %two:_(s32) = G_CONSTANT i32 2
1172
1173 ; 000...1010
1174 %ten:_(s32) = G_CONSTANT i32 10
1175
1176 ; ???...????
1177 %w0:_(s32) = COPY $w0
1178
1179 ; ???...?1?
1180 %or:_(s32) = G_OR %w0, %two
1181
1182 ; All bits are known.
1183 %inreg1:_(s32) = G_SEXT_INREG %one, 1
1184 %copy_inreg1:_(s32) = COPY %inreg1
1185
1186 ; All bits unknown
1187 %inreg2:_(s32) = G_SEXT_INREG %or, 1
1188 %copy_inreg2:_(s32) = COPY %inreg2
1189
1190 ; Extending from the only (known) set bit
1191 ; 111...11?
1192 %inreg3:_(s32) = G_SEXT_INREG %or, 2
1193 %copy_inreg3:_(s32) = COPY %inreg3
1194
1195 ; Extending from a known set bit, overwriting all of the high set bits.
1196 ; 111...1110
1197 %inreg4:_(s32) = G_SEXT_INREG %ten, 2
1198 %copy_inreg4:_(s32) = COPY %inreg4
1199
1200 )";
1201 setUp(MIRString);
1202 if (!TM)
1203 return;
1204 GISelKnownBits Info(*MF);
1205 KnownBits Res;
1206 auto GetKB = [&](unsigned Idx) {
1207 Register CopyReg = Copies[Idx];
1208 auto *Copy = MRI->getVRegDef(CopyReg);
1209 return Info.getKnownBits(Copy->getOperand(1).getReg());
1210 };
1211
1212 // Every bit is known to be a 1.
1213 Res = GetKB(Copies.size() - 4);
1214 EXPECT_EQ(32u, Res.getBitWidth());
1215 EXPECT_TRUE(Res.isAllOnes());
1216
1217 // All bits are unknown
1218 Res = GetKB(Copies.size() - 3);
1219 EXPECT_EQ(32u, Res.getBitWidth());
1220 EXPECT_TRUE(Res.isUnknown());
1221
1222 // Extending from the only known set bit
1223 // 111...11?
1224 Res = GetKB(Copies.size() - 2);
1225 EXPECT_EQ(32u, Res.getBitWidth());
1226 EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue());
1227 EXPECT_EQ(0u, Res.Zero.getZExtValue());
1228
1229 // Extending from a known set bit, overwriting all of the high set bits.
1230 // 111...1110
1231 Res = GetKB(Copies.size() - 1);
1232 EXPECT_EQ(32u, Res.getBitWidth());
1233 EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue());
1234 EXPECT_EQ(1u, Res.Zero.getZExtValue());
1235 }
1236
1237 TEST_F(AArch64GISelMITest, TestKnownBitsAssertSext) {
1238 StringRef MIRString = R"(
1239 ; 000...0001
1240 %one:_(s32) = G_CONSTANT i32 1
1241
1242 ; 000...0010
1243 %two:_(s32) = G_CONSTANT i32 2
1244
1245 ; 000...1010
1246 %ten:_(s32) = G_CONSTANT i32 10
1247
1248 ; ???...????
1249 %w0:_(s32) = COPY $w0
1250
1251 ; ???...?1?
1252 %or:_(s32) = G_OR %w0, %two
1253
1254 ; All bits are known.
1255 %assert_sext1:_(s32) = G_ASSERT_SEXT %one, 1
1256 %copy_assert_sext1:_(s32) = COPY %assert_sext1
1257
1258 ; All bits unknown
1259 %assert_sext2:_(s32) = G_ASSERT_SEXT %or, 1
1260 %copy_assert_sext2:_(s32) = COPY %assert_sext2
1261
1262 ; Extending from the only (known) set bit
1263 ; 111...11?
1264 %assert_sext3:_(s32) = G_ASSERT_SEXT %or, 2
1265 %copy_assert_sext3:_(s32) = COPY %assert_sext3
1266
1267 ; Extending from a known set bit, overwriting all of the high set bits.
1268 ; 111...1110
1269 %assert_sext4:_(s32) = G_ASSERT_SEXT %ten, 2
1270 %copy_assert_sext4:_(s32) = COPY %assert_sext4
1271 )";
1272 setUp(MIRString);
1273 if (!TM)
1274 return;
1275 GISelKnownBits Info(*MF);
1276 KnownBits Res;
1277 auto GetKB = [&](unsigned Idx) {
1278 Register CopyReg = Copies[Idx];
1279 auto *Copy = MRI->getVRegDef(CopyReg);
1280 return Info.getKnownBits(Copy->getOperand(1).getReg());
1281 };
1282
1283 // Every bit is known to be a 1.
1284 Res = GetKB(Copies.size() - 4);
1285 EXPECT_EQ(32u, Res.getBitWidth());
1286 EXPECT_TRUE(Res.isAllOnes());
1287
1288 // All bits are unknown
1289 Res = GetKB(Copies.size() - 3);
1290 EXPECT_EQ(32u, Res.getBitWidth());
1291 EXPECT_TRUE(Res.isUnknown());
1292
1293 // Extending from the only known set bit
1294 // 111...11?
1295 Res = GetKB(Copies.size() - 2);
1296 EXPECT_EQ(32u, Res.getBitWidth());
1297 EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue());
1298 EXPECT_EQ(0u, Res.Zero.getZExtValue());
1299
1300 // Extending from a known set bit, overwriting all of the high set bits.
1301 // 111...1110
1302 Res = GetKB(Copies.size() - 1);
1303 EXPECT_EQ(32u, Res.getBitWidth());
1304 EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue());
1305 EXPECT_EQ(1u, Res.Zero.getZExtValue());
1306 }
1307
1308 TEST_F(AArch64GISelMITest, TestKnownBitsMergeValues) {
1309 StringRef MIRString = R"(
1310 %val0:_(s16) = G_CONSTANT i16 35224
1311 %val1:_(s16) = G_CONSTANT i16 17494
1312 %val2:_(s16) = G_CONSTANT i16 4659
1313 %val3:_(s16) = G_CONSTANT i16 43981
1314 %merge:_(s64) = G_MERGE_VALUES %val0, %val1, %val2, %val3
1315 %mergecopy:_(s64) = COPY %merge
1316 )";
1317 setUp(MIRString);
1318 if (!TM)
1319 return;
1320
1321 const uint64_t TestVal = UINT64_C(0xabcd123344568998);
1322 Register CopyMerge = Copies[Copies.size() - 1];
1323
1324 GISelKnownBits Info(*MF);
1325 KnownBits Res = Info.getKnownBits(CopyMerge);
1326 EXPECT_EQ(64u, Res.getBitWidth());
1327 EXPECT_EQ(TestVal, Res.One.getZExtValue());
1328 EXPECT_EQ(~TestVal, Res.Zero.getZExtValue());
1329 }
1330
1331 TEST_F(AArch64GISelMITest, TestKnownBitsUnmergeValues) {
1332 StringRef MIRString = R"(
1333 %val:_(s64) = G_CONSTANT i64 12379570962110515608
1334 %val0:_(s16), %val1:_(s16), %val2:_(s16), %val3:_(s16) = G_UNMERGE_VALUES %val
1335 %part0:_(s16) = COPY %val0
1336 %part1:_(s16) = COPY %val1
1337 %part2:_(s16) = COPY %val2
1338 %part3:_(s16) = COPY %val3
1339
1340 )";
1341 setUp(MIRString);
1342 if (!TM)
1343 return;
1344
1345 const uint64_t TestVal = UINT64_C(0xabcd123344568998);
1346 GISelKnownBits Info(*MF);
1347
1348 int Offset = -4;
1349 for (unsigned BitOffset = 0; BitOffset != 64; BitOffset += 16, ++Offset) {
1350 Register Part = Copies[Copies.size() + Offset];
1351 KnownBits PartKnown = Info.getKnownBits(Part);
1352 EXPECT_EQ(16u, PartKnown.getBitWidth());
1353
1354 uint16_t PartTestVal = static_cast<uint16_t>(TestVal >> BitOffset);
1355 EXPECT_EQ(PartTestVal, PartKnown.One.getZExtValue());
1356 EXPECT_EQ(static_cast<uint16_t>(~PartTestVal), PartKnown.Zero.getZExtValue());
1357 }
1358 }
1359
1360 TEST_F(AArch64GISelMITest, TestKnownBitsBSwapBitReverse) {
1361 StringRef MIRString = R"(
1362 %const:_(s32) = G_CONSTANT i32 287454020
1363 %bswap:_(s32) = G_BSWAP %const
1364 %bitreverse:_(s32) = G_BITREVERSE %const
1365 %copy_bswap:_(s32) = COPY %bswap
1366 %copy_bitreverse:_(s32) = COPY %bitreverse
1367 )";
1368 setUp(MIRString);
1369 if (!TM)
1370 return;
1371
1372 const uint32_t ByteSwappedVal = 0x44332211;
1373 const uint32_t BitSwappedVal = 0x22cc4488;
1374
1375 Register CopyBSwap = Copies[Copies.size() - 2];
1376 Register CopyBitReverse = Copies[Copies.size() - 1];
1377
1378 GISelKnownBits Info(*MF);
1379
1380 KnownBits BSwapKnown = Info.getKnownBits(CopyBSwap);
1381 EXPECT_EQ(32u, BSwapKnown.getBitWidth());
1382 EXPECT_EQ(ByteSwappedVal, BSwapKnown.One.getZExtValue());
1383 EXPECT_EQ(~ByteSwappedVal, BSwapKnown.Zero.getZExtValue());
1384
1385 KnownBits BitReverseKnown = Info.getKnownBits(CopyBitReverse);
1386 EXPECT_EQ(32u, BitReverseKnown.getBitWidth());
1387 EXPECT_EQ(BitSwappedVal, BitReverseKnown.One.getZExtValue());
1388 EXPECT_EQ(~BitSwappedVal, BitReverseKnown.Zero.getZExtValue());
1389 }
1390
1391 TEST_F(AArch64GISelMITest, TestKnownBitsUMAX) {
1392 StringRef MIRString = R"(
1393 %ptr:_(p0) = G_IMPLICIT_DEF
1394 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
1395 %mask0:_(s8) = G_CONSTANT i8 10
1396 %mask1:_(s8) = G_CONSTANT i8 1
1397 %tmp0:_(s8) = G_AND %unknown, %mask0
1398 %val0:_(s8) = G_OR %tmp0, %mask1
1399 %mask2:_(s8) = G_CONSTANT i8 3
1400 %mask3:_(s8) = G_CONSTANT i8 12
1401 %tmp1:_(s8) = G_AND %unknown, %mask2
1402 %val1:_(s8) = G_OR %tmp1, %mask3
1403 %umax0:_(s8) = G_UMAX %val0, %val1
1404 %copy_umax0:_(s8) = COPY %umax0
1405
1406 %mask4:_(s8) = G_CONSTANT i8 14
1407 %mask5:_(s8) = G_CONSTANT i8 2
1408 %tmp3:_(s8) = G_AND %unknown, %mask4
1409 %val3:_(s8) = G_OR %tmp3, %mask5
1410 %mask6:_(s8) = G_CONSTANT i8 4
1411 %mask7:_(s8) = G_CONSTANT i8 11
1412 %tmp4:_(s8) = G_AND %unknown, %mask6
1413 %val4:_(s8) = G_OR %tmp4, %mask7
1414 %umax1:_(s8) = G_UMAX %val3, %val4
1415 %copy_umax1:_(s8) = COPY %umax1
1416 )";
1417
1418 setUp(MIRString);
1419 if (!TM)
1420 return;
1421
1422 Register CopyReg0 = Copies[Copies.size() - 2];
1423 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
1424 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
1425 GISelKnownBits Info(*MF);
1426 // Compares min/max of LHS and RHS, min uses 0 for unknown bits, max uses 1.
1427 // If min(LHS) >= max(RHS) returns KnownBits for LHS, similar for RHS. If this
1428 // fails tries to calculate individual bits: common bits for both operands and
1429 // a few leading bits in some cases.
1430 // 0000?0?1
1431 // umax 000011??
1432 // = 000011??
1433 KnownBits Res0 = Info.getKnownBits(SrcReg0);
1434 EXPECT_EQ(0x0Cu, Res0.One.getZExtValue());
1435 EXPECT_EQ(0xF0u, Res0.Zero.getZExtValue());
1436
1437 Register CopyReg1 = Copies[Copies.size() - 1];
1438 MachineInstr *FinalCopy1 = MRI->getVRegDef(CopyReg1);
1439 Register SrcReg1 = FinalCopy1->getOperand(1).getReg();
1440 KnownBits Res1 = Info.getKnownBits(SrcReg1);
1441 // 0000??10
1442 // umax 00001?11
1443 // = 00001?1?
1444 EXPECT_EQ(0x0Au, Res1.One.getZExtValue());
1445 EXPECT_EQ(0xF0u, Res1.Zero.getZExtValue());
1446 }
1447
1448 TEST_F(AArch64GISelMITest, TestKnownBitsUMax) {
1449 StringRef MIRString = R"(
1450 %val:_(s32) = COPY $w0
1451 %zext:_(s64) = G_ZEXT %val
1452 %const:_(s64) = G_CONSTANT i64 -256
1453 %umax:_(s64) = G_UMAX %zext, %const
1454 %copy_umax:_(s64) = COPY %umax
1455 )";
1456 setUp(MIRString);
1457 if (!TM)
1458 return;
1459
1460 Register CopyUMax = Copies[Copies.size() - 1];
1461 GISelKnownBits Info(*MF);
1462
1463 KnownBits KnownUmax = Info.getKnownBits(CopyUMax);
1464 EXPECT_EQ(64u, KnownUmax.getBitWidth());
1465 EXPECT_EQ(0xffu, KnownUmax.Zero.getZExtValue());
1466 EXPECT_EQ(0xffffffffffffff00, KnownUmax.One.getZExtValue());
1467
1468 EXPECT_EQ(0xffu, KnownUmax.Zero.getZExtValue());
1469 EXPECT_EQ(0xffffffffffffff00, KnownUmax.One.getZExtValue());
1470 }
1471
1472 TEST_F(AArch64GISelMITest, TestKnownBitsUMIN) {
1473 StringRef MIRString = R"(
1474 %ptr:_(p0) = G_IMPLICIT_DEF
1475 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
1476 %mask0:_(s8) = G_CONSTANT i8 10
1477 %mask1:_(s8) = G_CONSTANT i8 1
1478 %tmp0:_(s8) = G_AND %unknown, %mask0
1479 %val0:_(s8) = G_OR %tmp0, %mask1
1480 %mask2:_(s8) = G_CONSTANT i8 3
1481 %mask3:_(s8) = G_CONSTANT i8 12
1482 %tmp1:_(s8) = G_AND %unknown, %mask2
1483 %val1:_(s8) = G_OR %tmp1, %mask3
1484 %umin:_(s8) = G_UMIN %val0, %val1
1485 %copy_umin:_(s8) = COPY %umin
1486 )";
1487
1488 setUp(MIRString);
1489 if (!TM)
1490 return;
1491
1492 Register CopyReg0 = Copies[Copies.size() - 1];
1493 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
1494 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
1495 GISelKnownBits Info(*MF);
1496 KnownBits Res0 = Info.getKnownBits(SrcReg0);
1497 // Flips the range of operands: [0, 0xFFFFFFFF] <-> [0xFFFFFFFF, 0],
1498 // uses umax and flips result back.
1499 // 0000?0?1
1500 // umin 000011??
1501 // = 0000?0?1
1502 EXPECT_EQ(0x01u, Res0.One.getZExtValue());
1503 EXPECT_EQ(0xF4u, Res0.Zero.getZExtValue());
1504 }
1505
1506 TEST_F(AArch64GISelMITest, TestKnownBitsSMAX) {
1507 StringRef MIRString = R"(
1508 %ptr:_(p0) = G_IMPLICIT_DEF
1509 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
1510 %mask0:_(s8) = G_CONSTANT i8 128
1511 %mask1:_(s8) = G_CONSTANT i8 64
1512 %tmp0:_(s8) = G_AND %unknown, %mask0
1513 %val0:_(s8) = G_OR %tmp0, %mask1
1514 %mask2:_(s8) = G_CONSTANT i8 1
1515 %mask3:_(s8) = G_CONSTANT i8 128
1516 %tmp1:_(s8) = G_AND %unknown, %mask2
1517 %val1:_(s8) = G_OR %tmp1, %mask3
1518 %smax:_(s8) = G_SMAX %val0, %val1
1519 %copy_smax:_(s8) = COPY %smax
1520 )";
1521
1522 setUp(MIRString);
1523 if (!TM)
1524 return;
1525
1526 Register CopyReg0 = Copies[Copies.size() - 1];
1527 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
1528 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
1529 GISelKnownBits Info(*MF);
1530 KnownBits Res0 = Info.getKnownBits(SrcReg0);
1531 // Flips the range of operands: [-0x80000000, 0x7FFFFFFF] <-> [0, 0xFFFFFFFF],
1532 // uses umax and flips result back.
1533 // RHS is negative, LHS is either positive or negative with smaller abs value.
1534 // ?1000000
1535 // smax 1000000?
1536 // = ?1000000
1537 EXPECT_EQ(0x40u, Res0.One.getZExtValue());
1538 EXPECT_EQ(0x3Fu, Res0.Zero.getZExtValue());
1539 }
1540
1541 TEST_F(AArch64GISelMITest, TestKnownBitsSMIN) {
1542 StringRef MIRString = R"(
1543 %ptr:_(p0) = G_IMPLICIT_DEF
1544 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
1545 %mask0:_(s8) = G_CONSTANT i8 128
1546 %mask1:_(s8) = G_CONSTANT i8 64
1547 %tmp0:_(s8) = G_AND %unknown, %mask0
1548 %val0:_(s8) = G_OR %tmp0, %mask1
1549 %mask2:_(s8) = G_CONSTANT i8 1
1550 %mask3:_(s8) = G_CONSTANT i8 128
1551 %tmp1:_(s8) = G_AND %unknown, %mask2
1552 %val1:_(s8) = G_OR %tmp1, %mask3
1553 %smin:_(s8) = G_SMIN %val0, %val1
1554 %copy_smin:_(s8) = COPY %smin
1555 )";
1556
1557 setUp(MIRString);
1558 if (!TM)
1559 return;
1560
1561 Register CopyReg0 = Copies[Copies.size() - 1];
1562 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
1563 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
1564 GISelKnownBits Info(*MF);
1565 KnownBits Res0 = Info.getKnownBits(SrcReg0);
1566 // Flips the range of operands: [-0x80000000, 0x7FFFFFFF] <-> [0xFFFFFFFF, 0],
1567 // uses umax and flips result back.
1568 // RHS is negative, LHS is either positive or negative with smaller abs value.
1569 // ?1000000
1570 // smin 1000000?
1571 // = 1000000?
1572 EXPECT_EQ(0x80u, Res0.One.getZExtValue());
1573 EXPECT_EQ(0x7Eu, Res0.Zero.getZExtValue());
1574 }
1575
1576 TEST_F(AArch64GISelMITest, TestInvalidQueries) {
1577 StringRef MIRString = R"(
1578 %src:_(s32) = COPY $w0
1579 %thirty2:_(s32) = G_CONSTANT i32 32
1580 %equalSized:_(s32) = G_SHL %src, %thirty2
1581 %copy1:_(s32) = COPY %equalSized
1582 %thirty3:_(s32) = G_CONSTANT i32 33
1583 %biggerSized:_(s32) = G_SHL %src, %thirty3
1584 %copy2:_(s32) = COPY %biggerSized
1585 )";
1586 setUp(MIRString);
1587 if (!TM)
1588 return;
1589
1590 Register EqSizedCopyReg = Copies[Copies.size() - 2];
1591 MachineInstr *EqSizedCopy = MRI->getVRegDef(EqSizedCopyReg);
1592 Register EqSizedShl = EqSizedCopy->getOperand(1).getReg();
1593
1594 Register BiggerSizedCopyReg = Copies[Copies.size() - 1];
1595 MachineInstr *BiggerSizedCopy = MRI->getVRegDef(BiggerSizedCopyReg);
1596 Register BiggerSizedShl = BiggerSizedCopy->getOperand(1).getReg();
1597
1598 GISelKnownBits Info(*MF);
1599 KnownBits EqSizeRes = Info.getKnownBits(EqSizedShl);
1600 KnownBits BiggerSizeRes = Info.getKnownBits(BiggerSizedShl);
1601
1602
1603 // We don't know what the result of the shift is, but we should not crash
1604 EXPECT_TRUE(EqSizeRes.One.isZero());
1605 EXPECT_TRUE(EqSizeRes.Zero.isZero());
1606
1607 EXPECT_TRUE(BiggerSizeRes.One.isZero());
1608 EXPECT_TRUE(BiggerSizeRes.Zero.isZero());
1609 }
1610
1611 TEST_F(AArch64GISelMITest, TestKnownBitsAssertZext) {
1612 StringRef MIRString = R"(
1613 %copy:_(s64) = COPY $x0
1614
1615 %assert8:_(s64) = G_ASSERT_ZEXT %copy, 8
1616 %copy_assert8:_(s64) = COPY %assert8
1617
1618 %assert1:_(s64) = G_ASSERT_ZEXT %copy, 1
1619 %copy_assert1:_(s64) = COPY %assert1
1620
1621 %assert63:_(s64) = G_ASSERT_ZEXT %copy, 63
1622 %copy_assert63:_(s64) = COPY %assert63
1623
1624 %assert3:_(s64) = G_ASSERT_ZEXT %copy, 3
1625 %copy_assert3:_(s64) = COPY %assert3
1626 )";
1627
1628 setUp(MIRString);
1629 if (!TM)
1630 return;
1631
1632 Register CopyAssert8 = Copies[Copies.size() - 4];
1633 Register CopyAssert1 = Copies[Copies.size() - 3];
1634 Register CopyAssert63 = Copies[Copies.size() - 2];
1635 Register CopyAssert3 = Copies[Copies.size() - 1];
1636
1637 GISelKnownBits Info(*MF);
1638 MachineInstr *Copy;
1639 Register SrcReg;
1640 KnownBits Res;
1641
1642 // Assert zero-extension from an 8-bit value.
1643 Copy = MRI->getVRegDef(CopyAssert8);
1644 SrcReg = Copy->getOperand(1).getReg();
1645 Res = Info.getKnownBits(SrcReg);
1646 EXPECT_EQ(64u, Res.getBitWidth());
1647 EXPECT_EQ(0u, Res.One.getZExtValue());
1648 EXPECT_EQ(0xFFFFFFFFFFFFFF00u, Res.Zero.getZExtValue());
1649
1650 // Assert zero-extension from a 1-bit value.
1651 Copy = MRI->getVRegDef(CopyAssert1);
1652 SrcReg = Copy->getOperand(1).getReg();
1653 Res = Info.getKnownBits(SrcReg);
1654 EXPECT_EQ(64u, Res.getBitWidth());
1655 EXPECT_EQ(0u, Res.One.getZExtValue());
1656 EXPECT_EQ(0xFFFFFFFFFFFFFFFE, Res.Zero.getZExtValue());
1657
1658 // Assert zero-extension from a 63-bit value.
1659 Copy = MRI->getVRegDef(CopyAssert63);
1660 SrcReg = Copy->getOperand(1).getReg();
1661 Res = Info.getKnownBits(SrcReg);
1662 EXPECT_EQ(64u, Res.getBitWidth());
1663 EXPECT_EQ(0u, Res.One.getZExtValue());
1664 EXPECT_EQ(0x8000000000000000u, Res.Zero.getZExtValue());
1665
1666 // Assert zero-extension from a 3-bit value.
1667 Copy = MRI->getVRegDef(CopyAssert3);
1668 SrcReg = Copy->getOperand(1).getReg();
1669 Res = Info.getKnownBits(SrcReg);
1670 EXPECT_EQ(64u, Res.getBitWidth());
1671 EXPECT_EQ(0u, Res.One.getZExtValue());
1672 EXPECT_EQ(0xFFFFFFFFFFFFFFF8u, Res.Zero.getZExtValue());
1673 }
1674
1675 TEST_F(AArch64GISelMITest, TestKnownBitsCTPOP) {
1676 StringRef MIRString = R"(
1677 %src:_(s32) = COPY $w0
1678 %unknown:_(s32) = G_CTPOP %src
1679 %unknown_copy:_(s32) = COPY %unknown
1680 %constant_4294967295:_(s32) = G_CONSTANT i32 4294967295
1681 %thirtytwo:_(s32) = G_CTPOP %constant_4294967295
1682 %thirtytwo_copy:_(s32) = COPY %thirtytwo
1683 %constant_15:_(s32) = G_CONSTANT i32 15
1684 %four:_(s32) = G_CTPOP %constant_15
1685 %four_copy:_(s32) = COPY %four
1686 %constant_1:_(s32) = G_CONSTANT i32 1
1687 %one:_(s32) = G_CTPOP %constant_1
1688 %one_copy:_(s32) = COPY %one
1689 )";
1690 setUp(MIRString);
1691 if (!TM)
1692 return;
1693
1694 Register UnknownCopy = Copies[Copies.size() - 4];
1695 Register ThirtytwoCopy = Copies[Copies.size() - 3];
1696 Register FourCopy = Copies[Copies.size() - 2];
1697 Register OneCopy = Copies[Copies.size() - 1];
1698
1699 GISelKnownBits Info(*MF);
1700 MachineInstr *Copy;
1701 Register SrcReg;
1702 KnownBits Res;
1703
1704 Copy = MRI->getVRegDef(UnknownCopy);
1705 SrcReg = Copy->getOperand(1).getReg();
1706 Res = Info.getKnownBits(SrcReg);
1707 EXPECT_EQ(32u, Res.getBitWidth());
1708 EXPECT_EQ(0u, Res.One.getZExtValue());
1709 EXPECT_EQ(0xFFFFFFC0u, Res.Zero.getZExtValue());
1710
1711 Copy = MRI->getVRegDef(ThirtytwoCopy);
1712 SrcReg = Copy->getOperand(1).getReg();
1713 Res = Info.getKnownBits(SrcReg);
1714 EXPECT_EQ(32u, Res.getBitWidth());
1715 EXPECT_EQ(0u, Res.One.getZExtValue());
1716 EXPECT_EQ(0xFFFFFFC0u, Res.Zero.getZExtValue());
1717
1718 Copy = MRI->getVRegDef(FourCopy);
1719 SrcReg = Copy->getOperand(1).getReg();
1720 Res = Info.getKnownBits(SrcReg);
1721 EXPECT_EQ(32u, Res.getBitWidth());
1722 EXPECT_EQ(0u, Res.One.getZExtValue());
1723 EXPECT_EQ(0xFFFFFFF8u, Res.Zero.getZExtValue());
1724
1725 Copy = MRI->getVRegDef(OneCopy);
1726 SrcReg = Copy->getOperand(1).getReg();
1727 Res = Info.getKnownBits(SrcReg);
1728 EXPECT_EQ(32u, Res.getBitWidth());
1729 EXPECT_EQ(0u, Res.One.getZExtValue());
1730 EXPECT_EQ(0xFFFFFFFEu, Res.Zero.getZExtValue());
1731 }
1732
1733 TEST_F(AMDGPUGISelMITest, TestKnownBitsUBFX) {
1734 StringRef MIRString = " %3:_(s32) = G_IMPLICIT_DEF\n"
1735 " %4:_(s32) = G_CONSTANT i32 12\n"
1736 " %5:_(s32) = G_CONSTANT i32 8\n"
1737 " %6:_(s32) = G_UBFX %3, %4(s32), %5\n"
1738 " %ubfx_copy:_(s32) = COPY %6\n"
1739 " %7:_(s32) = G_CONSTANT i32 28672\n"
1740 " %8:_(s32) = G_UBFX %7, %4(s32), %5\n"
1741 " %ubfx_copy_val:_(s32) = COPY %8\n"
1742 " %9:_(s32) = G_IMPLICIT_DEF\n"
1743 " %10:_(s32) = G_IMPLICIT_DEF\n"
1744 " %11:_(s32) = G_UBFX %3, %9(s32), %10\n"
1745 " %ubfx_copy_unk:_(s32) = COPY %11\n"
1746 " %12:_(s32) = G_UBFX %3, %9(s32), %5\n"
1747 " %ubfx_copy_unk_off:_(s32) = COPY %12\n"
1748 " %13:_(s32) = G_UBFX %3, %4(s32), %10\n"
1749 " %ubfx_copy_unk_width:_(s32) = COPY %13\n";
1750 setUp(MIRString);
1751 if (!TM)
1752 return;
1753 Register CopyBfxReg = Copies[Copies.size() - 5];
1754 Register CopyValBfxReg = Copies[Copies.size() - 4];
1755 Register CopyUnkBfxReg = Copies[Copies.size() - 3];
1756 Register CopyUnkOffBfxReg = Copies[Copies.size() - 2];
1757 Register CopyUnkWidthBfxReg = Copies[Copies.size() - 1];
1758
1759 MachineInstr *CopyBfx = MRI->getVRegDef(CopyBfxReg);
1760 Register SrcReg = CopyBfx->getOperand(1).getReg();
1761 MachineInstr *CopyValBfx = MRI->getVRegDef(CopyValBfxReg);
1762 Register ValSrcReg = CopyValBfx->getOperand(1).getReg();
1763 MachineInstr *CopyUnkBfx = MRI->getVRegDef(CopyUnkBfxReg);
1764 Register UnkSrcReg = CopyUnkBfx->getOperand(1).getReg();
1765 MachineInstr *CopyUnkOffBfx = MRI->getVRegDef(CopyUnkOffBfxReg);
1766 Register UnkOffSrcReg = CopyUnkOffBfx->getOperand(1).getReg();
1767 MachineInstr *CopyUnkWidthBfx = MRI->getVRegDef(CopyUnkWidthBfxReg);
1768 Register UnkWidthSrcReg = CopyUnkWidthBfx->getOperand(1).getReg();
1769
1770 GISelKnownBits Info(*MF);
1771
1772 KnownBits Res1 = Info.getKnownBits(SrcReg);
1773 EXPECT_EQ(0u, Res1.One.getZExtValue());
1774 EXPECT_EQ(0xffffff00u, Res1.Zero.getZExtValue());
1775
1776 KnownBits Res2 = Info.getKnownBits(ValSrcReg);
1777 EXPECT_EQ(7u, Res2.One.getZExtValue());
1778 EXPECT_EQ(0xfffffff8u, Res2.Zero.getZExtValue());
1779
1780 KnownBits Res3 = Info.getKnownBits(UnkSrcReg);
1781 EXPECT_EQ(0u, Res3.One.getZExtValue());
1782 EXPECT_EQ(0u, Res3.Zero.getZExtValue());
1783
1784 KnownBits Res4 = Info.getKnownBits(UnkOffSrcReg);
1785 EXPECT_EQ(0u, Res4.One.getZExtValue());
1786 EXPECT_EQ(0xffffff00u, Res4.Zero.getZExtValue());
1787
1788 KnownBits Res5 = Info.getKnownBits(UnkWidthSrcReg);
1789 EXPECT_EQ(0u, Res5.One.getZExtValue());
1790 EXPECT_EQ(0xfff00000u, Res5.Zero.getZExtValue());
1791 }
1792
1793 TEST_F(AMDGPUGISelMITest, TestKnownBitsSBFX) {
1794 StringRef MIRString = " %3:_(s32) = G_IMPLICIT_DEF\n"
1795 " %4:_(s32) = G_CONSTANT i32 8\n"
1796 " %5:_(s32) = G_CONSTANT i32 4\n"
1797 " %6:_(s32) = G_SBFX %3, %4(s32), %5\n"
1798 " %sbfx_copy:_(s32) = COPY %6\n"
1799 " %7:_(s32) = G_CONSTANT i32 2047\n"
1800 " %8:_(s32) = G_SBFX %7, %4(s32), %5\n"
1801 " %sbfx_copy_val:_(s32) = COPY %8\n"
1802 " %9:_(s32) = G_CONSTANT i32 2048\n"
1803 " %10:_(s32) = G_SBFX %9, %4(s32), %5\n"
1804 " %sbfx_copy_neg_val:_(s32) = COPY %10\n"
1805 " %11:_(s32) = G_IMPLICIT_DEF\n"
1806 " %12:_(s32) = G_SBFX %7, %11(s32), %5\n"
1807 " %sbfx_copy_unk_off:_(s32) = COPY %12\n"
1808 " %13:_(s32) = G_SBFX %9, %4(s32), %11\n"
1809 " %sbfx_copy_unk_width:_(s32) = COPY %13\n";
1810 setUp(MIRString);
1811 if (!TM)
1812 return;
1813 Register CopyBfxReg = Copies[Copies.size() - 5];
1814 Register CopyValBfxReg = Copies[Copies.size() - 4];
1815 Register CopyNegValBfxReg = Copies[Copies.size() - 3];
1816 Register CopyUnkOffBfxReg = Copies[Copies.size() - 2];
1817 Register CopyUnkWidthBfxReg = Copies[Copies.size() - 1];
1818
1819 MachineInstr *CopyBfx = MRI->getVRegDef(CopyBfxReg);
1820 Register SrcReg = CopyBfx->getOperand(1).getReg();
1821 MachineInstr *CopyValBfx = MRI->getVRegDef(CopyValBfxReg);
1822 Register ValSrcReg = CopyValBfx->getOperand(1).getReg();
1823 MachineInstr *CopyNegValBfx = MRI->getVRegDef(CopyNegValBfxReg);
1824 Register NegValSrcReg = CopyNegValBfx->getOperand(1).getReg();
1825 MachineInstr *CopyUnkOffBfx = MRI->getVRegDef(CopyUnkOffBfxReg);
1826 Register UnkOffSrcReg = CopyUnkOffBfx->getOperand(1).getReg();
1827 MachineInstr *CopyUnkWidthBfx = MRI->getVRegDef(CopyUnkWidthBfxReg);
1828 Register UnkWidthSrcReg = CopyUnkWidthBfx->getOperand(1).getReg();
1829
1830 GISelKnownBits Info(*MF);
1831
1832 KnownBits Res1 = Info.getKnownBits(SrcReg);
1833 EXPECT_EQ(0u, Res1.One.getZExtValue());
1834 EXPECT_EQ(0u, Res1.Zero.getZExtValue());
1835
1836 KnownBits Res2 = Info.getKnownBits(ValSrcReg);
1837 EXPECT_EQ(7u, Res2.One.getZExtValue());
1838 EXPECT_EQ(0xfffffff8u, Res2.Zero.getZExtValue());
1839
1840 KnownBits Res3 = Info.getKnownBits(NegValSrcReg);
1841 EXPECT_EQ(0xfffffff8u, Res3.One.getZExtValue());
1842 EXPECT_EQ(7u, Res3.Zero.getZExtValue());
1843
1844 KnownBits Res4 = Info.getKnownBits(UnkOffSrcReg);
1845 EXPECT_EQ(0u, Res4.One.getZExtValue());
1846 EXPECT_EQ(0u, Res4.Zero.getZExtValue());
1847
1848 KnownBits Res5 = Info.getKnownBits(UnkWidthSrcReg);
1849 EXPECT_EQ(0u, Res5.One.getZExtValue());
1850 EXPECT_EQ(0u, Res5.Zero.getZExtValue());
1851 }
1852
1853 TEST_F(AMDGPUGISelMITest, TestNumSignBitsUBFX) {
1854 StringRef MIRString = " %3:_(s32) = G_IMPLICIT_DEF\n"
1855 " %4:_(s32) = G_CONSTANT i32 12\n"
1856 " %5:_(s32) = G_CONSTANT i32 8\n"
1857 " %6:_(s32) = G_UBFX %3, %4(s32), %5\n"
1858 " %ubfx_copy_unk:_(s32) = COPY %6\n"
1859 " %7:_(s32) = G_CONSTANT i32 28672\n"
1860 " %8:_(s32) = G_UBFX %7, %4(s32), %5\n"
1861 " %ubfx_copy_pos:_(s32) = COPY %8\n"
1862 " %9:_(s32) = G_CONSTANT i32 -1\n"
1863 " %10:_(s32) = G_UBFX %9, %4(s32), %5\n"
1864 " %ubfx_copy_neg:_(s32) = COPY %10\n"
1865 " %11:_(s32) = G_IMPLICIT_DEF\n"
1866 " %12:_(s32) = G_UBFX %7, %11(s32), %5\n"
1867 " %ubfx_copy_unk_off:_(s32) = COPY %12\n"
1868 " %13:_(s32) = G_UBFX %7, %4(s32), %11\n"
1869 " %ubfx_copy_unk_width:_(s32) = COPY %13\n";
1870 setUp(MIRString);
1871 if (!TM)
1872 return;
1873 Register CopyUnkBfxReg = Copies[Copies.size() - 5];
1874 Register CopyPosBfxReg = Copies[Copies.size() - 4];
1875 Register CopyNegBfxReg = Copies[Copies.size() - 3];
1876 Register CopyUnkOffBfxReg = Copies[Copies.size() - 2];
1877 Register CopyUnkWidthBfxReg = Copies[Copies.size() - 1];
1878
1879 GISelKnownBits Info(*MF);
1880 EXPECT_EQ(24u, Info.computeNumSignBits(CopyUnkBfxReg));
1881 EXPECT_EQ(29u, Info.computeNumSignBits(CopyPosBfxReg));
1882 EXPECT_EQ(24u, Info.computeNumSignBits(CopyNegBfxReg));
1883 EXPECT_EQ(24u, Info.computeNumSignBits(CopyUnkOffBfxReg));
1884 EXPECT_EQ(29u, Info.computeNumSignBits(CopyUnkWidthBfxReg));
1885 }
1886
1887 TEST_F(AMDGPUGISelMITest, TestNumSignBitsSBFX) {
1888 StringRef MIRString = " %3:_(s32) = G_CONSTANT i32 -1\n"
1889 " %4:_(s32) = G_CONSTANT i32 8\n"
1890 " %5:_(s32) = G_CONSTANT i32 4\n"
1891 " %6:_(s32) = G_SBFX %3, %4(s32), %5\n"
1892 " %sbfx_copy_neg:_(s32) = COPY %6\n"
1893 " %7:_(s32) = G_CONSTANT i32 2047\n"
1894 " %8:_(s32) = G_SBFX %7, %4(s32), %5\n"
1895 " %sbfx_copy_pos:_(s32) = COPY %8\n"
1896 " %9:_(s32) = G_CONSTANT i32 2048\n"
1897 " %10:_(s32) = G_SBFX %9, %4(s32), %5\n"
1898 " %sbfx_copy_hiset:_(s32) = COPY %10\n"
1899 " %11:_(s32) = G_IMPLICIT_DEF\n"
1900 " %12:_(s32) = G_SBFX %11, %4(s32), %5\n"
1901 " %sbfx_copy_unk:_(s32) = COPY %12\n"
1902 " %13:_(s32) = G_SBFX %3, %11(s32), %5\n"
1903 " %sbfx_copy_unk_off:_(s32) = COPY %13\n";
1904 setUp(MIRString);
1905 if (!TM)
1906 return;
1907 Register CopyNegBfxReg = Copies[Copies.size() - 5];
1908 Register CopyPosBfxReg = Copies[Copies.size() - 4];
1909 Register CopyHiSetBfxReg = Copies[Copies.size() - 3];
1910 Register CopyUnkValBfxReg = Copies[Copies.size() - 2];
1911 Register CopyUnkOffBfxReg = Copies[Copies.size() - 1];
1912
1913 GISelKnownBits Info(*MF);
1914 EXPECT_EQ(32u, Info.computeNumSignBits(CopyNegBfxReg));
1915 EXPECT_EQ(29u, Info.computeNumSignBits(CopyPosBfxReg));
1916 EXPECT_EQ(29u, Info.computeNumSignBits(CopyHiSetBfxReg));
1917 EXPECT_EQ(1u, Info.computeNumSignBits(CopyUnkValBfxReg));
1918 EXPECT_EQ(1u, Info.computeNumSignBits(CopyUnkOffBfxReg));
1919 }
1920
1921 TEST_F(AMDGPUGISelMITest, TestKnownBitsAssertAlign) {
1922 StringRef MIRString = R"MIR(
1923 %val:_(s64) = COPY $vgpr0_vgpr1
1924 %ptrval:_(p1) = COPY $vgpr0_vgpr1
1925
1926 %assert_align0:_(s64) = G_ASSERT_ALIGN %val, 0
1927 %copy_assert_align0:_(s64) = COPY %assert_align0
1928
1929 %assert_align1:_(s64) = G_ASSERT_ALIGN %val, 1
1930 %copy_assert_align1:_(s64) = COPY %assert_align1
1931
1932 %assert_align2:_(s64) = G_ASSERT_ALIGN %val, 2
1933 %copy_assert_align2:_(s64) = COPY %assert_align2
1934
1935 %assert_align3:_(s64) = G_ASSERT_ALIGN %val, 3
1936 %copy_assert_align3:_(s64) = COPY %assert_align3
1937
1938 %assert_align8:_(s64) = G_ASSERT_ALIGN %val, 8
1939 %copy_assert_align8:_(s64) = COPY %assert_align8
1940
1941 %assert_maxalign:_(s64) = G_ASSERT_ALIGN %val, 30
1942 %copy_assert_maxalign:_(s64) = COPY %assert_maxalign
1943
1944 %assert_ptr_align5:_(p1) = G_ASSERT_ALIGN %ptrval, 5
1945 %copy_assert_ptr_align5:_(p1) = COPY %assert_ptr_align5
1946 )MIR";
1947 setUp(MIRString);
1948 if (!TM)
1949 return;
1950 GISelKnownBits Info(*MF);
1951
1952 KnownBits Res;
1953 auto GetKB = [&](unsigned Idx) {
1954 Register CopyReg = Copies[Idx];
1955 auto *Copy = MRI->getVRegDef(CopyReg);
1956 return Info.getKnownBits(Copy->getOperand(1).getReg());
1957 };
1958
1959 auto CheckBits = [&](unsigned NumBits, unsigned Idx) {
1960 Res = GetKB(Idx);
1961 EXPECT_EQ(64u, Res.getBitWidth());
1962 EXPECT_EQ(NumBits, Res.Zero.countTrailingOnes());
1963 EXPECT_EQ(64u, Res.One.countTrailingZeros());
1964 EXPECT_EQ(Align(1ull << NumBits), Info.computeKnownAlignment(Copies[Idx]));
1965 };
1966
1967 CheckBits(0, Copies.size() - 7);
1968 CheckBits(1, Copies.size() - 6);
1969 CheckBits(2, Copies.size() - 5);
1970 CheckBits(3, Copies.size() - 4);
1971 CheckBits(8, Copies.size() - 3);
1972 CheckBits(30, Copies.size() - 2);
1973 CheckBits(5, Copies.size() - 1);
1974 }
1975
1976 TEST_F(AArch64GISelMITest, TestKnownBitsUADDO) {
1977 StringRef MIRString = R"(
1978 %ptr:_(p0) = G_IMPLICIT_DEF
1979 %ld0:_(s32) = G_LOAD %ptr(p0) :: (load (s16))
1980 %ld1:_(s32) = G_LOAD %ptr(p0) :: (load (s16))
1981
1982 %add:_(s32), %overflow:_(s32) = G_UADDO %ld0, %ld1
1983 %copy_overflow:_(s32) = COPY %overflow
1984 )";
1985
1986 setUp(MIRString);
1987 if (!TM)
1988 return;
1989
1990 Register CopyOverflow = Copies[Copies.size() - 1];
1991 GISelKnownBits Info(*MF);
1992 KnownBits Res = Info.getKnownBits(CopyOverflow);
1993 EXPECT_EQ(0u, Res.One.getZExtValue());
1994 EXPECT_EQ(31u, Res.Zero.countLeadingOnes());
1995 }
LLVM monorepo