llvm/lib/Target/X86/X86SchedSkylakeClient.td

   1 //=- X86SchedSkylake.td - X86 Skylake Client Scheduling ------*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the machine model for Skylake Client to support
  10 // instruction scheduling and other instruction cost heuristics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 def SkylakeClientModel : SchedMachineModel {
  15   // All x86 instructions are modeled as a single micro-op, and SKylake can
  16   // decode 6 instructions per cycle.
  17   let IssueWidth = 6;
  18   let MicroOpBufferSize = 224; // Based on the reorder buffer.
  19   let LoadLatency = 5;
  20   let MispredictPenalty = 14;
  21
  22   // Based on the LSD (loop-stream detector) queue size and benchmarking data.
  23   let LoopMicroOpBufferSize = 50;
  24
  25   // This flag is set to allow the scheduler to assign a default model to
  26   // unrecognized opcodes.
  27   let CompleteModel = 0;
  28 }
  29
  30 let SchedModel = SkylakeClientModel in {
  31
  32 // Skylake Client can issue micro-ops to 8 different ports in one cycle.
  33
  34 // Ports 0, 1, 5, and 6 handle all computation.
  35 // Port 4 gets the data half of stores. Store data can be available later than
  36 // the store address, but since we don't model the latency of stores, we can
  37 // ignore that.
  38 // Ports 2 and 3 are identical. They handle loads and the address half of
  39 // stores. Port 7 can handle address calculations.
  40 def SKLPort0 : ProcResource<1>;
  41 def SKLPort1 : ProcResource<1>;
  42 def SKLPort2 : ProcResource<1>;
  43 def SKLPort3 : ProcResource<1>;
  44 def SKLPort4 : ProcResource<1>;
  45 def SKLPort5 : ProcResource<1>;
  46 def SKLPort6 : ProcResource<1>;
  47 def SKLPort7 : ProcResource<1>;
  48
  49 // Many micro-ops are capable of issuing on multiple ports.
  50 def SKLPort01  : ProcResGroup<[SKLPort0, SKLPort1]>;
  51 def SKLPort23  : ProcResGroup<[SKLPort2, SKLPort3]>;
  52 def SKLPort237 : ProcResGroup<[SKLPort2, SKLPort3, SKLPort7]>;
  53 def SKLPort04  : ProcResGroup<[SKLPort0, SKLPort4]>;
  54 def SKLPort05  : ProcResGroup<[SKLPort0, SKLPort5]>;
  55 def SKLPort06  : ProcResGroup<[SKLPort0, SKLPort6]>;
  56 def SKLPort15  : ProcResGroup<[SKLPort1, SKLPort5]>;
  57 def SKLPort16  : ProcResGroup<[SKLPort1, SKLPort6]>;
  58 def SKLPort56  : ProcResGroup<[SKLPort5, SKLPort6]>;
  59 def SKLPort015 : ProcResGroup<[SKLPort0, SKLPort1, SKLPort5]>;
  60 def SKLPort056 : ProcResGroup<[SKLPort0, SKLPort5, SKLPort6]>;
  61 def SKLPort0156: ProcResGroup<[SKLPort0, SKLPort1, SKLPort5, SKLPort6]>;
  62
  63 def SKLDivider : ProcResource<1>; // Integer division issued on port 0.
  64 // FP division and sqrt on port 0.
  65 def SKLFPDivider : ProcResource<1>;
  66
  67 // 60 Entry Unified Scheduler
  68 def SKLPortAny : ProcResGroup<[SKLPort0, SKLPort1, SKLPort2, SKLPort3, SKLPort4,
  69                               SKLPort5, SKLPort6, SKLPort7]> {
  70   let BufferSize=60;
  71 }
  72
  73 // Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
  74 // cycles after the memory operand.
  75 def : ReadAdvance<ReadAfterLd, 5>;
  76
  77 // Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available
  78 // until 5/6/7 cycles after the memory operand.
  79 def : ReadAdvance<ReadAfterVecLd, 5>;
  80 def : ReadAdvance<ReadAfterVecXLd, 6>;
  81 def : ReadAdvance<ReadAfterVecYLd, 7>;
  82
  83 def : ReadAdvance<ReadInt2Fpu, 0>;
  84
  85 // Many SchedWrites are defined in pairs with and without a folded load.
  86 // Instructions with folded loads are usually micro-fused, so they only appear
  87 // as two micro-ops when queued in the reservation station.
  88 // This multiclass defines the resource usage for variants with and without
  89 // folded loads.
  90 multiclass SKLWriteResPair<X86FoldableSchedWrite SchedRW,
  91                           list<ProcResourceKind> ExePorts,
  92                           int Lat, list<int> Res = [1], int UOps = 1,
  93                           int LoadLat = 5, int LoadUOps = 1> {
  94   // Register variant is using a single cycle on ExePort.
  95   def : WriteRes<SchedRW, ExePorts> {
  96     let Latency = Lat;
  97     let ReleaseAtCycles = Res;
  98     let NumMicroOps = UOps;
  99   }
 100
 101   // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
 102   // the latency (default = 5).
 103   def : WriteRes<SchedRW.Folded, !listconcat([SKLPort23], ExePorts)> {
 104     let Latency = !add(Lat, LoadLat);
 105     let ReleaseAtCycles = !listconcat([1], Res);
 106     let NumMicroOps = !add(UOps, LoadUOps);
 107   }
 108 }
 109
 110 // A folded store needs a cycle on port 4 for the store data, and an extra port
 111 // 2/3/7 cycle to recompute the address.
 112 def : WriteRes<WriteRMW, [SKLPort237,SKLPort4]>;
 113
 114 // Arithmetic.
 115 defm : SKLWriteResPair<WriteALU,    [SKLPort0156], 1>; // Simple integer ALU op.
 116 defm : SKLWriteResPair<WriteADC,    [SKLPort06],   1>; // Integer ALU + flags op.
 117
 118 // Integer multiplication.
 119 defm : SKLWriteResPair<WriteIMul8,     [SKLPort1],   3>;
 120 defm : SKLWriteResPair<WriteIMul16,    [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,2], 4>;
 121 defm : X86WriteRes<WriteIMul16Imm,     [SKLPort1,SKLPort0156], 4, [1,1], 2>;
 122 defm : X86WriteRes<WriteIMul16ImmLd,   [SKLPort1,SKLPort0156,SKLPort23], 8, [1,1,1], 3>;
 123 defm : SKLWriteResPair<WriteIMul16Reg, [SKLPort1],   3>;
 124 defm : SKLWriteResPair<WriteIMul32,    [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,1], 3>;
 125 defm : SKLWriteResPair<WriteMULX32,    [SKLPort1,SKLPort06,SKLPort0156], 3, [1,1,1], 3>;
 126 defm : SKLWriteResPair<WriteIMul32Imm, [SKLPort1],   3>;
 127 defm : SKLWriteResPair<WriteIMul32Reg, [SKLPort1],   3>;
 128 defm : SKLWriteResPair<WriteIMul64,    [SKLPort1,SKLPort5], 4, [1,1], 2>;
 129 defm : SKLWriteResPair<WriteMULX64,    [SKLPort1,SKLPort5], 3, [1,1], 2>;
 130 defm : SKLWriteResPair<WriteIMul64Imm, [SKLPort1],   3>;
 131 defm : SKLWriteResPair<WriteIMul64Reg, [SKLPort1],   3>;
 132 def SKLWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; }
 133 def  : WriteRes<WriteIMulHLd, []> {
 134   let Latency = !add(SKLWriteIMulH.Latency, SkylakeClientModel.LoadLatency);
 135 }
 136
 137 defm : X86WriteRes<WriteBSWAP32,    [SKLPort15], 1, [1], 1>;
 138 defm : X86WriteRes<WriteBSWAP64,    [SKLPort06, SKLPort15], 2, [1,1], 2>;
 139 defm : X86WriteRes<WriteCMPXCHG,[SKLPort06, SKLPort0156], 5, [2,3], 5>;
 140 defm : X86WriteRes<WriteCMPXCHGRMW,[SKLPort23,SKLPort06,SKLPort0156,SKLPort237,SKLPort4], 8, [1,2,1,1,1], 6>;
 141 defm : X86WriteRes<WriteXCHG, [SKLPort0156], 2, [3], 3>;
 142
 143 // TODO: Why isn't the SKLDivider used?
 144 defm : SKLWriteResPair<WriteDiv8,   [SKLPort0,SKLDivider], 25, [1,10], 1, 4>;
 145 defm : X86WriteRes<WriteDiv16,      [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>;
 146 defm : X86WriteRes<WriteDiv32,      [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>;
 147 defm : X86WriteRes<WriteDiv64,      [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>;
 148 defm : X86WriteRes<WriteDiv16Ld,    [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>;
 149 defm : X86WriteRes<WriteDiv32Ld,    [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>;
 150 defm : X86WriteRes<WriteDiv64Ld,    [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>;
 151
 152 defm : X86WriteRes<WriteIDiv8,    [SKLPort0,SKLDivider], 25, [1,10], 1>;
 153 defm : X86WriteRes<WriteIDiv16,   [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>;
 154 defm : X86WriteRes<WriteIDiv32,   [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>;
 155 defm : X86WriteRes<WriteIDiv64,   [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>;
 156 defm : X86WriteRes<WriteIDiv8Ld,  [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;
 157 defm : X86WriteRes<WriteIDiv16Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;
 158 defm : X86WriteRes<WriteIDiv32Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;
 159 defm : X86WriteRes<WriteIDiv64Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;
 160
 161 defm : SKLWriteResPair<WriteCRC32, [SKLPort1], 3>;
 162
 163 def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads.
 164
 165 defm : SKLWriteResPair<WriteCMOV,  [SKLPort06], 1, [1], 1>; // Conditional move.
 166 defm : X86WriteRes<WriteFCMOV, [SKLPort1], 3, [1], 1>; // x87 conditional move.
 167 def  : WriteRes<WriteSETCC, [SKLPort06]>; // Setcc.
 168 def  : WriteRes<WriteSETCCStore, [SKLPort06,SKLPort4,SKLPort237]> {
 169   let Latency = 2;
 170   let NumMicroOps = 3;
 171 }
 172
 173 defm : X86WriteRes<WriteLAHFSAHF,        [SKLPort06], 1, [1], 1>;
 174 defm : X86WriteRes<WriteBitTest,         [SKLPort06], 1, [1], 1>;
 175 defm : X86WriteRes<WriteBitTestImmLd,    [SKLPort06,SKLPort23], 6, [1,1], 2>;
 176 defm : X86WriteRes<WriteBitTestRegLd,    [SKLPort0156,SKLPort23], 6, [1,1], 2>;
 177 defm : X86WriteRes<WriteBitTestSet,      [SKLPort06], 1, [1], 1>;
 178 defm : X86WriteRes<WriteBitTestSetImmLd, [SKLPort06,SKLPort23], 5, [1,1], 3>;
 179 defm : X86WriteRes<WriteBitTestSetRegLd, [SKLPort0156,SKLPort23], 5, [1,1], 2>;
 180
 181 // Bit counts.
 182 defm : SKLWriteResPair<WriteBSF, [SKLPort1], 3>;
 183 defm : SKLWriteResPair<WriteBSR, [SKLPort1], 3>;
 184 defm : SKLWriteResPair<WriteLZCNT,          [SKLPort1], 3>;
 185 defm : SKLWriteResPair<WriteTZCNT,          [SKLPort1], 3>;
 186 defm : SKLWriteResPair<WritePOPCNT,         [SKLPort1], 3>;
 187
 188 // Integer shifts and rotates.
 189 defm : SKLWriteResPair<WriteShift,    [SKLPort06],  1>;
 190 defm : SKLWriteResPair<WriteShiftCL,  [SKLPort06],  3, [3], 3>;
 191 defm : SKLWriteResPair<WriteRotate,   [SKLPort06],  1, [1], 1>;
 192 defm : SKLWriteResPair<WriteRotateCL, [SKLPort06],  3, [3], 3>;
 193
 194 // SHLD/SHRD.
 195 defm : X86WriteRes<WriteSHDrri, [SKLPort1], 3, [1], 1>;
 196 defm : X86WriteRes<WriteSHDrrcl,[SKLPort1,SKLPort06,SKLPort0156], 6, [1, 2, 1], 4>;
 197 defm : X86WriteRes<WriteSHDmri, [SKLPort1,SKLPort23,SKLPort237,SKLPort0156], 9, [1, 1, 1, 1], 4>;
 198 defm : X86WriteRes<WriteSHDmrcl,[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort0156], 11, [1, 1, 1, 2, 1], 6>;
 199
 200 // BMI1 BEXTR/BLS, BMI2 BZHI
 201 defm : SKLWriteResPair<WriteBEXTR, [SKLPort06,SKLPort15], 2, [1,1], 2>;
 202 defm : SKLWriteResPair<WriteBLS,   [SKLPort15], 1>;
 203 defm : SKLWriteResPair<WriteBZHI,  [SKLPort15], 1>;
 204
 205 // Loads, stores, and moves, not folded with other operations.
 206 defm : X86WriteRes<WriteLoad,    [SKLPort23], 5, [1], 1>;
 207 defm : X86WriteRes<WriteStore,   [SKLPort237, SKLPort4], 1, [1,1], 1>;
 208 defm : X86WriteRes<WriteStoreNT, [SKLPort237, SKLPort4], 1, [1,1], 2>;
 209 defm : X86WriteRes<WriteMove,    [SKLPort0156], 1, [1], 1>;
 210
 211 // Model the effect of clobbering the read-write mask operand of the GATHER operation.
 212 // Does not cost anything by itself, only has latency, matching that of the WriteLoad,
 213 defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>;
 214
 215 // Idioms that clear a register, like xorps %xmm0, %xmm0.
 216 // These can often bypass execution ports completely.
 217 def : WriteRes<WriteZero,  []>;
 218
 219 // Branches don't produce values, so they have no latency, but they still
 220 // consume resources. Indirect branches can fold loads.
 221 defm : SKLWriteResPair<WriteJump,  [SKLPort06],   1>;
 222
 223 // Floating point. This covers both scalar and vector operations.
 224 defm : X86WriteRes<WriteFLD0,          [SKLPort05], 1, [1], 1>;
 225 defm : X86WriteRes<WriteFLD1,          [SKLPort05], 1, [2], 2>;
 226 defm : X86WriteRes<WriteFLDC,          [SKLPort05], 1, [2], 2>;
 227 defm : X86WriteRes<WriteFLoad,         [SKLPort23], 5, [1], 1>;
 228 defm : X86WriteRes<WriteFLoadX,        [SKLPort23], 6, [1], 1>;
 229 defm : X86WriteRes<WriteFLoadY,        [SKLPort23], 7, [1], 1>;
 230 defm : X86WriteRes<WriteFMaskedLoad,   [SKLPort23,SKLPort015], 7, [1,1], 2>;
 231 defm : X86WriteRes<WriteFMaskedLoadY,  [SKLPort23,SKLPort015], 8, [1,1], 2>;
 232 defm : X86WriteRes<WriteFStore,        [SKLPort237,SKLPort4], 1, [1,1], 2>;
 233 defm : X86WriteRes<WriteFStoreX,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
 234 defm : X86WriteRes<WriteFStoreY,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
 235 defm : X86WriteRes<WriteFStoreNT,      [SKLPort237,SKLPort4], 1, [1,1], 2>;
 236 defm : X86WriteRes<WriteFStoreNTX,     [SKLPort237,SKLPort4], 1, [1,1], 2>;
 237 defm : X86WriteRes<WriteFStoreNTY,     [SKLPort237,SKLPort4], 1, [1,1], 2>;
 238
 239 defm : X86WriteRes<WriteFMaskedStore32,  [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>;
 240 defm : X86WriteRes<WriteFMaskedStore32Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>;
 241 defm : X86WriteRes<WriteFMaskedStore64,  [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>;
 242 defm : X86WriteRes<WriteFMaskedStore64Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>;
 243
 244 defm : X86WriteRes<WriteFMove,         [SKLPort015], 1, [1], 1>;
 245 defm : X86WriteRes<WriteFMoveX,        [SKLPort015], 1, [1], 1>;
 246 defm : X86WriteRes<WriteFMoveY,        [SKLPort015], 1, [1], 1>;
 247 defm : X86WriteResUnsupported<WriteFMoveZ>;
 248 defm : X86WriteRes<WriteEMMS,          [SKLPort05,SKLPort0156], 10, [9,1], 10>;
 249
 250 defm : SKLWriteResPair<WriteFAdd,     [SKLPort01],  4, [1], 1, 5>; // Floating point add/sub.
 251 defm : SKLWriteResPair<WriteFAddX,    [SKLPort01],  4, [1], 1, 6>;
 252 defm : SKLWriteResPair<WriteFAddY,    [SKLPort01],  4, [1], 1, 7>;
 253 defm : X86WriteResPairUnsupported<WriteFAddZ>;
 254 defm : SKLWriteResPair<WriteFAdd64,   [SKLPort01],  4, [1], 1, 5>; // Floating point double add/sub.
 255 defm : SKLWriteResPair<WriteFAdd64X,  [SKLPort01],  4, [1], 1, 6>;
 256 defm : SKLWriteResPair<WriteFAdd64Y,  [SKLPort01],  4, [1], 1, 7>;
 257 defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
 258
 259 defm : SKLWriteResPair<WriteFCmp,     [SKLPort01],  4, [1], 1, 5>; // Floating point compare.
 260 defm : SKLWriteResPair<WriteFCmpX,    [SKLPort01],  4, [1], 1, 6>;
 261 defm : SKLWriteResPair<WriteFCmpY,    [SKLPort01],  4, [1], 1, 7>;
 262 defm : X86WriteResPairUnsupported<WriteFCmpZ>;
 263 defm : SKLWriteResPair<WriteFCmp64,   [SKLPort01],  4, [1], 1, 5>; // Floating point double compare.
 264 defm : SKLWriteResPair<WriteFCmp64X,  [SKLPort01],  4, [1], 1, 6>;
 265 defm : SKLWriteResPair<WriteFCmp64Y,  [SKLPort01],  4, [1], 1, 7>;
 266 defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
 267
 268 defm : SKLWriteResPair<WriteFCom,      [SKLPort0],  2>; // Floating point compare to flags (X87).
 269 defm : SKLWriteResPair<WriteFComX,     [SKLPort0],  2>; // Floating point compare to flags (SSE).
 270
 271 defm : SKLWriteResPair<WriteFMul,     [SKLPort01],  4, [1], 1, 5>; // Floating point multiplication.
 272 defm : SKLWriteResPair<WriteFMulX,    [SKLPort01],  4, [1], 1, 6>;
 273 defm : SKLWriteResPair<WriteFMulY,    [SKLPort01],  4, [1], 1, 7>;
 274 defm : X86WriteResPairUnsupported<WriteFMulZ>;
 275 defm : SKLWriteResPair<WriteFMul64,   [SKLPort01],  4, [1], 1, 5>; // Floating point double multiplication.
 276 defm : SKLWriteResPair<WriteFMul64X,  [SKLPort01],  4, [1], 1, 6>;
 277 defm : SKLWriteResPair<WriteFMul64Y,  [SKLPort01],  4, [1], 1, 7>;
 278 defm : X86WriteResPairUnsupported<WriteFMul64Z>;
 279
 280 defm : SKLWriteResPair<WriteFDiv,     [SKLPort0,SKLFPDivider], 11, [1,3], 1, 5>; // Floating point division.
 281 defm : SKLWriteResPair<WriteFDivX,    [SKLPort0,SKLFPDivider], 11, [1,3], 1, 6>;
 282 defm : SKLWriteResPair<WriteFDivY,    [SKLPort0,SKLFPDivider], 11, [1,5], 1, 7>;
 283 defm : X86WriteResPairUnsupported<WriteFDivZ>;
 284 defm : SKLWriteResPair<WriteFDiv64,   [SKLPort0,SKLFPDivider], 14, [1,4], 1, 5>; // Floating point double division.
 285 defm : SKLWriteResPair<WriteFDiv64X,  [SKLPort0,SKLFPDivider], 14, [1,4], 1, 6>;
 286 defm : SKLWriteResPair<WriteFDiv64Y,  [SKLPort0,SKLFPDivider], 14, [1,8], 1, 7>;
 287 defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
 288
 289 defm : SKLWriteResPair<WriteFSqrt,    [SKLPort0,SKLFPDivider], 12, [1,3], 1, 5>; // Floating point square root.
 290 defm : SKLWriteResPair<WriteFSqrtX,   [SKLPort0,SKLFPDivider], 12, [1,3], 1, 6>;
 291 defm : SKLWriteResPair<WriteFSqrtY,   [SKLPort0,SKLFPDivider], 12, [1,6], 1, 7>;
 292 defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
 293 defm : SKLWriteResPair<WriteFSqrt64,  [SKLPort0,SKLFPDivider], 18, [1,6], 1, 5>; // Floating point double square root.
 294 defm : SKLWriteResPair<WriteFSqrt64X, [SKLPort0,SKLFPDivider], 18, [1,6], 1, 6>;
 295 defm : SKLWriteResPair<WriteFSqrt64Y, [SKLPort0,SKLFPDivider], 18, [1,12],1, 7>;
 296 defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
 297 defm : SKLWriteResPair<WriteFSqrt80,  [SKLPort0,SKLFPDivider], 21, [1,7]>; // Floating point long double square root.
 298
 299 defm : SKLWriteResPair<WriteFRcp,   [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate.
 300 defm : SKLWriteResPair<WriteFRcpX,  [SKLPort0], 4, [1], 1, 6>;
 301 defm : SKLWriteResPair<WriteFRcpY,  [SKLPort0], 4, [1], 1, 7>;
 302 defm : X86WriteResPairUnsupported<WriteFRcpZ>;
 303
 304 defm : SKLWriteResPair<WriteFRsqrt, [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate.
 305 defm : SKLWriteResPair<WriteFRsqrtX,[SKLPort0], 4, [1], 1, 6>;
 306 defm : SKLWriteResPair<WriteFRsqrtY,[SKLPort0], 4, [1], 1, 7>;
 307 defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
 308
 309 defm : SKLWriteResPair<WriteFMA,    [SKLPort01], 4, [1], 1, 5>; // Fused Multiply Add.
 310 defm : SKLWriteResPair<WriteFMAX,   [SKLPort01], 4, [1], 1, 6>;
 311 defm : SKLWriteResPair<WriteFMAY,   [SKLPort01], 4, [1], 1, 7>;
 312 defm : X86WriteResPairUnsupported<WriteFMAZ>;
 313 defm : SKLWriteResPair<WriteDPPD,   [SKLPort5,SKLPort01],  9, [1,2], 3, 6>; // Floating point double dot product.
 314 defm : SKLWriteResPair<WriteDPPS,   [SKLPort5,SKLPort01], 13, [1,3], 4, 6>;
 315 defm : SKLWriteResPair<WriteDPPSY,  [SKLPort5,SKLPort01], 13, [1,3], 4, 7>;
 316 defm : SKLWriteResPair<WriteFSign,   [SKLPort0], 1>; // Floating point fabs/fchs.
 317 defm : SKLWriteResPair<WriteFRnd,     [SKLPort01], 8, [2], 2, 6>; // Floating point rounding.
 318 defm : SKLWriteResPair<WriteFRndY,    [SKLPort01], 8, [2], 2, 7>;
 319 defm : X86WriteResPairUnsupported<WriteFRndZ>;
 320 defm : SKLWriteResPair<WriteFLogic,  [SKLPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals.
 321 defm : SKLWriteResPair<WriteFLogicY, [SKLPort015], 1, [1], 1, 7>;
 322 defm : X86WriteResPairUnsupported<WriteFLogicZ>;
 323 defm : SKLWriteResPair<WriteFTest,   [SKLPort0], 2, [1], 1, 6>; // Floating point TEST instructions.
 324 defm : SKLWriteResPair<WriteFTestY,  [SKLPort0], 2, [1], 1, 7>;
 325 defm : X86WriteResPairUnsupported<WriteFTestZ>;
 326 defm : SKLWriteResPair<WriteFShuffle,  [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
 327 defm : SKLWriteResPair<WriteFShuffleY, [SKLPort5], 1, [1], 1, 7>;
 328 defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
 329 defm : SKLWriteResPair<WriteFVarShuffle,  [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
 330 defm : SKLWriteResPair<WriteFVarShuffleY, [SKLPort5], 1, [1], 1, 7>;
 331 defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
 332 defm : SKLWriteResPair<WriteFBlend,  [SKLPort015], 1, [1], 1, 6>; // Floating point vector blends.
 333 defm : SKLWriteResPair<WriteFBlendY, [SKLPort015], 1, [1], 1, 7>;
 334 defm : X86WriteResPairUnsupported<WriteFBlendZ>;
 335 defm : SKLWriteResPair<WriteFVarBlend, [SKLPort015], 2, [2], 2, 6>; // Fp vector variable blends.
 336 defm : SKLWriteResPair<WriteFVarBlendY,[SKLPort015], 2, [2], 2, 7>;
 337 defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
 338
 339 // FMA Scheduling helper class.
 340 // class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
 341
 342 // Vector integer operations.
 343 defm : X86WriteRes<WriteVecLoad,         [SKLPort23], 5, [1], 1>;
 344 defm : X86WriteRes<WriteVecLoadX,        [SKLPort23], 6, [1], 1>;
 345 defm : X86WriteRes<WriteVecLoadY,        [SKLPort23], 7, [1], 1>;
 346 defm : X86WriteRes<WriteVecLoadNT,       [SKLPort23], 6, [1], 1>;
 347 defm : X86WriteRes<WriteVecLoadNTY,      [SKLPort23], 7, [1], 1>;
 348 defm : X86WriteRes<WriteVecMaskedLoad,   [SKLPort23,SKLPort015], 7, [1,1], 2>;
 349 defm : X86WriteRes<WriteVecMaskedLoadY,  [SKLPort23,SKLPort015], 8, [1,1], 2>;
 350 defm : X86WriteRes<WriteVecStore,        [SKLPort237,SKLPort4], 1, [1,1], 2>;
 351 defm : X86WriteRes<WriteVecStoreX,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
 352 defm : X86WriteRes<WriteVecStoreY,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
 353 defm : X86WriteRes<WriteVecStoreNT,      [SKLPort237,SKLPort4], 1, [1,1], 2>;
 354 defm : X86WriteRes<WriteVecStoreNTY,     [SKLPort237,SKLPort4], 1, [1,1], 2>;
 355 defm : X86WriteRes<WriteVecMaskedStore32,  [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>;
 356 defm : X86WriteRes<WriteVecMaskedStore32Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>;
 357 defm : X86WriteRes<WriteVecMaskedStore64,  [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>;
 358 defm : X86WriteRes<WriteVecMaskedStore64Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>;
 359 defm : X86WriteRes<WriteVecMove,         [SKLPort05],  1, [1], 1>;
 360 defm : X86WriteRes<WriteVecMoveX,        [SKLPort015], 1, [1], 1>;
 361 defm : X86WriteRes<WriteVecMoveY,        [SKLPort015], 1, [1], 1>;
 362 defm : X86WriteResUnsupported<WriteVecMoveZ>;
 363 defm : X86WriteRes<WriteVecMoveToGpr,    [SKLPort0], 2, [1], 1>;
 364 defm : X86WriteRes<WriteVecMoveFromGpr,  [SKLPort5], 1, [1], 1>;
 365
 366 defm : SKLWriteResPair<WriteVecALU,   [SKLPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
 367 defm : SKLWriteResPair<WriteVecALUX,  [SKLPort01], 1, [1], 1, 6>;
 368 defm : SKLWriteResPair<WriteVecALUY,  [SKLPort01], 1, [1], 1, 7>;
 369 defm : X86WriteResPairUnsupported<WriteVecALUZ>;
 370 defm : SKLWriteResPair<WriteVecLogic, [SKLPort05],  1, [1], 1, 5>; // Vector integer and/or/xor.
 371 defm : SKLWriteResPair<WriteVecLogicX,[SKLPort015], 1, [1], 1, 6>;
 372 defm : SKLWriteResPair<WriteVecLogicY,[SKLPort015], 1, [1], 1, 7>;
 373 defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
 374 defm : SKLWriteResPair<WriteVecTest,  [SKLPort0,SKLPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions.
 375 defm : SKLWriteResPair<WriteVecTestY, [SKLPort0,SKLPort5], 3, [1,1], 2, 7>;
 376 defm : X86WriteResPairUnsupported<WriteVecTestZ>;
 377 defm : SKLWriteResPair<WriteVecIMul,  [SKLPort0] ,  5, [1], 1, 5>; // Vector integer multiply.
 378 defm : SKLWriteResPair<WriteVecIMulX, [SKLPort01],  5, [1], 1, 6>;
 379 defm : SKLWriteResPair<WriteVecIMulY, [SKLPort01],  5, [1], 1, 7>;
 380 defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
 381 defm : SKLWriteResPair<WritePMULLD,   [SKLPort01], 10, [2], 2, 6>; // Vector PMULLD.
 382 defm : SKLWriteResPair<WritePMULLDY,  [SKLPort01], 10, [2], 2, 7>;
 383 defm : X86WriteResPairUnsupported<WritePMULLDZ>;
 384 defm : SKLWriteResPair<WriteShuffle,  [SKLPort5], 1, [1], 1, 5>; // Vector shuffles.
 385 defm : SKLWriteResPair<WriteShuffleX, [SKLPort5], 1, [1], 1, 6>;
 386 defm : SKLWriteResPair<WriteShuffleY, [SKLPort5], 1, [1], 1, 7>;
 387 defm : X86WriteResPairUnsupported<WriteShuffleZ>;
 388 defm : SKLWriteResPair<WriteVarShuffle,  [SKLPort5], 1, [1], 1, 5>; // Vector shuffles.
 389 defm : SKLWriteResPair<WriteVarShuffleX, [SKLPort5], 1, [1], 1, 6>;
 390 defm : SKLWriteResPair<WriteVarShuffleY, [SKLPort5], 1, [1], 1, 7>;
 391 defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
 392 defm : SKLWriteResPair<WriteBlend,  [SKLPort5], 1, [1], 1, 6>; // Vector blends.
 393 defm : SKLWriteResPair<WriteBlendY, [SKLPort5], 1, [1], 1, 7>;
 394 defm : X86WriteResPairUnsupported<WriteBlendZ>;
 395 defm : SKLWriteResPair<WriteVarBlend,  [SKLPort015], 2, [2], 2, 6>; // Vector variable blends.
 396 defm : SKLWriteResPair<WriteVarBlendY, [SKLPort015], 2, [2], 2, 6>;
 397 defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
 398 defm : SKLWriteResPair<WriteMPSAD,  [SKLPort5], 4, [2], 2, 6>; // Vector MPSAD.
 399 defm : SKLWriteResPair<WriteMPSADY, [SKLPort5], 4, [2], 2, 7>;
 400 defm : X86WriteResPairUnsupported<WriteMPSADZ>;
 401 defm : SKLWriteResPair<WritePSADBW,  [SKLPort5], 3, [1], 1, 5>; // Vector PSADBW.
 402 defm : SKLWriteResPair<WritePSADBWX, [SKLPort5], 3, [1], 1, 6>;
 403 defm : SKLWriteResPair<WritePSADBWY, [SKLPort5], 3, [1], 1, 7>;
 404 defm : X86WriteResPairUnsupported<WritePSADBWZ>;
 405 defm : SKLWriteResPair<WritePHMINPOS, [SKLPort01], 4, [1], 1, 6>; // Vector PHMINPOS.
 406
 407 // Vector integer shifts.
 408 defm : SKLWriteResPair<WriteVecShift,     [SKLPort0], 1, [1], 1, 5>;
 409 defm : X86WriteRes<WriteVecShiftX,        [SKLPort5,SKLPort01],  2, [1,1], 2>;
 410 defm : X86WriteRes<WriteVecShiftY,        [SKLPort5,SKLPort01],  4, [1,1], 2>;
 411 defm : X86WriteRes<WriteVecShiftXLd,      [SKLPort01,SKLPort23], 7, [1,1], 2>;
 412 defm : X86WriteRes<WriteVecShiftYLd,      [SKLPort01,SKLPort23], 8, [1,1], 2>;
 413 defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
 414
 415 defm : SKLWriteResPair<WriteVecShiftImm,  [SKLPort0],  1, [1], 1, 5>; // Vector integer immediate shifts.
 416 defm : SKLWriteResPair<WriteVecShiftImmX, [SKLPort01], 1, [1], 1, 6>;
 417 defm : SKLWriteResPair<WriteVecShiftImmY, [SKLPort01], 1, [1], 1, 7>;
 418 defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
 419 defm : SKLWriteResPair<WriteVarVecShift,  [SKLPort01], 1, [1], 1, 6>; // Variable vector shifts.
 420 defm : SKLWriteResPair<WriteVarVecShiftY, [SKLPort01], 1, [1], 1, 7>;
 421 defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
 422
 423 // Vector insert/extract operations.
 424 def : WriteRes<WriteVecInsert, [SKLPort5]> {
 425   let Latency = 2;
 426   let NumMicroOps = 2;
 427   let ReleaseAtCycles = [2];
 428 }
 429 def : WriteRes<WriteVecInsertLd, [SKLPort5,SKLPort23]> {
 430   let Latency = 6;
 431   let NumMicroOps = 2;
 432 }
 433 def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;
 434
 435 def : WriteRes<WriteVecExtract, [SKLPort0,SKLPort5]> {
 436   let Latency = 3;
 437   let NumMicroOps = 2;
 438 }
 439 def : WriteRes<WriteVecExtractSt, [SKLPort4,SKLPort5,SKLPort237]> {
 440   let Latency = 2;
 441   let NumMicroOps = 3;
 442 }
 443
 444 // Conversion between integer and float.
 445 defm : SKLWriteResPair<WriteCvtSS2I,   [SKLPort0,SKLPort01], 6, [1,1], 2, 5>;
 446 defm : SKLWriteResPair<WriteCvtPS2I,   [SKLPort01], 4, [1], 1, 6>;
 447 defm : SKLWriteResPair<WriteCvtPS2IY,  [SKLPort01], 4, [1], 1, 7>;
 448 defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
 449 defm : SKLWriteResPair<WriteCvtSD2I,   [SKLPort0,SKLPort01], 6, [1,1], 2, 5>;
 450 defm : SKLWriteResPair<WriteCvtPD2I,   [SKLPort5,SKLPort01], 5, [1,1], 2, 6>;
 451 defm : SKLWriteResPair<WriteCvtPD2IY,  [SKLPort5,SKLPort01], 7, [1,1], 2, 6>;
 452 defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
 453
 454 defm : X86WriteRes<WriteCvtI2SS,      [SKLPort5,SKLPort01],  5, [1,1], 2>;
 455 defm : X86WriteRes<WriteCvtI2SSLd,   [SKLPort23,SKLPort01], 10, [1,1], 2>;
 456 defm : SKLWriteResPair<WriteCvtI2PS,   [SKLPort01], 4, [1], 1, 6>;
 457 defm : SKLWriteResPair<WriteCvtI2PSY,  [SKLPort01], 4, [1], 1, 7>;
 458 defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
 459 defm : X86WriteRes<WriteCvtI2SD,      [SKLPort5,SKLPort01],  5, [1,1], 2>;
 460 defm : X86WriteRes<WriteCvtI2SDLd,   [SKLPort23,SKLPort01], 10, [1,1], 2>;
 461 defm : SKLWriteResPair<WriteCvtI2PD,   [SKLPort0,SKLPort5],  5, [1,1], 2, 6>;
 462 defm : SKLWriteResPair<WriteCvtI2PDY,  [SKLPort0,SKLPort5],  7, [1,1], 2, 6>;
 463 defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
 464
 465 defm : X86WriteRes<WriteCvtSS2SD,     [SKLPort5,SKLPort01],  5, [1,1], 2>;
 466 defm : X86WriteRes<WriteCvtSS2SDLd,  [SKLPort23,SKLPort01], 10, [1,1], 2>;
 467 defm : X86WriteRes<WriteCvtPS2PD,     [SKLPort5,SKLPort01],  5, [1,1], 2>;
 468 defm : X86WriteRes<WriteCvtPS2PDLd,  [SKLPort23,SKLPort01],  9, [1,1], 2>;
 469 defm : X86WriteRes<WriteCvtPS2PDY,    [SKLPort5,SKLPort01],  7, [1,1], 2>;
 470 defm : X86WriteRes<WriteCvtPS2PDYLd, [SKLPort23,SKLPort01], 11, [1,1], 2>;
 471 defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
 472 defm : SKLWriteResPair<WriteCvtSD2SS,  [SKLPort5,SKLPort01], 5, [1,1], 2, 5>;
 473 defm : SKLWriteResPair<WriteCvtPD2PS,  [SKLPort5,SKLPort01], 5, [1,1], 2, 6>;
 474 defm : SKLWriteResPair<WriteCvtPD2PSY, [SKLPort5,SKLPort01], 7, [1,1], 2, 6>;
 475 defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
 476
 477 defm : X86WriteRes<WriteCvtPH2PS,     [SKLPort5,SKLPort01],  5, [1,1], 2>;
 478 defm : X86WriteRes<WriteCvtPH2PSY,    [SKLPort5,SKLPort01],  7, [1,1], 2>;
 479 defm : X86WriteResUnsupported<WriteCvtPH2PSZ>;
 480 defm : X86WriteRes<WriteCvtPH2PSLd,  [SKLPort23,SKLPort01],  9, [1,1], 2>;
 481 defm : X86WriteRes<WriteCvtPH2PSYLd, [SKLPort23,SKLPort01], 10, [1,1], 2>;
 482 defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>;
 483
 484 defm : X86WriteRes<WriteCvtPS2PH,                        [SKLPort5,SKLPort01], 5, [1,1], 2>;
 485 defm : X86WriteRes<WriteCvtPS2PHY,                       [SKLPort5,SKLPort01], 7, [1,1], 2>;
 486 defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
 487 defm : X86WriteRes<WriteCvtPS2PHSt,  [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 6, [1,1,1,1], 4>;
 488 defm : X86WriteRes<WriteCvtPS2PHYSt, [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 8, [1,1,1,1], 4>;
 489 defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
 490
 491 // Strings instructions.
 492
 493 // Packed Compare Implicit Length Strings, Return Mask
 494 def : WriteRes<WritePCmpIStrM, [SKLPort0]> {
 495   let Latency = 10;
 496   let NumMicroOps = 3;
 497   let ReleaseAtCycles = [3];
 498 }
 499 def : WriteRes<WritePCmpIStrMLd, [SKLPort0, SKLPort23]> {
 500   let Latency = 16;
 501   let NumMicroOps = 4;
 502   let ReleaseAtCycles = [3,1];
 503 }
 504
 505 // Packed Compare Explicit Length Strings, Return Mask
 506 def : WriteRes<WritePCmpEStrM, [SKLPort0, SKLPort5, SKLPort015, SKLPort0156]> {
 507   let Latency = 19;
 508   let NumMicroOps = 9;
 509   let ReleaseAtCycles = [4,3,1,1];
 510 }
 511 def : WriteRes<WritePCmpEStrMLd, [SKLPort0, SKLPort5,SKLPort23, SKLPort015, SKLPort0156]> {
 512   let Latency = 25;
 513   let NumMicroOps = 10;
 514   let ReleaseAtCycles = [4,3,1,1,1];
 515 }
 516
 517 // Packed Compare Implicit Length Strings, Return Index
 518 def : WriteRes<WritePCmpIStrI, [SKLPort0]> {
 519   let Latency = 10;
 520   let NumMicroOps = 3;
 521   let ReleaseAtCycles = [3];
 522 }
 523 def : WriteRes<WritePCmpIStrILd, [SKLPort0, SKLPort23]> {
 524   let Latency = 16;
 525   let NumMicroOps = 4;
 526   let ReleaseAtCycles = [3,1];
 527 }
 528
 529 // Packed Compare Explicit Length Strings, Return Index
 530 def : WriteRes<WritePCmpEStrI, [SKLPort0, SKLPort5, SKLPort0156]> {
 531   let Latency = 18;
 532   let NumMicroOps = 8;
 533   let ReleaseAtCycles = [4,3,1];
 534 }
 535 def : WriteRes<WritePCmpEStrILd, [SKLPort0, SKLPort5, SKLPort23, SKLPort0156]> {
 536   let Latency = 24;
 537   let NumMicroOps = 9;
 538   let ReleaseAtCycles = [4,3,1,1];
 539 }
 540
 541 // MOVMSK Instructions.
 542 def : WriteRes<WriteFMOVMSK,    [SKLPort0]> { let Latency = 2; }
 543 def : WriteRes<WriteVecMOVMSK,  [SKLPort0]> { let Latency = 2; }
 544 def : WriteRes<WriteVecMOVMSKY, [SKLPort0]> { let Latency = 2; }
 545 def : WriteRes<WriteMMXMOVMSK,  [SKLPort0]> { let Latency = 2; }
 546
 547 // AES instructions.
 548 def : WriteRes<WriteAESDecEnc, [SKLPort0]> { // Decryption, encryption.
 549   let Latency = 4;
 550   let NumMicroOps = 1;
 551   let ReleaseAtCycles = [1];
 552 }
 553 def : WriteRes<WriteAESDecEncLd, [SKLPort0, SKLPort23]> {
 554   let Latency = 10;
 555   let NumMicroOps = 2;
 556   let ReleaseAtCycles = [1,1];
 557 }
 558
 559 def : WriteRes<WriteAESIMC, [SKLPort0]> { // InvMixColumn.
 560   let Latency = 8;
 561   let NumMicroOps = 2;
 562   let ReleaseAtCycles = [2];
 563 }
 564 def : WriteRes<WriteAESIMCLd, [SKLPort0, SKLPort23]> {
 565   let Latency = 14;
 566   let NumMicroOps = 3;
 567   let ReleaseAtCycles = [2,1];
 568 }
 569
 570 def : WriteRes<WriteAESKeyGen, [SKLPort0, SKLPort5, SKLPort015]> { // Key Generation.
 571   let Latency = 20;
 572   let NumMicroOps = 11;
 573   let ReleaseAtCycles = [3,6,2];
 574 }
 575 def : WriteRes<WriteAESKeyGenLd, [SKLPort0, SKLPort5, SKLPort23, SKLPort015]> {
 576   let Latency = 25;
 577   let NumMicroOps = 11;
 578   let ReleaseAtCycles = [3,6,1,1];
 579 }
 580
 581 // Carry-less multiplication instructions.
 582 def : WriteRes<WriteCLMul, [SKLPort5]> {
 583   let Latency = 6;
 584   let NumMicroOps = 1;
 585   let ReleaseAtCycles = [1];
 586 }
 587 def : WriteRes<WriteCLMulLd, [SKLPort5, SKLPort23]> {
 588   let Latency = 12;
 589   let NumMicroOps = 2;
 590   let ReleaseAtCycles = [1,1];
 591 }
 592
 593 // Catch-all for expensive system instructions.
 594 def : WriteRes<WriteSystem,     [SKLPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
 595
 596 // AVX2.
 597 defm : SKLWriteResPair<WriteFShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles.
 598 defm : SKLWriteResPair<WriteFVarShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles.
 599 defm : SKLWriteResPair<WriteShuffle256, [SKLPort5], 3, [1], 1, 7>;  // 256-bit width vector shuffles.
 600 defm : SKLWriteResPair<WriteVPMOV256, [SKLPort5], 3, [1], 1, 7>;  // 256-bit width packed vector width-changing move.
 601 defm : SKLWriteResPair<WriteVarShuffle256, [SKLPort5], 3, [1], 1, 7>;  // 256-bit width vector variable shuffles.
 602
 603 // Old microcoded instructions that nobody use.
 604 def : WriteRes<WriteMicrocoded, [SKLPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
 605
 606 // Fence instructions.
 607 def : WriteRes<WriteFence,  [SKLPort23, SKLPort4]>;
 608
 609 // Load/store MXCSR.
 610 def : WriteRes<WriteLDMXCSR, [SKLPort0,SKLPort23,SKLPort0156]> { let Latency = 7; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
 611 def : WriteRes<WriteSTMXCSR, [SKLPort4,SKLPort5,SKLPort237]> { let Latency = 2; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; }
 612
 613 // Nop, not very useful expect it provides a model for nops!
 614 def : WriteRes<WriteNop, []>;
 615
 616 ////////////////////////////////////////////////////////////////////////////////
 617 // Horizontal add/sub  instructions.
 618 ////////////////////////////////////////////////////////////////////////////////
 619
 620 defm : SKLWriteResPair<WriteFHAdd,  [SKLPort5,SKLPort01], 6, [2,1], 3, 6>;
 621 defm : SKLWriteResPair<WriteFHAddY, [SKLPort5,SKLPort01], 6, [2,1], 3, 7>;
 622 defm : SKLWriteResPair<WritePHAdd,  [SKLPort5,SKLPort05],  3, [2,1], 3, 5>;
 623 defm : SKLWriteResPair<WritePHAddX, [SKLPort5,SKLPort015], 3, [2,1], 3, 6>;
 624 defm : SKLWriteResPair<WritePHAddY, [SKLPort5,SKLPort015], 3, [2,1], 3, 7>;
 625
 626 // Remaining instrs.
 627
 628 def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> {
 629   let Latency = 1;
 630   let NumMicroOps = 1;
 631   let ReleaseAtCycles = [1];
 632 }
 633 def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDS(B|W)rr",
 634                                             "MMX_PADDUS(B|W)rr",
 635                                             "MMX_PAVG(B|W)rr",
 636                                             "MMX_PCMPEQ(B|D|W)rr",
 637                                             "MMX_PCMPGT(B|D|W)rr",
 638                                             "MMX_P(MAX|MIN)SWrr",
 639                                             "MMX_P(MAX|MIN)UBrr",
 640                                             "MMX_PSUBS(B|W)rr",
 641                                             "MMX_PSUBUS(B|W)rr")>;
 642
 643 def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> {
 644   let Latency = 1;
 645   let NumMicroOps = 1;
 646   let ReleaseAtCycles = [1];
 647 }
 648 def: InstRW<[SKLWriteResGroup3], (instregex "COM(P?)_FST0r",
 649                                             "UCOM_F(P?)r")>;
 650
 651 def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> {
 652   let Latency = 1;
 653   let NumMicroOps = 1;
 654   let ReleaseAtCycles = [1];
 655 }
 656 def: InstRW<[SKLWriteResGroup4], (instregex "JMP(16|32|64)r")>;
 657
 658 def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> {
 659   let Latency = 1;
 660   let NumMicroOps = 1;
 661   let ReleaseAtCycles = [1];
 662 }
 663 def: InstRW<[SKLWriteResGroup6], (instrs FINCSTP, FNOP)>;
 664
 665 def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> {
 666   let Latency = 1;
 667   let NumMicroOps = 1;
 668   let ReleaseAtCycles = [1];
 669 }
 670 def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
 671
 672 def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> {
 673   let Latency = 1;
 674   let NumMicroOps = 1;
 675   let ReleaseAtCycles = [1];
 676 }
 677 def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr")>;
 678
 679 def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> {
 680   let Latency = 1;
 681   let NumMicroOps = 1;
 682   let ReleaseAtCycles = [1];
 683 }
 684 def: InstRW<[SKLWriteResGroup9], (instregex "(V?)PADD(B|D|Q|W)(Y?)rr",
 685                                             "VPBLENDD(Y?)rri")>;
 686
 687 def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {
 688   let Latency = 1;
 689   let NumMicroOps = 1;
 690   let ReleaseAtCycles = [1];
 691 }
 692 def: InstRW<[SKLWriteResGroup10], (instrs SGDT64m,
 693                                           SIDT64m,
 694                                           SMSW16m,
 695                                           STRm,
 696                                           SYSCALL)>;
 697
 698 def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> {
 699   let Latency = 1;
 700   let NumMicroOps = 2;
 701   let ReleaseAtCycles = [1,1];
 702 }
 703 def: InstRW<[SKLWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>;
 704 def: InstRW<[SKLWriteResGroup11], (instregex "ST_FP(32|64|80)m")>;
 705
 706 def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> {
 707   let Latency = 2;
 708   let NumMicroOps = 2;
 709   let ReleaseAtCycles = [2];
 710 }
 711 def: InstRW<[SKLWriteResGroup13], (instrs MMX_MOVQ2DQrr)>;
 712
 713 def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> {
 714   let Latency = 2;
 715   let NumMicroOps = 2;
 716   let ReleaseAtCycles = [2];
 717 }
 718 def: InstRW<[SKLWriteResGroup14], (instrs FDECSTP,
 719                                           MMX_MOVDQ2Qrr)>;
 720
 721 def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> {
 722   let Latency = 2;
 723   let NumMicroOps = 2;
 724   let ReleaseAtCycles = [2];
 725 }
 726 def: InstRW<[SKLWriteResGroup17], (instrs LFENCE,
 727                                           WAIT,
 728                                           XGETBV)>;
 729
 730 def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
 731   let Latency = 2;
 732   let NumMicroOps = 2;
 733   let ReleaseAtCycles = [1,1];
 734 }
 735 def: InstRW<[SKLWriteResGroup20], (instregex "CLFLUSH")>;
 736
 737 def SKLWriteResGroup21 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
 738   let Latency = 2;
 739   let NumMicroOps = 2;
 740   let ReleaseAtCycles = [1,1];
 741 }
 742 def: InstRW<[SKLWriteResGroup21], (instrs SFENCE)>;
 743
 744 def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
 745   let Latency = 2;
 746   let NumMicroOps = 2;
 747   let ReleaseAtCycles = [1,1];
 748 }
 749 def: InstRW<[SKLWriteResGroup23], (instrs CWD,
 750                                           JCXZ, JECXZ, JRCXZ,
 751                                           ADC8i8, SBB8i8,
 752                                           ADC16i16, SBB16i16,
 753                                           ADC32i32, SBB32i32,
 754                                           ADC64i32, SBB64i32)>;
 755
 756 def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> {
 757   let Latency = 2;
 758   let NumMicroOps = 3;
 759   let ReleaseAtCycles = [1,1,1];
 760 }
 761 def: InstRW<[SKLWriteResGroup25], (instrs FNSTCW16m)>;
 762
 763 def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> {
 764   let Latency = 2;
 765   let NumMicroOps = 3;
 766   let ReleaseAtCycles = [1,1,1];
 767 }
 768 def: InstRW<[SKLWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
 769
 770 def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
 771   let Latency = 2;
 772   let NumMicroOps = 3;
 773   let ReleaseAtCycles = [1,1,1];
 774 }
 775 def: InstRW<[SKLWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
 776                                           STOSB, STOSL, STOSQ, STOSW)>;
 777 def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>;
 778
 779 def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> {
 780   let Latency = 3;
 781   let NumMicroOps = 1;
 782   let ReleaseAtCycles = [1];
 783 }
 784 def: InstRW<[SKLWriteResGroup29], (instregex "PDEP(32|64)rr",
 785                                              "PEXT(32|64)rr")>;
 786
 787 def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> {
 788   let Latency = 3;
 789   let NumMicroOps = 1;
 790   let ReleaseAtCycles = [1];
 791 }
 792 def: InstRW<[SKLWriteResGroup30], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)",
 793                                              "VPBROADCAST(B|W)rr")>;
 794
 795 def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,SKLPort0156]> {
 796   let Latency = 3;
 797   let NumMicroOps = 2;
 798   let ReleaseAtCycles = [1,1];
 799 }
 800 def: InstRW<[SKLWriteResGroup32], (instrs FNSTSW16r)>;
 801
 802 def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,SKLPort5]> {
 803   let Latency = 3;
 804   let NumMicroOps = 3;
 805   let ReleaseAtCycles = [1,2];
 806 }
 807 def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PH(ADD|SUB)SWrr")>;
 808
 809 def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,SKLPort01]> {
 810   let Latency = 3;
 811   let NumMicroOps = 3;
 812   let ReleaseAtCycles = [2,1];
 813 }
 814 def: InstRW<[SKLWriteResGroup36], (instregex "(V?)PHADDSW(Y?)rr",
 815                                              "(V?)PHSUBSW(Y?)rr")>;
 816
 817 def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
 818   let Latency = 3;
 819   let NumMicroOps = 3;
 820   let ReleaseAtCycles = [2,1];
 821 }
 822 def: InstRW<[SKLWriteResGroup39], (instrs MMX_PACKSSDWrr,
 823                                           MMX_PACKSSWBrr,
 824                                           MMX_PACKUSWBrr)>;
 825
 826 def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
 827   let Latency = 3;
 828   let NumMicroOps = 3;
 829   let ReleaseAtCycles = [1,2];
 830 }
 831 def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>;
 832
 833 def SKLWriteResGroup41 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
 834   let Latency = 3;
 835   let NumMicroOps = 3;
 836   let ReleaseAtCycles = [1,2];
 837 }
 838 def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>;
 839
 840 def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
 841   let Latency = 2;
 842   let NumMicroOps = 3;
 843   let ReleaseAtCycles = [1,2];
 844 }
 845 def: InstRW<[SKLWriteResGroup42], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
 846                                           RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;
 847
 848 def SKLWriteResGroup42b : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
 849   let Latency = 5;
 850   let NumMicroOps = 8;
 851   let ReleaseAtCycles = [2,4,2];
 852 }
 853 def: InstRW<[SKLWriteResGroup42b], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
 854
 855 def SKLWriteResGroup42c : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
 856   let Latency = 6;
 857   let NumMicroOps = 8;
 858   let ReleaseAtCycles = [2,4,2];
 859 }
 860 def: InstRW<[SKLWriteResGroup42c], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
 861
 862 def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> {
 863   let Latency = 3;
 864   let NumMicroOps = 3;
 865   let ReleaseAtCycles = [1,1,1];
 866 }
 867 def: InstRW<[SKLWriteResGroup43], (instrs FNSTSWm)>;
 868
 869 def SKLWriteResGroup45 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237,SKLPort0156]> {
 870   let Latency = 3;
 871   let NumMicroOps = 4;
 872   let ReleaseAtCycles = [1,1,1,1];
 873 }
 874 def: InstRW<[SKLWriteResGroup45], (instregex "CALL(16|32|64)r")>;
 875
 876 def SKLWriteResGroup46 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06,SKLPort0156]> {
 877   let Latency = 3;
 878   let NumMicroOps = 4;
 879   let ReleaseAtCycles = [1,1,1,1];
 880 }
 881 def: InstRW<[SKLWriteResGroup46], (instrs CALL64pcrel32)>;
 882
 883 def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0]> {
 884   let Latency = 4;
 885   let NumMicroOps = 1;
 886   let ReleaseAtCycles = [1];
 887 }
 888 def: InstRW<[SKLWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
 889
 890 def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> {
 891   let Latency = 4;
 892   let NumMicroOps = 3;
 893   let ReleaseAtCycles = [1,1,1];
 894 }
 895 def: InstRW<[SKLWriteResGroup53], (instregex "IST(T?)_FP(16|32|64)m",
 896                                              "IST_F(16|32)m")>;
 897
 898 def SKLWriteResGroup54 : SchedWriteRes<[SKLPort0156]> {
 899   let Latency = 4;
 900   let NumMicroOps = 4;
 901   let ReleaseAtCycles = [4];
 902 }
 903 def: InstRW<[SKLWriteResGroup54], (instrs FNCLEX)>;
 904
 905 def SKLWriteResGroup55 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
 906   let Latency = 4;
 907   let NumMicroOps = 4;
 908   let ReleaseAtCycles = [1,3];
 909 }
 910 def: InstRW<[SKLWriteResGroup55], (instrs PAUSE)>;
 911
 912 def SKLWriteResGroup56 : SchedWriteRes<[]> {
 913   let Latency = 0;
 914   let NumMicroOps = 4;
 915   let ReleaseAtCycles = [];
 916 }
 917 def: InstRW<[SKLWriteResGroup56], (instrs VZEROUPPER)>;
 918
 919 def SKLWriteResGroup57 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> {
 920   let Latency = 4;
 921   let NumMicroOps = 4;
 922   let ReleaseAtCycles = [1,1,2];
 923 }
 924 def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
 925
 926 def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort01]> {
 927   let Latency = 5;
 928   let NumMicroOps = 2;
 929   let ReleaseAtCycles = [1,1];
 930 }
 931 def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVT(T?)PS2PIrr")>;
 932
 933 def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> {
 934   let Latency = 5;
 935   let NumMicroOps = 3;
 936   let ReleaseAtCycles = [1,1,1];
 937 }
 938 def: InstRW<[SKLWriteResGroup61], (instregex "STR(16|32|64)r")>;
 939
 940 def SKLWriteResGroup63 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
 941   let Latency = 5;
 942   let NumMicroOps = 5;
 943   let ReleaseAtCycles = [1,4];
 944 }
 945 def: InstRW<[SKLWriteResGroup63], (instrs XSETBV)>;
 946
 947 def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
 948   let Latency = 5;
 949   let NumMicroOps = 6;
 950   let ReleaseAtCycles = [1,1,4];
 951 }
 952 def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF(16|64)")>;
 953
 954 def SKLWriteResGroup67 : SchedWriteRes<[SKLPort23]> {
 955   let Latency = 6;
 956   let NumMicroOps = 1;
 957   let ReleaseAtCycles = [1];
 958 }
 959 def: InstRW<[SKLWriteResGroup67], (instrs VBROADCASTSSrm,
 960                                           VPBROADCASTDrm,
 961                                           VPBROADCASTQrm)>;
 962 def: InstRW<[SKLWriteResGroup67], (instregex "(V?)MOVSHDUPrm",
 963                                              "(V?)MOVSLDUPrm",
 964                                              "(V?)MOVDDUPrm")>;
 965
 966 def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0]> {
 967   let Latency = 6;
 968   let NumMicroOps = 2;
 969   let ReleaseAtCycles = [2];
 970 }
 971 def: InstRW<[SKLWriteResGroup68], (instrs MMX_CVTPI2PSrr)>;
 972
 973 def SKLWriteResGroup69 : SchedWriteRes<[SKLPort0,SKLPort23]> {
 974   let Latency = 6;
 975   let NumMicroOps = 2;
 976   let ReleaseAtCycles = [1,1];
 977 }
 978 def: InstRW<[SKLWriteResGroup69], (instrs MMX_PADDSBrm,
 979                                           MMX_PADDSWrm,
 980                                           MMX_PADDUSBrm,
 981                                           MMX_PADDUSWrm,
 982                                           MMX_PAVGBrm,
 983                                           MMX_PAVGWrm,
 984                                           MMX_PCMPEQBrm,
 985                                           MMX_PCMPEQDrm,
 986                                           MMX_PCMPEQWrm,
 987                                           MMX_PCMPGTBrm,
 988                                           MMX_PCMPGTDrm,
 989                                           MMX_PCMPGTWrm,
 990                                           MMX_PMAXSWrm,
 991                                           MMX_PMAXUBrm,
 992                                           MMX_PMINSWrm,
 993                                           MMX_PMINUBrm,
 994                                           MMX_PSUBSBrm,
 995                                           MMX_PSUBSWrm,
 996                                           MMX_PSUBUSBrm,
 997                                           MMX_PSUBUSWrm)>;
 998
 999 def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> {
1000   let Latency = 6;
1001   let NumMicroOps = 2;
1002   let ReleaseAtCycles = [1,1];
1003 }
1004 def: InstRW<[SKLWriteResGroup72], (instrs FARJMP64m)>;
1005 def: InstRW<[SKLWriteResGroup72], (instregex "JMP(16|32|64)m")>;
1006
1007 def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> {
1008   let Latency = 6;
1009   let NumMicroOps = 2;
1010   let ReleaseAtCycles = [1,1];
1011 }
1012 def: InstRW<[SKLWriteResGroup75], (instregex "ANDN(32|64)rm",
1013                                              "MOVBE(16|32|64)rm")>;
1014
1015 def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
1016   let Latency = 6;
1017   let NumMicroOps = 2;
1018   let ReleaseAtCycles = [1,1];
1019 }
1020 def: InstRW<[SKLWriteResGroup76], (instrs POP16r, POP32r, POP64r)>;
1021 def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>;
1022
1023 def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort01]> {
1024   let Latency = 6;
1025   let NumMicroOps = 3;
1026   let ReleaseAtCycles = [2,1];
1027 }
1028 def: InstRW<[SKLWriteResGroup78], (instregex "(V?)CVTSI642SSrr")>;
1029
1030 def SKLWriteResGroup80 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06,SKLPort0156]> {
1031   let Latency = 6;
1032   let NumMicroOps = 4;
1033   let ReleaseAtCycles = [1,1,1,1];
1034 }
1035 def: InstRW<[SKLWriteResGroup80], (instregex "SLDT(16|32|64)r")>;
1036
1037 def SKLWriteResGroup82 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1038   let Latency = 6;
1039   let NumMicroOps = 4;
1040   let ReleaseAtCycles = [1,1,1,1];
1041 }
1042 def: InstRW<[SKLWriteResGroup82], (instregex "SAR(8|16|32|64)m(1|i)",
1043                                              "SHL(8|16|32|64)m(1|i)",
1044                                              "SHR(8|16|32|64)m(1|i)")>;
1045
1046 def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
1047   let Latency = 6;
1048   let NumMicroOps = 4;
1049   let ReleaseAtCycles = [1,1,1,1];
1050 }
1051 def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm",
1052                                              "PUSH(16|32|64)rmm")>;
1053
1054 def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
1055   let Latency = 6;
1056   let NumMicroOps = 6;
1057   let ReleaseAtCycles = [1,5];
1058 }
1059 def: InstRW<[SKLWriteResGroup84], (instrs STD)>;
1060
1061 def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> {
1062   let Latency = 7;
1063   let NumMicroOps = 1;
1064   let ReleaseAtCycles = [1];
1065 }
1066 def: InstRW<[SKLWriteResGroup85], (instregex "LD_F(32|64|80)m")>;
1067 def: InstRW<[SKLWriteResGroup85], (instrs VBROADCASTF128rm,
1068                                           VBROADCASTI128rm,
1069                                           VBROADCASTSDYrm,
1070                                           VBROADCASTSSYrm,
1071                                           VMOVDDUPYrm,
1072                                           VMOVSHDUPYrm,
1073                                           VMOVSLDUPYrm,
1074                                           VPBROADCASTDYrm,
1075                                           VPBROADCASTQYrm)>;
1076
1077 def SKLWriteResGroup88 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1078   let Latency = 6;
1079   let NumMicroOps = 2;
1080   let ReleaseAtCycles = [1,1];
1081 }
1082 def: InstRW<[SKLWriteResGroup88], (instregex "(V?)PMOV(SX|ZX)BDrm",
1083                                              "(V?)PMOV(SX|ZX)BQrm",
1084                                              "(V?)PMOV(SX|ZX)BWrm",
1085                                              "(V?)PMOV(SX|ZX)DQrm",
1086                                              "(V?)PMOV(SX|ZX)WDrm",
1087                                              "(V?)PMOV(SX|ZX)WQrm")>;
1088
1089 def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> {
1090   let Latency = 7;
1091   let NumMicroOps = 2;
1092   let ReleaseAtCycles = [1,1];
1093 }
1094 def: InstRW<[SKLWriteResGroup91], (instrs VINSERTF128rm,
1095                                           VINSERTI128rm,
1096                                           VPBLENDDrmi)>;
1097 def: InstRW<[SKLWriteResGroup91, ReadAfterVecXLd],
1098                                   (instregex "(V?)PADD(B|D|Q|W)rm",
1099                                              "(V?)PSUB(B|D|Q|W)rm")>;
1100
1101 def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1102   let Latency = 7;
1103   let NumMicroOps = 3;
1104   let ReleaseAtCycles = [2,1];
1105 }
1106 def: InstRW<[SKLWriteResGroup92], (instrs MMX_PACKSSDWrm,
1107                                           MMX_PACKSSWBrm,
1108                                           MMX_PACKUSWBrm)>;
1109
1110 def SKLWriteResGroup94 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
1111   let Latency = 7;
1112   let NumMicroOps = 3;
1113   let ReleaseAtCycles = [1,2];
1114 }
1115 def: InstRW<[SKLWriteResGroup94], (instrs LEAVE, LEAVE64,
1116                                           SCASB, SCASL, SCASQ, SCASW)>;
1117
1118 def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort01]> {
1119   let Latency = 7;
1120   let NumMicroOps = 3;
1121   let ReleaseAtCycles = [1,1,1];
1122 }
1123 def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVT(T?)SS2SI64rr")>;
1124
1125 def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> {
1126   let Latency = 7;
1127   let NumMicroOps = 3;
1128   let ReleaseAtCycles = [1,1,1];
1129 }
1130 def: InstRW<[SKLWriteResGroup96], (instrs FLDCW16m)>;
1131
1132 def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> {
1133   let Latency = 7;
1134   let NumMicroOps = 3;
1135   let ReleaseAtCycles = [1,1,1];
1136 }
1137 def: InstRW<[SKLWriteResGroup98], (instrs LRET64, RET64)>;
1138
1139 def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1140   let Latency = 7;
1141   let NumMicroOps = 5;
1142   let ReleaseAtCycles = [1,1,1,2];
1143 }
1144 def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m(1|i)",
1145                                               "ROR(8|16|32|64)m(1|i)")>;
1146
1147 def SKLWriteResGroup100_1 : SchedWriteRes<[SKLPort06]> {
1148   let Latency = 2;
1149   let NumMicroOps = 2;
1150   let ReleaseAtCycles = [2];
1151 }
1152 def: InstRW<[SKLWriteResGroup100_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
1153                                              ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;
1154
1155 def SKLWriteResGroup101 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
1156   let Latency = 7;
1157   let NumMicroOps = 5;
1158   let ReleaseAtCycles = [1,1,1,2];
1159 }
1160 def: InstRW<[SKLWriteResGroup101], (instregex "XADD(8|16|32|64)rm")>;
1161
1162 def SKLWriteResGroup102 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1163   let Latency = 7;
1164   let NumMicroOps = 5;
1165   let ReleaseAtCycles = [1,1,1,1,1];
1166 }
1167 def: InstRW<[SKLWriteResGroup102], (instregex "CALL(16|32|64)m")>;
1168 def: InstRW<[SKLWriteResGroup102], (instrs FARCALL64m)>;
1169
1170 def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort0156]> {
1171   let Latency = 7;
1172   let NumMicroOps = 7;
1173   let ReleaseAtCycles = [1,3,1,2];
1174 }
1175 def: InstRW<[SKLWriteResGroup103], (instrs LOOP)>;
1176
1177 def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,SKLPort23]> {
1178   let Latency = 8;
1179   let NumMicroOps = 2;
1180   let ReleaseAtCycles = [1,1];
1181 }
1182 def: InstRW<[SKLWriteResGroup107], (instregex "PDEP(32|64)rm",
1183                                               "PEXT(32|64)rm")>;
1184
1185 def SKLWriteResGroup108 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1186   let Latency = 8;
1187   let NumMicroOps = 2;
1188   let ReleaseAtCycles = [1,1];
1189 }
1190 def: InstRW<[SKLWriteResGroup108], (instregex "FCOM(P?)(32|64)m")>;
1191 def: InstRW<[SKLWriteResGroup108], (instrs VPBROADCASTBYrm,
1192                                            VPBROADCASTWYrm,
1193                                            VPMOVSXBDYrm,
1194                                            VPMOVSXBQYrm,
1195                                            VPMOVSXWQYrm)>;
1196
1197 def SKLWriteResGroup110 : SchedWriteRes<[SKLPort23,SKLPort015]> {
1198   let Latency = 8;
1199   let NumMicroOps = 2;
1200   let ReleaseAtCycles = [1,1];
1201 }
1202 def: InstRW<[SKLWriteResGroup110], (instrs VPBLENDDYrmi)>;
1203 def: InstRW<[SKLWriteResGroup110, ReadAfterVecYLd],
1204                                    (instregex "VPADD(B|D|Q|W)Yrm",
1205                                               "VPSUB(B|D|Q|W)Yrm")>;
1206
1207 def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1208   let Latency = 8;
1209   let NumMicroOps = 4;
1210   let ReleaseAtCycles = [1,2,1];
1211 }
1212 def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PH(ADD|SUB)SWrm")>;
1213
1214 def SKLWriteResGroup116 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1215   let Latency = 8;
1216   let NumMicroOps = 5;
1217   let ReleaseAtCycles = [1,1,1,2];
1218 }
1219 def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m(1|i)",
1220                                               "RCR(8|16|32|64)m(1|i)")>;
1221
1222 def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1223   let Latency = 8;
1224   let NumMicroOps = 6;
1225   let ReleaseAtCycles = [1,1,1,3];
1226 }
1227 def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL",
1228                                               "ROR(8|16|32|64)mCL",
1229                                               "SAR(8|16|32|64)mCL",
1230                                               "SHL(8|16|32|64)mCL",
1231                                               "SHR(8|16|32|64)mCL")>;
1232
1233 def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1234   let Latency = 8;
1235   let NumMicroOps = 6;
1236   let ReleaseAtCycles = [1,1,1,2,1];
1237 }
1238 def: SchedAlias<WriteADCRMW, SKLWriteResGroup119>;
1239
1240 def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1241   let Latency = 9;
1242   let NumMicroOps = 2;
1243   let ReleaseAtCycles = [1,1];
1244 }
1245 def: InstRW<[SKLWriteResGroup120], (instrs MMX_CVTPI2PSrm)>;
1246
1247 def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1248   let Latency = 9;
1249   let NumMicroOps = 2;
1250   let ReleaseAtCycles = [1,1];
1251 }
1252 def: InstRW<[SKLWriteResGroup121], (instrs PCMPGTQrm,
1253                                            VPCMPGTQrm,
1254                                            VPMOVSXBWYrm,
1255                                            VPMOVSXDQYrm,
1256                                            VPMOVSXWDYrm,
1257                                            VPMOVZXWDYrm)>;
1258
1259 def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort01]> {
1260   let Latency = 9;
1261   let NumMicroOps = 2;
1262   let ReleaseAtCycles = [1,1];
1263 }
1264 def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVT(T?)PS2PIrm")>;
1265
1266 def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
1267   let Latency = 9;
1268   let NumMicroOps = 4;
1269   let ReleaseAtCycles = [2,1,1];
1270 }
1271 def: InstRW<[SKLWriteResGroup128], (instregex "(V?)PHADDSWrm",
1272                                               "(V?)PHSUBSWrm")>;
1273
1274 def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
1275   let Latency = 9;
1276   let NumMicroOps = 5;
1277   let ReleaseAtCycles = [1,2,1,1];
1278 }
1279 def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm",
1280                                               "LSL(16|32|64)rm")>;
1281
1282 def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1283   let Latency = 10;
1284   let NumMicroOps = 2;
1285   let ReleaseAtCycles = [1,1];
1286 }
1287 def: InstRW<[SKLWriteResGroup133], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1288                                               "ILD_F(16|32|64)m")>;
1289 def: InstRW<[SKLWriteResGroup133], (instrs VPCMPGTQYrm)>;
1290
1291 def SKLWriteResGroup138 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1292   let Latency = 10;
1293   let NumMicroOps = 3;
1294   let ReleaseAtCycles = [1,1,1];
1295 }
1296 def: InstRW<[SKLWriteResGroup138], (instrs MMX_CVTPI2PDrm)>;
1297
1298 def SKLWriteResGroup140 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
1299   let Latency = 10;
1300   let NumMicroOps = 4;
1301   let ReleaseAtCycles = [2,1,1];
1302 }
1303 def: InstRW<[SKLWriteResGroup140], (instrs VPHADDSWYrm,
1304                                            VPHSUBSWYrm)>;
1305
1306 def SKLWriteResGroup143 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1307   let Latency = 10;
1308   let NumMicroOps = 8;
1309   let ReleaseAtCycles = [1,1,1,1,1,3];
1310 }
1311 def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>;
1312
1313 def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1314   let Latency = 11;
1315   let NumMicroOps = 2;
1316   let ReleaseAtCycles = [1,1];
1317 }
1318 def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F(32|64)m")>;
1319
1320 def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1321   let Latency = 11;
1322   let NumMicroOps = 3;
1323   let ReleaseAtCycles = [2,1];
1324 }
1325 def: InstRW<[SKLWriteResGroup149], (instregex "FICOM(P?)(16|32)m")>;
1326
1327 def SKLWriteResGroup154 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
1328   let Latency = 11;
1329   let NumMicroOps = 7;
1330   let ReleaseAtCycles = [2,3,2];
1331 }
1332 def: InstRW<[SKLWriteResGroup154], (instregex "RCL(16|32|64)rCL",
1333                                               "RCR(16|32|64)rCL")>;
1334
1335 def SKLWriteResGroup155 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
1336   let Latency = 11;
1337   let NumMicroOps = 9;
1338   let ReleaseAtCycles = [1,5,1,2];
1339 }
1340 def: InstRW<[SKLWriteResGroup155], (instrs RCL8rCL)>;
1341
1342 def SKLWriteResGroup156 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
1343   let Latency = 11;
1344   let NumMicroOps = 11;
1345   let ReleaseAtCycles = [2,9];
1346 }
1347 def: InstRW<[SKLWriteResGroup156], (instrs LOOPE, LOOPNE)>;
1348
1349 def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1350   let Latency = 13;
1351   let NumMicroOps = 3;
1352   let ReleaseAtCycles = [2,1];
1353 }
1354 def: InstRW<[SKLWriteResGroup162], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
1355
1356 def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1357   let Latency = 14;
1358   let NumMicroOps = 3;
1359   let ReleaseAtCycles = [1,1,1];
1360 }
1361 def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI(16|32)m")>;
1362
1363 def SKLWriteResGroup170 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
1364   let Latency = 14;
1365   let NumMicroOps = 10;
1366   let ReleaseAtCycles = [2,4,1,3];
1367 }
1368 def: InstRW<[SKLWriteResGroup170], (instrs RCR8rCL)>;
1369
1370 def SKLWriteResGroup171 : SchedWriteRes<[SKLPort0]> {
1371   let Latency = 15;
1372   let NumMicroOps = 1;
1373   let ReleaseAtCycles = [1];
1374 }
1375 def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
1376
1377 def SKLWriteResGroup174 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
1378   let Latency = 15;
1379   let NumMicroOps = 10;
1380   let ReleaseAtCycles = [1,1,1,5,1,1];
1381 }
1382 def: InstRW<[SKLWriteResGroup174], (instregex "RCL(8|16|32|64)mCL")>;
1383
1384 def SKLWriteResGroup177 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
1385   let Latency = 16;
1386   let NumMicroOps = 14;
1387   let ReleaseAtCycles = [1,1,1,4,2,5];
1388 }
1389 def: InstRW<[SKLWriteResGroup177], (instrs CMPXCHG8B)>;
1390
1391 def SKLWriteResGroup178 : SchedWriteRes<[SKLPort0156]> {
1392   let Latency = 16;
1393   let NumMicroOps = 16;
1394   let ReleaseAtCycles = [16];
1395 }
1396 def: InstRW<[SKLWriteResGroup178], (instrs VZEROALL)>;
1397
1398 def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {
1399   let Latency = 17;
1400   let NumMicroOps = 15;
1401   let ReleaseAtCycles = [2,1,2,4,2,4];
1402 }
1403 def: InstRW<[SKLWriteResGroup180], (instrs XCH_F)>;
1404
1405 def SKLWriteResGroup184 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {
1406   let Latency = 18;
1407   let NumMicroOps = 8;
1408   let ReleaseAtCycles = [1,1,1,5];
1409 }
1410 def: InstRW<[SKLWriteResGroup184], (instrs CPUID, RDTSC)>;
1411
1412 def SKLWriteResGroup185 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
1413   let Latency = 18;
1414   let NumMicroOps = 11;
1415   let ReleaseAtCycles = [2,1,1,4,1,2];
1416 }
1417 def: InstRW<[SKLWriteResGroup185], (instregex "RCR(8|16|32|64)mCL")>;
1418
1419 def SKLWriteResGroup189 : SchedWriteRes<[SKLPort0]> {
1420   let Latency = 20;
1421   let NumMicroOps = 1;
1422   let ReleaseAtCycles = [1];
1423 }
1424 def: InstRW<[SKLWriteResGroup189], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
1425
1426 def SKLWriteResGroup192 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1427   let Latency = 20;
1428   let NumMicroOps = 8;
1429   let ReleaseAtCycles = [1,1,1,1,1,1,2];
1430 }
1431 def: InstRW<[SKLWriteResGroup192], (instrs INSB, INSL, INSW)>;
1432
1433 def SKLWriteResGroup193 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> {
1434   let Latency = 20;
1435   let NumMicroOps = 10;
1436   let ReleaseAtCycles = [1,2,7];
1437 }
1438 def: InstRW<[SKLWriteResGroup193], (instrs MWAITrr)>;
1439
1440 def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1441   let Latency = 22;
1442   let NumMicroOps = 2;
1443   let ReleaseAtCycles = [1,1];
1444 }
1445 def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F(32|64)m")>;
1446
1447 def SKLWriteResGroupVEX2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
1448   let Latency = 18;
1449   let NumMicroOps = 5; // 2 uops perform multiple loads
1450   let ReleaseAtCycles = [1,2,1,1];
1451 }
1452 def: InstRW<[SKLWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm,
1453                                             VGATHERQPDrm, VPGATHERQQrm,
1454                                             VGATHERQPSrm, VPGATHERQDrm)>;
1455
1456 def SKLWriteResGroupVEX4 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
1457   let Latency = 20;
1458   let NumMicroOps = 5; // 2 uops peform multiple loads
1459   let ReleaseAtCycles = [1,4,1,1];
1460 }
1461 def: InstRW<[SKLWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm,
1462                                             VGATHERDPSrm,  VPGATHERDDrm,
1463                                             VGATHERQPDYrm, VPGATHERQQYrm,
1464                                             VGATHERQPSYrm,  VPGATHERQDYrm)>;
1465
1466 def SKLWriteResGroupVEX8 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
1467   let Latency = 22;
1468   let NumMicroOps = 5; // 2 uops perform multiple loads
1469   let ReleaseAtCycles = [1,8,1,1];
1470 }
1471 def: InstRW<[SKLWriteResGroupVEX8], (instrs VGATHERDPSYrm,  VPGATHERDDYrm)>;
1472
1473 def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort5,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1474   let Latency = 23;
1475   let NumMicroOps = 19;
1476   let ReleaseAtCycles = [2,1,4,1,1,4,6];
1477 }
1478 def: InstRW<[SKLWriteResGroup198], (instrs CMPXCHG16B)>;
1479
1480 def SKLWriteResGroup202 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1481   let Latency = 25;
1482   let NumMicroOps = 3;
1483   let ReleaseAtCycles = [1,1,1];
1484 }
1485 def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI(16|32)m")>;
1486
1487 def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1488   let Latency = 27;
1489   let NumMicroOps = 2;
1490   let ReleaseAtCycles = [1,1];
1491 }
1492 def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F(32|64)m")>;
1493
1494 def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1495   let Latency = 30;
1496   let NumMicroOps = 3;
1497   let ReleaseAtCycles = [1,1,1];
1498 }
1499 def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI(16|32)m")>;
1500
1501 def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,SKLPort0156]> {
1502   let Latency = 35;
1503   let NumMicroOps = 23;
1504   let ReleaseAtCycles = [1,5,3,4,10];
1505 }
1506 def: InstRW<[SKLWriteResGroup209], (instregex "IN(8|16|32)ri",
1507                                               "IN(8|16|32)rr")>;
1508
1509 def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1510   let Latency = 35;
1511   let NumMicroOps = 23;
1512   let ReleaseAtCycles = [1,5,2,1,4,10];
1513 }
1514 def: InstRW<[SKLWriteResGroup210], (instregex "OUT(8|16|32)ir",
1515                                               "OUT(8|16|32)rr")>;
1516
1517 def SKLWriteResGroup211 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
1518   let Latency = 37;
1519   let NumMicroOps = 31;
1520   let ReleaseAtCycles = [1,8,1,21];
1521 }
1522 def: InstRW<[SKLWriteResGroup211], (instregex "XRSTOR(64)?")>;
1523
1524 def SKLWriteResGroup212 : SchedWriteRes<[SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort15,SKLPort0156]> {
1525   let Latency = 40;
1526   let NumMicroOps = 18;
1527   let ReleaseAtCycles = [1,1,2,3,1,1,1,8];
1528 }
1529 def: InstRW<[SKLWriteResGroup212], (instrs VMCLEARm)>;
1530
1531 def SKLWriteResGroup213 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1532   let Latency = 41;
1533   let NumMicroOps = 39;
1534   let ReleaseAtCycles = [1,10,1,1,26];
1535 }
1536 def: InstRW<[SKLWriteResGroup213], (instrs XSAVE64)>;
1537
1538 def SKLWriteResGroup214 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
1539   let Latency = 42;
1540   let NumMicroOps = 22;
1541   let ReleaseAtCycles = [2,20];
1542 }
1543 def: InstRW<[SKLWriteResGroup214], (instrs RDTSCP)>;
1544
1545 def SKLWriteResGroup215 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1546   let Latency = 42;
1547   let NumMicroOps = 40;
1548   let ReleaseAtCycles = [1,11,1,1,26];
1549 }
1550 def: InstRW<[SKLWriteResGroup215], (instrs XSAVE)>;
1551 def: InstRW<[SKLWriteResGroup215], (instregex "XSAVEC", "XSAVES")>;
1552
1553 def SKLWriteResGroup216 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1554   let Latency = 46;
1555   let NumMicroOps = 44;
1556   let ReleaseAtCycles = [1,11,1,1,30];
1557 }
1558 def: InstRW<[SKLWriteResGroup216], (instregex "XSAVEOPT")>;
1559
1560 def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05,SKLPort06,SKLPort0156]> {
1561   let Latency = 62;
1562   let NumMicroOps = 64;
1563   let ReleaseAtCycles = [2,8,5,10,39];
1564 }
1565 def: InstRW<[SKLWriteResGroup217], (instrs FLDENVm)>;
1566
1567 def SKLWriteResGroup218 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
1568   let Latency = 63;
1569   let NumMicroOps = 88;
1570   let ReleaseAtCycles = [4,4,31,1,2,1,45];
1571 }
1572 def: InstRW<[SKLWriteResGroup218], (instrs FXRSTOR64)>;
1573
1574 def SKLWriteResGroup219 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
1575   let Latency = 63;
1576   let NumMicroOps = 90;
1577   let ReleaseAtCycles = [4,2,33,1,2,1,47];
1578 }
1579 def: InstRW<[SKLWriteResGroup219], (instrs FXRSTOR)>;
1580
1581 def SKLWriteResGroup220 : SchedWriteRes<[SKLPort5,SKLPort05,SKLPort0156]> {
1582   let Latency = 75;
1583   let NumMicroOps = 15;
1584   let ReleaseAtCycles = [6,3,6];
1585 }
1586 def: InstRW<[SKLWriteResGroup220], (instrs FNINIT)>;
1587
1588 def SKLWriteResGroup223 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort237,SKLPort06,SKLPort0156]> {
1589   let Latency = 106;
1590   let NumMicroOps = 100;
1591   let ReleaseAtCycles = [9,1,11,16,1,11,21,30];
1592 }
1593 def: InstRW<[SKLWriteResGroup223], (instrs FSTENVm)>;
1594
1595 def: InstRW<[WriteZero], (instrs CLC)>;
1596
1597
1598 // Instruction variants handled by the renamer. These might not need execution
1599 // ports in certain conditions.
1600 // See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",
1601 // section "Skylake Pipeline" > "Register allocation and renaming".
1602 // These can be investigated with llvm-exegesis, e.g.
1603 // echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1604 // echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1605
1606 def SKLWriteZeroLatency : SchedWriteRes<[]> {
1607   let Latency = 0;
1608 }
1609
1610 def SKLWriteZeroIdiom : SchedWriteVariant<[
1611     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1612     SchedVar<NoSchedPred,                          [WriteALU]>
1613 ]>;
1614 def : InstRW<[SKLWriteZeroIdiom], (instrs SUB32rr, SUB64rr,
1615                                           XOR32rr, XOR64rr)>;
1616
1617 def SKLWriteFZeroIdiom : SchedWriteVariant<[
1618     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1619     SchedVar<NoSchedPred,                          [WriteFLogic]>
1620 ]>;
1621 def : InstRW<[SKLWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr,
1622                                            VXORPDrr)>;
1623
1624 def SKLWriteFZeroIdiomY : SchedWriteVariant<[
1625     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1626     SchedVar<NoSchedPred,                          [WriteFLogicY]>
1627 ]>;
1628 def : InstRW<[SKLWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>;
1629
1630 def SKLWriteVZeroIdiomLogicX : SchedWriteVariant<[
1631     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1632     SchedVar<NoSchedPred,                          [WriteVecLogicX]>
1633 ]>;
1634 def : InstRW<[SKLWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>;
1635
1636 def SKLWriteVZeroIdiomLogicY : SchedWriteVariant<[
1637     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1638     SchedVar<NoSchedPred,                          [WriteVecLogicY]>
1639 ]>;
1640 def : InstRW<[SKLWriteVZeroIdiomLogicY], (instrs VPXORYrr)>;
1641
1642 def SKLWriteVZeroIdiomALUX : SchedWriteVariant<[
1643     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1644     SchedVar<NoSchedPred,                          [WriteVecALUX]>
1645 ]>;
1646 def : InstRW<[SKLWriteVZeroIdiomALUX], (instrs PCMPGTBrr, VPCMPGTBrr,
1647                                                PCMPGTDrr, VPCMPGTDrr,
1648                                                PCMPGTWrr, VPCMPGTWrr)>;
1649
1650 def SKLWriteVZeroIdiomALUY : SchedWriteVariant<[
1651     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1652     SchedVar<NoSchedPred,                          [WriteVecALUY]>
1653 ]>;
1654 def : InstRW<[SKLWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr,
1655                                                VPCMPGTDYrr,
1656                                                VPCMPGTWYrr)>;
1657
1658 def SKLWritePSUB : SchedWriteRes<[SKLPort015]> {
1659   let Latency = 1;
1660   let NumMicroOps = 1;
1661   let ReleaseAtCycles = [1];
1662 }
1663
1664 def SKLWriteVZeroIdiomPSUB : SchedWriteVariant<[
1665     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1666     SchedVar<NoSchedPred,                          [SKLWritePSUB]>
1667 ]>;
1668 def : InstRW<[SKLWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr,
1669                                                PSUBDrr, VPSUBDrr,
1670                                                PSUBQrr, VPSUBQrr,
1671                                                PSUBWrr, VPSUBWrr,
1672                                                VPSUBBYrr,
1673                                                VPSUBDYrr,
1674                                                VPSUBQYrr,
1675                                                VPSUBWYrr)>;
1676
1677 def SKLWritePCMPGTQ : SchedWriteRes<[SKLPort5]> {
1678   let Latency = 3;
1679   let NumMicroOps = 1;
1680   let ReleaseAtCycles = [1];
1681 }
1682
1683 def SKLWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
1684     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1685     SchedVar<NoSchedPred,                          [SKLWritePCMPGTQ]>
1686 ]>;
1687 def : InstRW<[SKLWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,
1688                                                   VPCMPGTQYrr)>;
1689
1690
1691 // CMOVs that use both Z and C flag require an extra uop.
1692 def SKLWriteCMOVA_CMOVBErr : SchedWriteRes<[SKLPort06]> {
1693   let Latency = 2;
1694   let ReleaseAtCycles = [2];
1695   let NumMicroOps = 2;
1696 }
1697
1698 def SKLWriteCMOVA_CMOVBErm : SchedWriteRes<[SKLPort23,SKLPort06]> {
1699   let Latency = 7;
1700   let ReleaseAtCycles = [1,2];
1701   let NumMicroOps = 3;
1702 }
1703
1704 def SKLCMOVA_CMOVBErr :  SchedWriteVariant<[
1705   SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SKLWriteCMOVA_CMOVBErr]>,
1706   SchedVar<NoSchedPred,                             [WriteCMOV]>
1707 ]>;
1708
1709 def SKLCMOVA_CMOVBErm :  SchedWriteVariant<[
1710   SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SKLWriteCMOVA_CMOVBErm]>,
1711   SchedVar<NoSchedPred,                             [WriteCMOV.Folded]>
1712 ]>;
1713
1714 def : InstRW<[SKLCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
1715 def : InstRW<[SKLCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
1716
1717 // SETCCs that use both Z and C flag require an extra uop.
1718 def SKLWriteSETA_SETBEr : SchedWriteRes<[SKLPort06]> {
1719   let Latency = 2;
1720   let ReleaseAtCycles = [2];
1721   let NumMicroOps = 2;
1722 }
1723
1724 def SKLWriteSETA_SETBEm : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {
1725   let Latency = 3;
1726   let ReleaseAtCycles = [1,1,2];
1727   let NumMicroOps = 4;
1728 }
1729
1730 def SKLSETA_SETBErr :  SchedWriteVariant<[
1731   SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SKLWriteSETA_SETBEr]>,
1732   SchedVar<NoSchedPred,                         [WriteSETCC]>
1733 ]>;
1734
1735 def SKLSETA_SETBErm :  SchedWriteVariant<[
1736   SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SKLWriteSETA_SETBEm]>,
1737   SchedVar<NoSchedPred,                         [WriteSETCCStore]>
1738 ]>;
1739
1740 def : InstRW<[SKLSETA_SETBErr], (instrs SETCCr)>;
1741 def : InstRW<[SKLSETA_SETBErm], (instrs SETCCm)>;
1742
1743 ///////////////////////////////////////////////////////////////////////////////
1744 // Dependency breaking instructions.
1745 ///////////////////////////////////////////////////////////////////////////////
1746
1747 def : IsZeroIdiomFunction<[
1748   // GPR Zero-idioms.
1749   DepBreakingClass<[ SUB32rr, SUB64rr, XOR32rr, XOR64rr ], ZeroIdiomPredicate>,
1750
1751   // SSE Zero-idioms.
1752   DepBreakingClass<[
1753     // fp variants.
1754     XORPSrr, XORPDrr,
1755
1756     // int variants.
1757     PXORrr,
1758     PSUBBrr, PSUBWrr, PSUBDrr, PSUBQrr,
1759     PCMPGTBrr, PCMPGTDrr, PCMPGTQrr, PCMPGTWrr
1760   ], ZeroIdiomPredicate>,
1761
1762   // AVX Zero-idioms.
1763   DepBreakingClass<[
1764     // xmm fp variants.
1765     VXORPSrr, VXORPDrr,
1766
1767     // xmm int variants.
1768     VPXORrr,
1769     VPSUBBrr, VPSUBWrr, VPSUBDrr, VPSUBQrr,
1770     VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr,
1771
1772     // ymm variants.
1773     VXORPSYrr, VXORPDYrr, VPXORYrr,
1774     VPSUBBYrr, VPSUBWYrr, VPSUBDYrr, VPSUBQYrr,
1775     VPCMPGTBYrr, VPCMPGTWYrr, VPCMPGTDYrr, VPCMPGTQYrr
1776   ], ZeroIdiomPredicate>,
1777 ]>;
1778
1779 } // SchedModel