llvm/lib/Target/AArch64/AArch64SchedA53.td

   1 //==- AArch64SchedA53.td - Cortex-A53 Scheduling Definitions -*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the itinerary class data for the ARM Cortex A53 processors.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 // ===---------------------------------------------------------------------===//
  14 // The following definitions describe the simpler per-operand machine model.
  15 // This works with MachineScheduler. See MCSchedule.h for details.
  16
  17 // Cortex-A53 machine model for scheduling and other instruction cost heuristics.
  18 def CortexA53Model : SchedMachineModel {
  19   let MicroOpBufferSize = 0; // Explicitly set to zero since A53 is in-order.
  20   let IssueWidth = 2;        // 2 micro-ops are dispatched per cycle.
  21   let LoadLatency = 3;       // Optimistic load latency assuming bypass.
  22                              // This is overriden by OperandCycles if the
  23                              // Itineraries are queried instead.
  24   let MispredictPenalty = 9; // Based on "Cortex-A53 Software Optimisation
  25                              // Specification - Instruction Timings"
  26                              // v 1.0 Spreadsheet
  27   let CompleteModel = 1;
  28
  29   list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
  30                                                     PAUnsupported.F,
  31                                                     SMEUnsupported.F);
  32 }
  33
  34
  35 //===----------------------------------------------------------------------===//
  36 // Define each kind of processor resource and number available.
  37
  38 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
  39 // Cortex-A53 is in-order.
  40
  41 def A53UnitALU    : ProcResource<2> { let BufferSize = 0; } // Int ALU
  42 def A53UnitMAC    : ProcResource<1> { let BufferSize = 0; } // Int MAC
  43 def A53UnitDiv    : ProcResource<1> { let BufferSize = 0; } // Int Division
  44 def A53UnitLdSt   : ProcResource<1> { let BufferSize = 0; } // Load/Store
  45 def A53UnitB      : ProcResource<1> { let BufferSize = 0; } // Branch
  46 def A53UnitFPALU  : ProcResource<1> { let BufferSize = 0; } // FP ALU
  47 def A53UnitFPMDS  : ProcResource<1> { let BufferSize = 0; } // FP Mult/Div/Sqrt
  48
  49
  50 //===----------------------------------------------------------------------===//
  51 // Subtarget-specific SchedWrite types which both map the ProcResources and
  52 // set the latency.
  53
  54 let SchedModel = CortexA53Model in {
  55
  56 // ALU - Despite having a full latency of 4, most of the ALU instructions can
  57 //       forward a cycle earlier and then two cycles earlier in the case of a
  58 //       shift-only instruction. These latencies will be incorrect when the
  59 //       result cannot be forwarded, but modeling isn't rocket surgery.
  60 def : WriteRes<WriteImm, [A53UnitALU]> { let Latency = 3; }
  61 def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; }
  62 def : WriteRes<WriteISReg, [A53UnitALU]> { let Latency = 3; }
  63 def : WriteRes<WriteIEReg, [A53UnitALU]> { let Latency = 3; }
  64 def : WriteRes<WriteIS, [A53UnitALU]> { let Latency = 2; }
  65 def : WriteRes<WriteExtr, [A53UnitALU]> { let Latency = 3; }
  66
  67 // MAC
  68 def : WriteRes<WriteIM32, [A53UnitMAC]> { let Latency = 4; }
  69 def : WriteRes<WriteIM64, [A53UnitMAC]> { let Latency = 4; }
  70
  71 // Div
  72 def : WriteRes<WriteID32, [A53UnitDiv]> { let Latency = 4; }
  73 def : WriteRes<WriteID64, [A53UnitDiv]> { let Latency = 4; }
  74
  75 // Load
  76 def : WriteRes<WriteLD, [A53UnitLdSt]> { let Latency = 4; }
  77 def : WriteRes<WriteLDIdx, [A53UnitLdSt]> { let Latency = 4; }
  78 def : WriteRes<WriteLDHi, [A53UnitLdSt]> { let Latency = 4; }
  79
  80 // Vector Load - Vector loads take 1-5 cycles to issue. For the WriteVecLd
  81 //               below, choosing the median of 3 which makes the latency 6.
  82 //               May model this more carefully in the future. The remaining
  83 //               A53WriteVLD# types represent the 1-5 cycle issues explicitly.
  84 def : WriteRes<WriteVLD, [A53UnitLdSt]> { let Latency = 6;
  85                                           let ResourceCycles = [3]; }
  86 def A53WriteVLD1 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 4; }
  87 def A53WriteVLD2 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 5;
  88                                                   let ResourceCycles = [2]; }
  89 def A53WriteVLD3 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 6;
  90                                                   let ResourceCycles = [3]; }
  91 def A53WriteVLD4 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 7;
  92                                                   let ResourceCycles = [4]; }
  93 def A53WriteVLD5 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 8;
  94                                                   let ResourceCycles = [5]; }
  95
  96 // Pre/Post Indexing - Performed as part of address generation which is already
  97 //                     accounted for in the WriteST* latencies below
  98 def : WriteRes<WriteAdr, []> { let Latency = 0; }
  99
 100 // Store
 101 def : WriteRes<WriteST, [A53UnitLdSt]> { let Latency = 4; }
 102 def : WriteRes<WriteSTP, [A53UnitLdSt]> { let Latency = 4; }
 103 def : WriteRes<WriteSTIdx, [A53UnitLdSt]> { let Latency = 4; }
 104 def : WriteRes<WriteSTX, [A53UnitLdSt]> { let Latency = 4; }
 105
 106 // Vector Store - Similar to vector loads, can take 1-3 cycles to issue.
 107 def : WriteRes<WriteVST, [A53UnitLdSt]> { let Latency = 5;
 108                                           let ResourceCycles = [2];}
 109 def A53WriteVST1 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 4; }
 110 def A53WriteVST2 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 5;
 111                                                   let ResourceCycles = [2]; }
 112 def A53WriteVST3 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 6;
 113                                                   let ResourceCycles = [3]; }
 114
 115 def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
 116
 117 // Branch
 118 def : WriteRes<WriteBr, [A53UnitB]>;
 119 def : WriteRes<WriteBrReg, [A53UnitB]>;
 120 def : WriteRes<WriteSys, [A53UnitB]>;
 121 def : WriteRes<WriteBarrier, [A53UnitB]>;
 122 def : WriteRes<WriteHint, [A53UnitB]>;
 123
 124 // FP ALU
 125 def : WriteRes<WriteF, [A53UnitFPALU]> { let Latency = 6; }
 126 def : WriteRes<WriteFCmp, [A53UnitFPALU]> { let Latency = 6; }
 127 def : WriteRes<WriteFCvt, [A53UnitFPALU]> { let Latency = 6; }
 128 def : WriteRes<WriteFCopy, [A53UnitFPALU]> { let Latency = 6; }
 129 def : WriteRes<WriteFImm, [A53UnitFPALU]> { let Latency = 6; }
 130 def : WriteRes<WriteVd, [A53UnitFPALU]> { let Latency = 6; }
 131 def : WriteRes<WriteVq, [A53UnitFPALU]> { let Latency = 6; }
 132
 133 // FP Mul, Div, Sqrt
 134 def : WriteRes<WriteFMul, [A53UnitFPMDS]> { let Latency = 6; }
 135 def : WriteRes<WriteFDiv, [A53UnitFPMDS]> { let Latency = 33;
 136                                             let ResourceCycles = [29]; }
 137 def A53WriteFMAC : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 10; }
 138 def A53WriteFDivSP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 18;
 139                                                      let ResourceCycles = [14]; }
 140 def A53WriteFDivDP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 33;
 141                                                      let ResourceCycles = [29]; }
 142 def A53WriteFSqrtSP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 17;
 143                                                       let ResourceCycles = [13]; }
 144 def A53WriteFSqrtDP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 32;
 145                                                       let ResourceCycles = [28]; }
 146
 147 //===----------------------------------------------------------------------===//
 148 // Subtarget-specific SchedRead types.
 149
 150 // No forwarding for these reads.
 151 def : ReadAdvance<ReadExtrHi, 0>;
 152 def : ReadAdvance<ReadAdrBase, 0>;
 153 def : ReadAdvance<ReadST, 0>;
 154 def : ReadAdvance<ReadVLD, 0>;
 155
 156 // ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable
 157 //       operands are needed one cycle later if and only if they are to be
 158 //       shifted. Otherwise, they too are needed two cycles later. This same
 159 //       ReadAdvance applies to Extended registers as well, even though there is
 160 //       a separate SchedPredicate for them.
 161 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
 162                              WriteISReg, WriteIEReg,WriteIS,
 163                              WriteID32,WriteID64,
 164                              WriteIM32,WriteIM64]>;
 165 def A53ReadShifted : SchedReadAdvance<1, [WriteImm,WriteI,
 166                                           WriteISReg, WriteIEReg,WriteIS,
 167                                           WriteID32,WriteID64,
 168                                           WriteIM32,WriteIM64]>;
 169 def A53ReadNotShifted : SchedReadAdvance<2, [WriteImm,WriteI,
 170                                              WriteISReg, WriteIEReg,WriteIS,
 171                                              WriteID32,WriteID64,
 172                                              WriteIM32,WriteIM64]>;
 173 def A53ReadISReg : SchedReadVariant<[
 174         SchedVar<RegShiftedPred, [A53ReadShifted]>,
 175         SchedVar<NoSchedPred, [A53ReadNotShifted]>]>;
 176 def : SchedAlias<ReadISReg, A53ReadISReg>;
 177
 178 def A53ReadIEReg : SchedReadVariant<[
 179         SchedVar<RegExtendedPred, [A53ReadShifted]>,
 180         SchedVar<NoSchedPred, [A53ReadNotShifted]>]>;
 181 def : SchedAlias<ReadIEReg, A53ReadIEReg>;
 182
 183 // MAC - Operands are generally needed one cycle later in the MAC pipe.
 184 //       Accumulator operands are needed two cycles later.
 185 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
 186                               WriteISReg, WriteIEReg,WriteIS,
 187                               WriteID32,WriteID64,
 188                               WriteIM32,WriteIM64]>;
 189 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
 190                                WriteISReg, WriteIEReg,WriteIS,
 191                                WriteID32,WriteID64,
 192                                WriteIM32,WriteIM64]>;
 193
 194 // Div
 195 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
 196                               WriteISReg, WriteIEReg,WriteIS,
 197                               WriteID32,WriteID64,
 198                               WriteIM32,WriteIM64]>;
 199
 200 //===----------------------------------------------------------------------===//
 201 // Subtarget-specific InstRWs.
 202
 203 //---
 204 // Miscellaneous
 205 //---
 206 def : InstRW<[WriteI], (instrs COPY)>;
 207
 208 //---
 209 // Vector Loads
 210 //---
 211 def : InstRW<[A53WriteVLD1], (instregex "LD1i(8|16|32|64)$")>;
 212 def : InstRW<[A53WriteVLD1], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 213 def : InstRW<[A53WriteVLD1], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 214 def : InstRW<[A53WriteVLD2], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 215 def : InstRW<[A53WriteVLD3], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 216 def : InstRW<[A53WriteVLD4], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 217 def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD1i(8|16|32|64)_POST$")>;
 218 def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 219 def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 220 def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 221 def : InstRW<[A53WriteVLD3, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 222 def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 223
 224 def : InstRW<[A53WriteVLD1], (instregex "LD2i(8|16|32|64)$")>;
 225 def : InstRW<[A53WriteVLD1], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 226 def : InstRW<[A53WriteVLD2], (instregex "LD2Twov(8b|4h|2s)$")>;
 227 def : InstRW<[A53WriteVLD4], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
 228 def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD2i(8|16|32|64)_POST$")>;
 229 def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 230 def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD2Twov(8b|4h|2s)_POST$")>;
 231 def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>;
 232
 233 def : InstRW<[A53WriteVLD2], (instregex "LD3i(8|16|32|64)$")>;
 234 def : InstRW<[A53WriteVLD2], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 235 def : InstRW<[A53WriteVLD4], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)$")>;
 236 def : InstRW<[A53WriteVLD3], (instregex "LD3Threev2d$")>;
 237 def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD3i(8|16|32|64)_POST$")>;
 238 def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 239 def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
 240 def : InstRW<[A53WriteVLD3, WriteAdr], (instregex "LD3Threev2d_POST$")>;
 241
 242 def : InstRW<[A53WriteVLD2], (instregex "LD4i(8|16|32|64)$")>;
 243 def : InstRW<[A53WriteVLD2], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 244 def : InstRW<[A53WriteVLD5], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>;
 245 def : InstRW<[A53WriteVLD4], (instregex "LD4Fourv(2d)$")>;
 246 def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD4i(8|16|32|64)_POST$")>;
 247 def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 248 def : InstRW<[A53WriteVLD5, WriteAdr], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
 249 def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD4Fourv(2d)_POST$")>;
 250
 251 //---
 252 // Vector Stores
 253 //---
 254 def : InstRW<[A53WriteVST1], (instregex "ST1i(8|16|32|64)$")>;
 255 def : InstRW<[A53WriteVST1], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 256 def : InstRW<[A53WriteVST1], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 257 def : InstRW<[A53WriteVST2], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 258 def : InstRW<[A53WriteVST2], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
 259 def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST1i(8|16|32|64)_POST$")>;
 260 def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 261 def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 262 def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 263 def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
 264
 265 def : InstRW<[A53WriteVST1], (instregex "ST2i(8|16|32|64)$")>;
 266 def : InstRW<[A53WriteVST1], (instregex "ST2Twov(8b|4h|2s)$")>;
 267 def : InstRW<[A53WriteVST2], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
 268 def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST2i(8|16|32|64)_POST$")>;
 269 def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
 270 def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
 271
 272 def : InstRW<[A53WriteVST2], (instregex "ST3i(8|16|32|64)$")>;
 273 def : InstRW<[A53WriteVST3], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)$")>;
 274 def : InstRW<[A53WriteVST2], (instregex "ST3Threev(2d)$")>;
 275 def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST3i(8|16|32|64)_POST$")>;
 276 def : InstRW<[A53WriteVST3, WriteAdr], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
 277 def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST3Threev(2d)_POST$")>;
 278
 279 def : InstRW<[A53WriteVST2], (instregex "ST4i(8|16|32|64)$")>;
 280 def : InstRW<[A53WriteVST3], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>;
 281 def : InstRW<[A53WriteVST2], (instregex "ST4Fourv(2d)$")>;
 282 def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST4i(8|16|32|64)_POST$")>;
 283 def : InstRW<[A53WriteVST3, WriteAdr], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
 284 def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>;
 285
 286 //---
 287 // Floating Point MAC, DIV, SQRT
 288 //---
 289 def : InstRW<[A53WriteFMAC], (instregex "^FN?M(ADD|SUB).*")>;
 290 def : InstRW<[A53WriteFMAC], (instregex "^FML(A|S).*")>;
 291 def : InstRW<[A53WriteFDivSP], (instrs FDIVSrr)>;
 292 def : InstRW<[A53WriteFDivDP], (instrs FDIVDrr)>;
 293 def : InstRW<[A53WriteFDivSP], (instregex "^FDIVv.*32$")>;
 294 def : InstRW<[A53WriteFDivDP], (instregex "^FDIVv.*64$")>;
 295 def : InstRW<[A53WriteFSqrtSP], (instregex "^.*SQRT.*32$")>;
 296 def : InstRW<[A53WriteFSqrtDP], (instregex "^.*SQRT.*64$")>;
 297
 298 }