| blob | 47de57a68be96a42cb6e46eae30af8c96854707d |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3 ; RUN: llc -mtriple=aarch64-unknown-linux-gnu -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
5 define <8 x i8> @and8xi8(<8 x i8> %a, <8 x i8> %b) {
6 ; CHECK-LABEL: and8xi8:
7 ; CHECK: // %bb.0:
8 ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
9 ; CHECK-NEXT: ret
10 %tmp1 = and <8 x i8> %a, %b;
11 ret <8 x i8> %tmp1
12 }
14 define <16 x i8> @and16xi8(<16 x i8> %a, <16 x i8> %b) {
15 ; CHECK-LABEL: and16xi8:
16 ; CHECK: // %bb.0:
17 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
18 ; CHECK-NEXT: ret
19 %tmp1 = and <16 x i8> %a, %b;
20 ret <16 x i8> %tmp1
21 }
24 define <8 x i8> @orr8xi8(<8 x i8> %a, <8 x i8> %b) {
25 ; CHECK-LABEL: orr8xi8:
26 ; CHECK: // %bb.0:
27 ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
28 ; CHECK-NEXT: ret
29 %tmp1 = or <8 x i8> %a, %b;
30 ret <8 x i8> %tmp1
31 }
33 define <16 x i8> @orr16xi8(<16 x i8> %a, <16 x i8> %b) {
34 ; CHECK-LABEL: orr16xi8:
35 ; CHECK: // %bb.0:
36 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
37 ; CHECK-NEXT: ret
38 %tmp1 = or <16 x i8> %a, %b;
39 ret <16 x i8> %tmp1
40 }
43 define <8 x i8> @xor8xi8(<8 x i8> %a, <8 x i8> %b) {
44 ; CHECK-LABEL: xor8xi8:
45 ; CHECK: // %bb.0:
46 ; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
47 ; CHECK-NEXT: ret
48 %tmp1 = xor <8 x i8> %a, %b;
49 ret <8 x i8> %tmp1
50 }
52 define <16 x i8> @xor16xi8(<16 x i8> %a, <16 x i8> %b) {
53 ; CHECK-LABEL: xor16xi8:
54 ; CHECK: // %bb.0:
55 ; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
56 ; CHECK-NEXT: ret
57 %tmp1 = xor <16 x i8> %a, %b;
58 ret <16 x i8> %tmp1
59 }
61 define <8 x i8> @bsl8xi8_const(<8 x i8> %a, <8 x i8> %b) {
62 ; CHECK-SD-LABEL: bsl8xi8_const:
63 ; CHECK-SD: // %bb.0:
64 ; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff
65 ; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b
66 ; CHECK-SD-NEXT: ret
67 ;
68 ; CHECK-GI-LABEL: bsl8xi8_const:
69 ; CHECK-GI: // %bb.0:
70 ; CHECK-GI-NEXT: adrp x8, .LCPI6_1
71 ; CHECK-GI-NEXT: adrp x9, .LCPI6_0
72 ; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI6_1]
73 ; CHECK-GI-NEXT: ldr d3, [x9, :lo12:.LCPI6_0]
74 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v2.8b
75 ; CHECK-GI-NEXT: and v1.8b, v1.8b, v3.8b
76 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
77 ; CHECK-GI-NEXT: ret
78 %tmp1 = and <8 x i8> %a, < i8 -1, i8 -1, i8 0, i8 0, i8 -1, i8 -1, i8 0, i8 0 >
79 %tmp2 = and <8 x i8> %b, < i8 0, i8 0, i8 -1, i8 -1, i8 0, i8 0, i8 -1, i8 -1 >
80 %tmp3 = or <8 x i8> %tmp1, %tmp2
81 ret <8 x i8> %tmp3
82 }
84 define <16 x i8> @bsl16xi8_const(<16 x i8> %a, <16 x i8> %b) {
85 ; CHECK-SD-LABEL: bsl16xi8_const:
86 ; CHECK-SD: // %bb.0:
87 ; CHECK-SD-NEXT: movi v2.2d, #0x000000ffffffff
88 ; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b
89 ; CHECK-SD-NEXT: ret
90 ;
91 ; CHECK-GI-LABEL: bsl16xi8_const:
92 ; CHECK-GI: // %bb.0:
93 ; CHECK-GI-NEXT: adrp x8, .LCPI7_1
94 ; CHECK-GI-NEXT: adrp x9, .LCPI7_0
95 ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI7_1]
96 ; CHECK-GI-NEXT: ldr q3, [x9, :lo12:.LCPI7_0]
97 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b
98 ; CHECK-GI-NEXT: and v1.16b, v1.16b, v3.16b
99 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
100 ; CHECK-GI-NEXT: ret
101 %tmp1 = and <16 x i8> %a, < i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0 >
102 %tmp2 = and <16 x i8> %b, < i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1 >
103 %tmp3 = or <16 x i8> %tmp1, %tmp2
104 ret <16 x i8> %tmp3
105 }
107 define <8 x i8> @orn8xi8(<8 x i8> %a, <8 x i8> %b) {
108 ; CHECK-LABEL: orn8xi8:
109 ; CHECK: // %bb.0:
110 ; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b
111 ; CHECK-NEXT: ret
112 %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
113 %tmp2 = or <8 x i8> %a, %tmp1
114 ret <8 x i8> %tmp2
115 }
117 define <16 x i8> @orn16xi8(<16 x i8> %a, <16 x i8> %b) {
118 ; CHECK-LABEL: orn16xi8:
119 ; CHECK: // %bb.0:
120 ; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b
121 ; CHECK-NEXT: ret
122 %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
123 %tmp2 = or <16 x i8> %a, %tmp1
124 ret <16 x i8> %tmp2
125 }
127 define <8 x i8> @bic8xi8(<8 x i8> %a, <8 x i8> %b) {
128 ; CHECK-LABEL: bic8xi8:
129 ; CHECK: // %bb.0:
130 ; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b
131 ; CHECK-NEXT: ret
132 %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
133 %tmp2 = and <8 x i8> %a, %tmp1
134 ret <8 x i8> %tmp2
135 }
137 define <16 x i8> @bic16xi8(<16 x i8> %a, <16 x i8> %b) {
138 ; CHECK-LABEL: bic16xi8:
139 ; CHECK: // %bb.0:
140 ; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b
141 ; CHECK-NEXT: ret
142 %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
143 %tmp2 = and <16 x i8> %a, %tmp1
144 ret <16 x i8> %tmp2
145 }
147 define <2 x i32> @orrimm2s_lsl0(<2 x i32> %a) {
148 ; CHECK-SD-LABEL: orrimm2s_lsl0:
149 ; CHECK-SD: // %bb.0:
150 ; CHECK-SD-NEXT: orr v0.2s, #255
151 ; CHECK-SD-NEXT: ret
152 ;
153 ; CHECK-GI-LABEL: orrimm2s_lsl0:
154 ; CHECK-GI: // %bb.0:
155 ; CHECK-GI-NEXT: adrp x8, .LCPI12_0
156 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI12_0]
157 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
158 ; CHECK-GI-NEXT: ret
159 %tmp1 = or <2 x i32> %a, < i32 255, i32 255>
160 ret <2 x i32> %tmp1
161 }
163 define <2 x i32> @orrimm2s_lsl8(<2 x i32> %a) {
164 ; CHECK-SD-LABEL: orrimm2s_lsl8:
165 ; CHECK-SD: // %bb.0:
166 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #8
167 ; CHECK-SD-NEXT: ret
168 ;
169 ; CHECK-GI-LABEL: orrimm2s_lsl8:
170 ; CHECK-GI: // %bb.0:
171 ; CHECK-GI-NEXT: adrp x8, .LCPI13_0
172 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI13_0]
173 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
174 ; CHECK-GI-NEXT: ret
175 %tmp1 = or <2 x i32> %a, < i32 65280, i32 65280>
176 ret <2 x i32> %tmp1
177 }
179 define <2 x i32> @orrimm2s_lsl16(<2 x i32> %a) {
180 ; CHECK-SD-LABEL: orrimm2s_lsl16:
181 ; CHECK-SD: // %bb.0:
182 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #16
183 ; CHECK-SD-NEXT: ret
184 ;
185 ; CHECK-GI-LABEL: orrimm2s_lsl16:
186 ; CHECK-GI: // %bb.0:
187 ; CHECK-GI-NEXT: adrp x8, .LCPI14_0
188 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI14_0]
189 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
190 ; CHECK-GI-NEXT: ret
191 %tmp1 = or <2 x i32> %a, < i32 16711680, i32 16711680>
192 ret <2 x i32> %tmp1
193 }
195 define <2 x i32> @orrimm2s_lsl24(<2 x i32> %a) {
196 ; CHECK-SD-LABEL: orrimm2s_lsl24:
197 ; CHECK-SD: // %bb.0:
198 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #24
199 ; CHECK-SD-NEXT: ret
200 ;
201 ; CHECK-GI-LABEL: orrimm2s_lsl24:
202 ; CHECK-GI: // %bb.0:
203 ; CHECK-GI-NEXT: adrp x8, .LCPI15_0
204 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI15_0]
205 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
206 ; CHECK-GI-NEXT: ret
207 %tmp1 = or <2 x i32> %a, < i32 4278190080, i32 4278190080>
208 ret <2 x i32> %tmp1
209 }
211 define <4 x i32> @orrimm4s_lsl0(<4 x i32> %a) {
212 ; CHECK-SD-LABEL: orrimm4s_lsl0:
213 ; CHECK-SD: // %bb.0:
214 ; CHECK-SD-NEXT: orr v0.4s, #255
215 ; CHECK-SD-NEXT: ret
216 ;
217 ; CHECK-GI-LABEL: orrimm4s_lsl0:
218 ; CHECK-GI: // %bb.0:
219 ; CHECK-GI-NEXT: adrp x8, .LCPI16_0
220 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_0]
221 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
222 ; CHECK-GI-NEXT: ret
223 %tmp1 = or <4 x i32> %a, < i32 255, i32 255, i32 255, i32 255>
224 ret <4 x i32> %tmp1
225 }
227 define <4 x i32> @orrimm4s_lsl8(<4 x i32> %a) {
228 ; CHECK-SD-LABEL: orrimm4s_lsl8:
229 ; CHECK-SD: // %bb.0:
230 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #8
231 ; CHECK-SD-NEXT: ret
232 ;
233 ; CHECK-GI-LABEL: orrimm4s_lsl8:
234 ; CHECK-GI: // %bb.0:
235 ; CHECK-GI-NEXT: adrp x8, .LCPI17_0
236 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI17_0]
237 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
238 ; CHECK-GI-NEXT: ret
239 %tmp1 = or <4 x i32> %a, < i32 65280, i32 65280, i32 65280, i32 65280>
240 ret <4 x i32> %tmp1
241 }
243 define <4 x i32> @orrimm4s_lsl16(<4 x i32> %a) {
244 ; CHECK-SD-LABEL: orrimm4s_lsl16:
245 ; CHECK-SD: // %bb.0:
246 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #16
247 ; CHECK-SD-NEXT: ret
248 ;
249 ; CHECK-GI-LABEL: orrimm4s_lsl16:
250 ; CHECK-GI: // %bb.0:
251 ; CHECK-GI-NEXT: adrp x8, .LCPI18_0
252 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI18_0]
253 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
254 ; CHECK-GI-NEXT: ret
255 %tmp1 = or <4 x i32> %a, < i32 16711680, i32 16711680, i32 16711680, i32 16711680>
256 ret <4 x i32> %tmp1
257 }
259 define <4 x i32> @orrimm4s_lsl24(<4 x i32> %a) {
260 ; CHECK-SD-LABEL: orrimm4s_lsl24:
261 ; CHECK-SD: // %bb.0:
262 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #24
263 ; CHECK-SD-NEXT: ret
264 ;
265 ; CHECK-GI-LABEL: orrimm4s_lsl24:
266 ; CHECK-GI: // %bb.0:
267 ; CHECK-GI-NEXT: adrp x8, .LCPI19_0
268 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI19_0]
269 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
270 ; CHECK-GI-NEXT: ret
271 %tmp1 = or <4 x i32> %a, < i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080>
272 ret <4 x i32> %tmp1
273 }
275 define <4 x i16> @orrimm4h_lsl0(<4 x i16> %a) {
276 ; CHECK-SD-LABEL: orrimm4h_lsl0:
277 ; CHECK-SD: // %bb.0:
278 ; CHECK-SD-NEXT: orr v0.4h, #255
279 ; CHECK-SD-NEXT: ret
280 ;
281 ; CHECK-GI-LABEL: orrimm4h_lsl0:
282 ; CHECK-GI: // %bb.0:
283 ; CHECK-GI-NEXT: adrp x8, .LCPI20_0
284 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI20_0]
285 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
286 ; CHECK-GI-NEXT: ret
287 %tmp1 = or <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255 >
288 ret <4 x i16> %tmp1
289 }
291 define <4 x i16> @orrimm4h_lsl8(<4 x i16> %a) {
292 ; CHECK-SD-LABEL: orrimm4h_lsl8:
293 ; CHECK-SD: // %bb.0:
294 ; CHECK-SD-NEXT: orr v0.4h, #255, lsl #8
295 ; CHECK-SD-NEXT: ret
296 ;
297 ; CHECK-GI-LABEL: orrimm4h_lsl8:
298 ; CHECK-GI: // %bb.0:
299 ; CHECK-GI-NEXT: adrp x8, .LCPI21_0
300 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI21_0]
301 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
302 ; CHECK-GI-NEXT: ret
303 %tmp1 = or <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 >
304 ret <4 x i16> %tmp1
305 }
307 define <8 x i16> @orrimm8h_lsl0(<8 x i16> %a) {
308 ; CHECK-SD-LABEL: orrimm8h_lsl0:
309 ; CHECK-SD: // %bb.0:
310 ; CHECK-SD-NEXT: orr v0.8h, #255
311 ; CHECK-SD-NEXT: ret
312 ;
313 ; CHECK-GI-LABEL: orrimm8h_lsl0:
314 ; CHECK-GI: // %bb.0:
315 ; CHECK-GI-NEXT: adrp x8, .LCPI22_0
316 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI22_0]
317 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
318 ; CHECK-GI-NEXT: ret
319 %tmp1 = or <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255 >
320 ret <8 x i16> %tmp1
321 }
323 define <8 x i16> @orrimm8h_lsl8(<8 x i16> %a) {
324 ; CHECK-SD-LABEL: orrimm8h_lsl8:
325 ; CHECK-SD: // %bb.0:
326 ; CHECK-SD-NEXT: orr v0.8h, #255, lsl #8
327 ; CHECK-SD-NEXT: ret
328 ;
329 ; CHECK-GI-LABEL: orrimm8h_lsl8:
330 ; CHECK-GI: // %bb.0:
331 ; CHECK-GI-NEXT: adrp x8, .LCPI23_0
332 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI23_0]
333 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
334 ; CHECK-GI-NEXT: ret
335 %tmp1 = or <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
336 ret <8 x i16> %tmp1
337 }
339 define <2 x i32> @bicimm2s_lsl0(<2 x i32> %a) {
340 ; CHECK-SD-LABEL: bicimm2s_lsl0:
341 ; CHECK-SD: // %bb.0:
342 ; CHECK-SD-NEXT: bic v0.2s, #16
343 ; CHECK-SD-NEXT: ret
344 ;
345 ; CHECK-GI-LABEL: bicimm2s_lsl0:
346 ; CHECK-GI: // %bb.0:
347 ; CHECK-GI-NEXT: adrp x8, .LCPI24_0
348 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI24_0]
349 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
350 ; CHECK-GI-NEXT: ret
351 %tmp1 = and <2 x i32> %a, < i32 4294967279, i32 4294967279 >
352 ret <2 x i32> %tmp1
353 }
355 define <2 x i32> @bicimm2s_lsl8(<2 x i32> %a) {
356 ; CHECK-SD-LABEL: bicimm2s_lsl8:
357 ; CHECK-SD: // %bb.0:
358 ; CHECK-SD-NEXT: bic v0.2s, #16, lsl #8
359 ; CHECK-SD-NEXT: ret
360 ;
361 ; CHECK-GI-LABEL: bicimm2s_lsl8:
362 ; CHECK-GI: // %bb.0:
363 ; CHECK-GI-NEXT: adrp x8, .LCPI25_0
364 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI25_0]
365 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
366 ; CHECK-GI-NEXT: ret
367 %tmp1 = and <2 x i32> %a, < i32 4294963199, i32 4294963199 >
368 ret <2 x i32> %tmp1
369 }
371 define <2 x i32> @bicimm2s_lsl16(<2 x i32> %a) {
372 ; CHECK-SD-LABEL: bicimm2s_lsl16:
373 ; CHECK-SD: // %bb.0:
374 ; CHECK-SD-NEXT: bic v0.2s, #16, lsl #16
375 ; CHECK-SD-NEXT: ret
376 ;
377 ; CHECK-GI-LABEL: bicimm2s_lsl16:
378 ; CHECK-GI: // %bb.0:
379 ; CHECK-GI-NEXT: adrp x8, .LCPI26_0
380 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI26_0]
381 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
382 ; CHECK-GI-NEXT: ret
383 %tmp1 = and <2 x i32> %a, < i32 4293918719, i32 4293918719 >
384 ret <2 x i32> %tmp1
385 }
387 define <2 x i32> @bicimm2s_lsl124(<2 x i32> %a) {
388 ; CHECK-SD-LABEL: bicimm2s_lsl124:
389 ; CHECK-SD: // %bb.0:
390 ; CHECK-SD-NEXT: bic v0.2s, #16, lsl #24
391 ; CHECK-SD-NEXT: ret
392 ;
393 ; CHECK-GI-LABEL: bicimm2s_lsl124:
394 ; CHECK-GI: // %bb.0:
395 ; CHECK-GI-NEXT: adrp x8, .LCPI27_0
396 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI27_0]
397 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
398 ; CHECK-GI-NEXT: ret
399 %tmp1 = and <2 x i32> %a, < i32 4026531839, i32 4026531839>
400 ret <2 x i32> %tmp1
401 }
403 define <4 x i32> @bicimm4s_lsl0(<4 x i32> %a) {
404 ; CHECK-SD-LABEL: bicimm4s_lsl0:
405 ; CHECK-SD: // %bb.0:
406 ; CHECK-SD-NEXT: bic v0.4s, #16
407 ; CHECK-SD-NEXT: ret
408 ;
409 ; CHECK-GI-LABEL: bicimm4s_lsl0:
410 ; CHECK-GI: // %bb.0:
411 ; CHECK-GI-NEXT: adrp x8, .LCPI28_0
412 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI28_0]
413 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
414 ; CHECK-GI-NEXT: ret
415 %tmp1 = and <4 x i32> %a, < i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279 >
416 ret <4 x i32> %tmp1
417 }
419 define <4 x i32> @bicimm4s_lsl8(<4 x i32> %a) {
420 ; CHECK-SD-LABEL: bicimm4s_lsl8:
421 ; CHECK-SD: // %bb.0:
422 ; CHECK-SD-NEXT: bic v0.4s, #16, lsl #8
423 ; CHECK-SD-NEXT: ret
424 ;
425 ; CHECK-GI-LABEL: bicimm4s_lsl8:
426 ; CHECK-GI: // %bb.0:
427 ; CHECK-GI-NEXT: adrp x8, .LCPI29_0
428 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI29_0]
429 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
430 ; CHECK-GI-NEXT: ret
431 %tmp1 = and <4 x i32> %a, < i32 4294963199, i32 4294963199, i32 4294963199, i32 4294963199 >
432 ret <4 x i32> %tmp1
433 }
435 define <4 x i32> @bicimm4s_lsl16(<4 x i32> %a) {
436 ; CHECK-SD-LABEL: bicimm4s_lsl16:
437 ; CHECK-SD: // %bb.0:
438 ; CHECK-SD-NEXT: bic v0.4s, #16, lsl #16
439 ; CHECK-SD-NEXT: ret
440 ;
441 ; CHECK-GI-LABEL: bicimm4s_lsl16:
442 ; CHECK-GI: // %bb.0:
443 ; CHECK-GI-NEXT: adrp x8, .LCPI30_0
444 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_0]
445 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
446 ; CHECK-GI-NEXT: ret
447 %tmp1 = and <4 x i32> %a, < i32 4293918719, i32 4293918719, i32 4293918719, i32 4293918719 >
448 ret <4 x i32> %tmp1
449 }
451 define <4 x i32> @bicimm4s_lsl124(<4 x i32> %a) {
452 ; CHECK-SD-LABEL: bicimm4s_lsl124:
453 ; CHECK-SD: // %bb.0:
454 ; CHECK-SD-NEXT: bic v0.4s, #16, lsl #24
455 ; CHECK-SD-NEXT: ret
456 ;
457 ; CHECK-GI-LABEL: bicimm4s_lsl124:
458 ; CHECK-GI: // %bb.0:
459 ; CHECK-GI-NEXT: adrp x8, .LCPI31_0
460 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI31_0]
461 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
462 ; CHECK-GI-NEXT: ret
463 %tmp1 = and <4 x i32> %a, < i32 4026531839, i32 4026531839, i32 4026531839, i32 4026531839>
464 ret <4 x i32> %tmp1
465 }
467 define <4 x i16> @bicimm4h_lsl0_a(<4 x i16> %a) {
468 ; CHECK-SD-LABEL: bicimm4h_lsl0_a:
469 ; CHECK-SD: // %bb.0:
470 ; CHECK-SD-NEXT: bic v0.4h, #16
471 ; CHECK-SD-NEXT: ret
472 ;
473 ; CHECK-GI-LABEL: bicimm4h_lsl0_a:
474 ; CHECK-GI: // %bb.0:
475 ; CHECK-GI-NEXT: adrp x8, .LCPI32_0
476 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI32_0]
477 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
478 ; CHECK-GI-NEXT: ret
479 %tmp1 = and <4 x i16> %a, < i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279 >
480 ret <4 x i16> %tmp1
481 }
483 define <4 x i16> @bicimm4h_lsl0_b(<4 x i16> %a) {
484 ; CHECK-SD-LABEL: bicimm4h_lsl0_b:
485 ; CHECK-SD: // %bb.0:
486 ; CHECK-SD-NEXT: bic v0.4h, #255
487 ; CHECK-SD-NEXT: ret
488 ;
489 ; CHECK-GI-LABEL: bicimm4h_lsl0_b:
490 ; CHECK-GI: // %bb.0:
491 ; CHECK-GI-NEXT: adrp x8, .LCPI33_0
492 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI33_0]
493 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
494 ; CHECK-GI-NEXT: ret
495 %tmp1 = and <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 >
496 ret <4 x i16> %tmp1
497 }
499 define <4 x i16> @bicimm4h_lsl8_a(<4 x i16> %a) {
500 ; CHECK-SD-LABEL: bicimm4h_lsl8_a:
501 ; CHECK-SD: // %bb.0:
502 ; CHECK-SD-NEXT: bic v0.4h, #16, lsl #8
503 ; CHECK-SD-NEXT: ret
504 ;
505 ; CHECK-GI-LABEL: bicimm4h_lsl8_a:
506 ; CHECK-GI: // %bb.0:
507 ; CHECK-GI-NEXT: adrp x8, .LCPI34_0
508 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI34_0]
509 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
510 ; CHECK-GI-NEXT: ret
511 %tmp1 = and <4 x i16> %a, < i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199>
512 ret <4 x i16> %tmp1
513 }
515 define <4 x i16> @bicimm4h_lsl8_b(<4 x i16> %a) {
516 ; CHECK-SD-LABEL: bicimm4h_lsl8_b:
517 ; CHECK-SD: // %bb.0:
518 ; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
519 ; CHECK-SD-NEXT: ret
520 ;
521 ; CHECK-GI-LABEL: bicimm4h_lsl8_b:
522 ; CHECK-GI: // %bb.0:
523 ; CHECK-GI-NEXT: adrp x8, .LCPI35_0
524 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI35_0]
525 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
526 ; CHECK-GI-NEXT: ret
527 %tmp1 = and <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255>
528 ret <4 x i16> %tmp1
529 }
531 define <8 x i16> @bicimm8h_lsl0_a(<8 x i16> %a) {
532 ; CHECK-SD-LABEL: bicimm8h_lsl0_a:
533 ; CHECK-SD: // %bb.0:
534 ; CHECK-SD-NEXT: bic v0.8h, #16
535 ; CHECK-SD-NEXT: ret
536 ;
537 ; CHECK-GI-LABEL: bicimm8h_lsl0_a:
538 ; CHECK-GI: // %bb.0:
539 ; CHECK-GI-NEXT: adrp x8, .LCPI36_0
540 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI36_0]
541 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
542 ; CHECK-GI-NEXT: ret
543 %tmp1 = and <8 x i16> %a, < i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279,
544 i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279 >
545 ret <8 x i16> %tmp1
546 }
548 define <8 x i16> @bicimm8h_lsl0_b(<8 x i16> %a) {
549 ; CHECK-SD-LABEL: bicimm8h_lsl0_b:
550 ; CHECK-SD: // %bb.0:
551 ; CHECK-SD-NEXT: bic v0.8h, #255
552 ; CHECK-SD-NEXT: ret
553 ;
554 ; CHECK-GI-LABEL: bicimm8h_lsl0_b:
555 ; CHECK-GI: // %bb.0:
556 ; CHECK-GI-NEXT: adrp x8, .LCPI37_0
557 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI37_0]
558 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
559 ; CHECK-GI-NEXT: ret
560 %tmp1 = and <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
561 ret <8 x i16> %tmp1
562 }
564 define <8 x i16> @bicimm8h_lsl8_a(<8 x i16> %a) {
565 ; CHECK-SD-LABEL: bicimm8h_lsl8_a:
566 ; CHECK-SD: // %bb.0:
567 ; CHECK-SD-NEXT: bic v0.8h, #16, lsl #8
568 ; CHECK-SD-NEXT: ret
569 ;
570 ; CHECK-GI-LABEL: bicimm8h_lsl8_a:
571 ; CHECK-GI: // %bb.0:
572 ; CHECK-GI-NEXT: adrp x8, .LCPI38_0
573 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI38_0]
574 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
575 ; CHECK-GI-NEXT: ret
576 %tmp1 = and <8 x i16> %a, < i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199,
577 i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199>
578 ret <8 x i16> %tmp1
579 }
581 define <8 x i16> @bicimm8h_lsl8_b(<8 x i16> %a) {
582 ; CHECK-SD-LABEL: bicimm8h_lsl8_b:
583 ; CHECK-SD: // %bb.0:
584 ; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8
585 ; CHECK-SD-NEXT: ret
586 ;
587 ; CHECK-GI-LABEL: bicimm8h_lsl8_b:
588 ; CHECK-GI: // %bb.0:
589 ; CHECK-GI-NEXT: adrp x8, .LCPI39_0
590 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI39_0]
591 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
592 ; CHECK-GI-NEXT: ret
593 %tmp1 = and <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
594 ret <8 x i16> %tmp1
595 }
597 define <2 x i32> @and2xi32(<2 x i32> %a, <2 x i32> %b) {
598 ; CHECK-LABEL: and2xi32:
599 ; CHECK: // %bb.0:
600 ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
601 ; CHECK-NEXT: ret
602 %tmp1 = and <2 x i32> %a, %b;
603 ret <2 x i32> %tmp1
604 }
606 define <4 x i16> @and4xi16(<4 x i16> %a, <4 x i16> %b) {
607 ; CHECK-LABEL: and4xi16:
608 ; CHECK: // %bb.0:
609 ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
610 ; CHECK-NEXT: ret
611 %tmp1 = and <4 x i16> %a, %b;
612 ret <4 x i16> %tmp1
613 }
615 define <1 x i64> @and1xi64(<1 x i64> %a, <1 x i64> %b) {
616 ; CHECK-SD-LABEL: and1xi64:
617 ; CHECK-SD: // %bb.0:
618 ; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
619 ; CHECK-SD-NEXT: ret
620 ;
621 ; CHECK-GI-LABEL: and1xi64:
622 ; CHECK-GI: // %bb.0:
623 ; CHECK-GI-NEXT: fmov x8, d0
624 ; CHECK-GI-NEXT: fmov x9, d1
625 ; CHECK-GI-NEXT: and x8, x8, x9
626 ; CHECK-GI-NEXT: fmov d0, x8
627 ; CHECK-GI-NEXT: ret
628 %tmp1 = and <1 x i64> %a, %b;
629 ret <1 x i64> %tmp1
630 }
632 define <4 x i32> @and4xi32(<4 x i32> %a, <4 x i32> %b) {
633 ; CHECK-LABEL: and4xi32:
634 ; CHECK: // %bb.0:
635 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
636 ; CHECK-NEXT: ret
637 %tmp1 = and <4 x i32> %a, %b;
638 ret <4 x i32> %tmp1
639 }
641 define <8 x i16> @and8xi16(<8 x i16> %a, <8 x i16> %b) {
642 ; CHECK-LABEL: and8xi16:
643 ; CHECK: // %bb.0:
644 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
645 ; CHECK-NEXT: ret
646 %tmp1 = and <8 x i16> %a, %b;
647 ret <8 x i16> %tmp1
648 }
650 define <2 x i64> @and2xi64(<2 x i64> %a, <2 x i64> %b) {
651 ; CHECK-LABEL: and2xi64:
652 ; CHECK: // %bb.0:
653 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
654 ; CHECK-NEXT: ret
655 %tmp1 = and <2 x i64> %a, %b;
656 ret <2 x i64> %tmp1
657 }
659 define <2 x i32> @orr2xi32(<2 x i32> %a, <2 x i32> %b) {
660 ; CHECK-LABEL: orr2xi32:
661 ; CHECK: // %bb.0:
662 ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
663 ; CHECK-NEXT: ret
664 %tmp1 = or <2 x i32> %a, %b;
665 ret <2 x i32> %tmp1
666 }
668 define <4 x i16> @orr4xi16(<4 x i16> %a, <4 x i16> %b) {
669 ; CHECK-LABEL: orr4xi16:
670 ; CHECK: // %bb.0:
671 ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
672 ; CHECK-NEXT: ret
673 %tmp1 = or <4 x i16> %a, %b;
674 ret <4 x i16> %tmp1
675 }
677 define <1 x i64> @orr1xi64(<1 x i64> %a, <1 x i64> %b) {
678 ; CHECK-SD-LABEL: orr1xi64:
679 ; CHECK-SD: // %bb.0:
680 ; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
681 ; CHECK-SD-NEXT: ret
682 ;
683 ; CHECK-GI-LABEL: orr1xi64:
684 ; CHECK-GI: // %bb.0:
685 ; CHECK-GI-NEXT: fmov x8, d0
686 ; CHECK-GI-NEXT: fmov x9, d1
687 ; CHECK-GI-NEXT: orr x8, x8, x9
688 ; CHECK-GI-NEXT: fmov d0, x8
689 ; CHECK-GI-NEXT: ret
690 %tmp1 = or <1 x i64> %a, %b;
691 ret <1 x i64> %tmp1
692 }
694 define <4 x i32> @orr4xi32(<4 x i32> %a, <4 x i32> %b) {
695 ; CHECK-LABEL: orr4xi32:
696 ; CHECK: // %bb.0:
697 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
698 ; CHECK-NEXT: ret
699 %tmp1 = or <4 x i32> %a, %b;
700 ret <4 x i32> %tmp1
701 }
703 define <8 x i16> @orr8xi16(<8 x i16> %a, <8 x i16> %b) {
704 ; CHECK-LABEL: orr8xi16:
705 ; CHECK: // %bb.0:
706 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
707 ; CHECK-NEXT: ret
708 %tmp1 = or <8 x i16> %a, %b;
709 ret <8 x i16> %tmp1
710 }
712 define <2 x i64> @orr2xi64(<2 x i64> %a, <2 x i64> %b) {
713 ; CHECK-LABEL: orr2xi64:
714 ; CHECK: // %bb.0:
715 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
716 ; CHECK-NEXT: ret
717 %tmp1 = or <2 x i64> %a, %b;
718 ret <2 x i64> %tmp1
719 }
721 define <2 x i32> @eor2xi32(<2 x i32> %a, <2 x i32> %b) {
722 ; CHECK-LABEL: eor2xi32:
723 ; CHECK: // %bb.0:
724 ; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
725 ; CHECK-NEXT: ret
726 %tmp1 = xor <2 x i32> %a, %b;
727 ret <2 x i32> %tmp1
728 }
730 define <4 x i16> @eor4xi16(<4 x i16> %a, <4 x i16> %b) {
731 ; CHECK-LABEL: eor4xi16:
732 ; CHECK: // %bb.0:
733 ; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
734 ; CHECK-NEXT: ret
735 %tmp1 = xor <4 x i16> %a, %b;
736 ret <4 x i16> %tmp1
737 }
739 define <1 x i64> @eor1xi64(<1 x i64> %a, <1 x i64> %b) {
740 ; CHECK-SD-LABEL: eor1xi64:
741 ; CHECK-SD: // %bb.0:
742 ; CHECK-SD-NEXT: eor v0.8b, v0.8b, v1.8b
743 ; CHECK-SD-NEXT: ret
744 ;
745 ; CHECK-GI-LABEL: eor1xi64:
746 ; CHECK-GI: // %bb.0:
747 ; CHECK-GI-NEXT: fmov x8, d0
748 ; CHECK-GI-NEXT: fmov x9, d1
749 ; CHECK-GI-NEXT: eor x8, x8, x9
750 ; CHECK-GI-NEXT: fmov d0, x8
751 ; CHECK-GI-NEXT: ret
752 %tmp1 = xor <1 x i64> %a, %b;
753 ret <1 x i64> %tmp1
754 }
756 define <4 x i32> @eor4xi32(<4 x i32> %a, <4 x i32> %b) {
757 ; CHECK-LABEL: eor4xi32:
758 ; CHECK: // %bb.0:
759 ; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
760 ; CHECK-NEXT: ret
761 %tmp1 = xor <4 x i32> %a, %b;
762 ret <4 x i32> %tmp1
763 }
765 define <8 x i16> @eor8xi16(<8 x i16> %a, <8 x i16> %b) {
766 ; CHECK-LABEL: eor8xi16:
767 ; CHECK: // %bb.0:
768 ; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
769 ; CHECK-NEXT: ret
770 %tmp1 = xor <8 x i16> %a, %b;
771 ret <8 x i16> %tmp1
772 }
774 define <2 x i64> @eor2xi64(<2 x i64> %a, <2 x i64> %b) {
775 ; CHECK-LABEL: eor2xi64:
776 ; CHECK: // %bb.0:
777 ; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
778 ; CHECK-NEXT: ret
779 %tmp1 = xor <2 x i64> %a, %b;
780 ret <2 x i64> %tmp1
781 }
784 define <2 x i32> @bic2xi32(<2 x i32> %a, <2 x i32> %b) {
785 ; CHECK-LABEL: bic2xi32:
786 ; CHECK: // %bb.0:
787 ; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b
788 ; CHECK-NEXT: ret
789 %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 >
790 %tmp2 = and <2 x i32> %a, %tmp1
791 ret <2 x i32> %tmp2
792 }
794 define <4 x i16> @bic4xi16(<4 x i16> %a, <4 x i16> %b) {
795 ; CHECK-LABEL: bic4xi16:
796 ; CHECK: // %bb.0:
797 ; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b
798 ; CHECK-NEXT: ret
799 %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 >
800 %tmp2 = and <4 x i16> %a, %tmp1
801 ret <4 x i16> %tmp2
802 }
804 define <1 x i64> @bic1xi64(<1 x i64> %a, <1 x i64> %b) {
805 ; CHECK-SD-LABEL: bic1xi64:
806 ; CHECK-SD: // %bb.0:
807 ; CHECK-SD-NEXT: bic v0.8b, v0.8b, v1.8b
808 ; CHECK-SD-NEXT: ret
809 ;
810 ; CHECK-GI-LABEL: bic1xi64:
811 ; CHECK-GI: // %bb.0:
812 ; CHECK-GI-NEXT: fmov x8, d1
813 ; CHECK-GI-NEXT: fmov x9, d0
814 ; CHECK-GI-NEXT: bic x8, x9, x8
815 ; CHECK-GI-NEXT: fmov d0, x8
816 ; CHECK-GI-NEXT: ret
817 %tmp1 = xor <1 x i64> %b, < i64 -1>
818 %tmp2 = and <1 x i64> %a, %tmp1
819 ret <1 x i64> %tmp2
820 }
822 define <4 x i32> @bic4xi32(<4 x i32> %a, <4 x i32> %b) {
823 ; CHECK-LABEL: bic4xi32:
824 ; CHECK: // %bb.0:
825 ; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b
826 ; CHECK-NEXT: ret
827 %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1>
828 %tmp2 = and <4 x i32> %a, %tmp1
829 ret <4 x i32> %tmp2
830 }
832 define <8 x i16> @bic8xi16(<8 x i16> %a, <8 x i16> %b) {
833 ; CHECK-LABEL: bic8xi16:
834 ; CHECK: // %bb.0:
835 ; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b
836 ; CHECK-NEXT: ret
837 %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 >
838 %tmp2 = and <8 x i16> %a, %tmp1
839 ret <8 x i16> %tmp2
840 }
842 define <2 x i64> @bic2xi64(<2 x i64> %a, <2 x i64> %b) {
843 ; CHECK-LABEL: bic2xi64:
844 ; CHECK: // %bb.0:
845 ; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b
846 ; CHECK-NEXT: ret
847 %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1>
848 %tmp2 = and <2 x i64> %a, %tmp1
849 ret <2 x i64> %tmp2
850 }
852 define <2 x i32> @orn2xi32(<2 x i32> %a, <2 x i32> %b) {
853 ; CHECK-LABEL: orn2xi32:
854 ; CHECK: // %bb.0:
855 ; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b
856 ; CHECK-NEXT: ret
857 %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 >
858 %tmp2 = or <2 x i32> %a, %tmp1
859 ret <2 x i32> %tmp2
860 }
862 define <4 x i16> @orn4xi16(<4 x i16> %a, <4 x i16> %b) {
863 ; CHECK-LABEL: orn4xi16:
864 ; CHECK: // %bb.0:
865 ; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b
866 ; CHECK-NEXT: ret
867 %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 >
868 %tmp2 = or <4 x i16> %a, %tmp1
869 ret <4 x i16> %tmp2
870 }
872 define <1 x i64> @orn1xi64(<1 x i64> %a, <1 x i64> %b) {
873 ; CHECK-SD-LABEL: orn1xi64:
874 ; CHECK-SD: // %bb.0:
875 ; CHECK-SD-NEXT: orn v0.8b, v0.8b, v1.8b
876 ; CHECK-SD-NEXT: ret
877 ;
878 ; CHECK-GI-LABEL: orn1xi64:
879 ; CHECK-GI: // %bb.0:
880 ; CHECK-GI-NEXT: fmov x8, d1
881 ; CHECK-GI-NEXT: fmov x9, d0
882 ; CHECK-GI-NEXT: orn x8, x9, x8
883 ; CHECK-GI-NEXT: fmov d0, x8
884 ; CHECK-GI-NEXT: ret
885 %tmp1 = xor <1 x i64> %b, < i64 -1>
886 %tmp2 = or <1 x i64> %a, %tmp1
887 ret <1 x i64> %tmp2
888 }
890 define <4 x i32> @orn4xi32(<4 x i32> %a, <4 x i32> %b) {
891 ; CHECK-LABEL: orn4xi32:
892 ; CHECK: // %bb.0:
893 ; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b
894 ; CHECK-NEXT: ret
895 %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1>
896 %tmp2 = or <4 x i32> %a, %tmp1
897 ret <4 x i32> %tmp2
898 }
900 define <8 x i16> @orn8xi16(<8 x i16> %a, <8 x i16> %b) {
901 ; CHECK-LABEL: orn8xi16:
902 ; CHECK: // %bb.0:
903 ; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b
904 ; CHECK-NEXT: ret
905 %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 >
906 %tmp2 = or <8 x i16> %a, %tmp1
907 ret <8 x i16> %tmp2
908 }
910 define <2 x i64> @orn2xi64(<2 x i64> %a, <2 x i64> %b) {
911 ; CHECK-LABEL: orn2xi64:
912 ; CHECK: // %bb.0:
913 ; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b
914 ; CHECK-NEXT: ret
915 %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1>
916 %tmp2 = or <2 x i64> %a, %tmp1
917 ret <2 x i64> %tmp2
918 }
920 define <2 x i32> @bsl2xi32_const(<2 x i32> %a, <2 x i32> %b) {
921 ; CHECK-SD-LABEL: bsl2xi32_const:
922 ; CHECK-SD: // %bb.0:
923 ; CHECK-SD-NEXT: movi d2, #0x000000ffffffff
924 ; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b
925 ; CHECK-SD-NEXT: ret
926 ;
927 ; CHECK-GI-LABEL: bsl2xi32_const:
928 ; CHECK-GI: // %bb.0:
929 ; CHECK-GI-NEXT: adrp x8, .LCPI70_1
930 ; CHECK-GI-NEXT: adrp x9, .LCPI70_0
931 ; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI70_1]
932 ; CHECK-GI-NEXT: ldr d3, [x9, :lo12:.LCPI70_0]
933 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v2.8b
934 ; CHECK-GI-NEXT: and v1.8b, v1.8b, v3.8b
935 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
936 ; CHECK-GI-NEXT: ret
937 %tmp1 = and <2 x i32> %a, < i32 -1, i32 0 >
938 %tmp2 = and <2 x i32> %b, < i32 0, i32 -1 >
939 %tmp3 = or <2 x i32> %tmp1, %tmp2
940 ret <2 x i32> %tmp3
941 }
944 define <4 x i16> @bsl4xi16_const(<4 x i16> %a, <4 x i16> %b) {
945 ; CHECK-SD-LABEL: bsl4xi16_const:
946 ; CHECK-SD: // %bb.0:
947 ; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff
948 ; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b
949 ; CHECK-SD-NEXT: ret
950 ;
951 ; CHECK-GI-LABEL: bsl4xi16_const:
952 ; CHECK-GI: // %bb.0:
953 ; CHECK-GI-NEXT: adrp x8, .LCPI71_1
954 ; CHECK-GI-NEXT: adrp x9, .LCPI71_0
955 ; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI71_1]
956 ; CHECK-GI-NEXT: ldr d3, [x9, :lo12:.LCPI71_0]
957 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v2.8b
958 ; CHECK-GI-NEXT: and v1.8b, v1.8b, v3.8b
959 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
960 ; CHECK-GI-NEXT: ret
961 %tmp1 = and <4 x i16> %a, < i16 -1, i16 0, i16 -1,i16 0 >
962 %tmp2 = and <4 x i16> %b, < i16 0, i16 -1,i16 0, i16 -1 >
963 %tmp3 = or <4 x i16> %tmp1, %tmp2
964 ret <4 x i16> %tmp3
965 }
967 define <1 x i64> @bsl1xi64_const(<1 x i64> %a, <1 x i64> %b) {
968 ; CHECK-SD-LABEL: bsl1xi64_const:
969 ; CHECK-SD: // %bb.0:
970 ; CHECK-SD-NEXT: movi d2, #0xffffffffffffff00
971 ; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b
972 ; CHECK-SD-NEXT: ret
973 ;
974 ; CHECK-GI-LABEL: bsl1xi64_const:
975 ; CHECK-GI: // %bb.0:
976 ; CHECK-GI-NEXT: fmov x8, d0
977 ; CHECK-GI-NEXT: fmov x9, d1
978 ; CHECK-GI-NEXT: and x8, x8, #0xffffffffffffff00
979 ; CHECK-GI-NEXT: and x9, x9, #0xff
980 ; CHECK-GI-NEXT: orr x8, x8, x9
981 ; CHECK-GI-NEXT: fmov d0, x8
982 ; CHECK-GI-NEXT: ret
983 %tmp1 = and <1 x i64> %a, < i64 -256 >
984 %tmp2 = and <1 x i64> %b, < i64 255 >
985 %tmp3 = or <1 x i64> %tmp1, %tmp2
986 ret <1 x i64> %tmp3
987 }
989 define <4 x i32> @bsl4xi32_const(<4 x i32> %a, <4 x i32> %b) {
990 ; CHECK-SD-LABEL: bsl4xi32_const:
991 ; CHECK-SD: // %bb.0:
992 ; CHECK-SD-NEXT: movi v2.2d, #0x000000ffffffff
993 ; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b
994 ; CHECK-SD-NEXT: ret
995 ;
996 ; CHECK-GI-LABEL: bsl4xi32_const:
997 ; CHECK-GI: // %bb.0:
998 ; CHECK-GI-NEXT: adrp x8, .LCPI73_1
999 ; CHECK-GI-NEXT: adrp x9, .LCPI73_0
1000 ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI73_1]
1001 ; CHECK-GI-NEXT: ldr q3, [x9, :lo12:.LCPI73_0]
1002 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b
1003 ; CHECK-GI-NEXT: and v1.16b, v1.16b, v3.16b
1004 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
1005 ; CHECK-GI-NEXT: ret
1006 %tmp1 = and <4 x i32> %a, < i32 -1, i32 0, i32 -1, i32 0 >
1007 %tmp2 = and <4 x i32> %b, < i32 0, i32 -1, i32 0, i32 -1 >
1008 %tmp3 = or <4 x i32> %tmp1, %tmp2
1009 ret <4 x i32> %tmp3
1010 }
1012 define <8 x i16> @bsl8xi16_const(<8 x i16> %a, <8 x i16> %b) {
1013 ; CHECK-SD-LABEL: bsl8xi16_const:
1014 ; CHECK-SD: // %bb.0:
1015 ; CHECK-SD-NEXT: movi v2.2d, #0x000000ffffffff
1016 ; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b
1017 ; CHECK-SD-NEXT: ret
1018 ;
1019 ; CHECK-GI-LABEL: bsl8xi16_const:
1020 ; CHECK-GI: // %bb.0:
1021 ; CHECK-GI-NEXT: adrp x8, .LCPI74_1
1022 ; CHECK-GI-NEXT: adrp x9, .LCPI74_0
1023 ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI74_1]
1024 ; CHECK-GI-NEXT: ldr q3, [x9, :lo12:.LCPI74_0]
1025 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b
1026 ; CHECK-GI-NEXT: and v1.16b, v1.16b, v3.16b
1027 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
1028 ; CHECK-GI-NEXT: ret
1029 %tmp1 = and <8 x i16> %a, < i16 -1, i16 -1, i16 0,i16 0, i16 -1, i16 -1, i16 0,i16 0 >
1030 %tmp2 = and <8 x i16> %b, < i16 0, i16 0, i16 -1, i16 -1, i16 0, i16 0, i16 -1, i16 -1 >
1031 %tmp3 = or <8 x i16> %tmp1, %tmp2
1032 ret <8 x i16> %tmp3
1033 }
1035 define <2 x i64> @bsl2xi64_const(<2 x i64> %a, <2 x i64> %b) {
1036 ; CHECK-SD-LABEL: bsl2xi64_const:
1037 ; CHECK-SD: // %bb.0:
1038 ; CHECK-SD-NEXT: adrp x8, .LCPI75_0
1039 ; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI75_0]
1040 ; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b
1041 ; CHECK-SD-NEXT: ret
1042 ;
1043 ; CHECK-GI-LABEL: bsl2xi64_const:
1044 ; CHECK-GI: // %bb.0:
1045 ; CHECK-GI-NEXT: adrp x8, .LCPI75_1
1046 ; CHECK-GI-NEXT: adrp x9, .LCPI75_0
1047 ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI75_1]
1048 ; CHECK-GI-NEXT: ldr q3, [x9, :lo12:.LCPI75_0]
1049 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b
1050 ; CHECK-GI-NEXT: and v1.16b, v1.16b, v3.16b
1051 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
1052 ; CHECK-GI-NEXT: ret
1053 %tmp1 = and <2 x i64> %a, < i64 -1, i64 0 >
1054 %tmp2 = and <2 x i64> %b, < i64 0, i64 -1 >
1055 %tmp3 = or <2 x i64> %tmp1, %tmp2
1056 ret <2 x i64> %tmp3
1057 }
1060 define <8 x i8> @bsl8xi8(<8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3) {
1061 ; CHECK-LABEL: bsl8xi8:
1062 ; CHECK: // %bb.0:
1063 ; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
1064 ; CHECK-NEXT: ret
1065 %1 = and <8 x i8> %v1, %v2
1066 %2 = xor <8 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
1067 %3 = and <8 x i8> %2, %v3
1068 %4 = or <8 x i8> %1, %3
1069 ret <8 x i8> %4
1070 }
1072 define <4 x i16> @bsl4xi16(<4 x i16> %v1, <4 x i16> %v2, <4 x i16> %v3) {
1073 ; CHECK-LABEL: bsl4xi16:
1074 ; CHECK: // %bb.0:
1075 ; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
1076 ; CHECK-NEXT: ret
1077 %1 = and <4 x i16> %v1, %v2
1078 %2 = xor <4 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1>
1079 %3 = and <4 x i16> %2, %v3
1080 %4 = or <4 x i16> %1, %3
1081 ret <4 x i16> %4
1082 }
1084 define <2 x i32> @bsl2xi32(<2 x i32> %v1, <2 x i32> %v2, <2 x i32> %v3) {
1085 ; CHECK-LABEL: bsl2xi32:
1086 ; CHECK: // %bb.0:
1087 ; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
1088 ; CHECK-NEXT: ret
1089 %1 = and <2 x i32> %v1, %v2
1090 %2 = xor <2 x i32> %v1, <i32 -1, i32 -1>
1091 %3 = and <2 x i32> %2, %v3
1092 %4 = or <2 x i32> %1, %3
1093 ret <2 x i32> %4
1094 }
1096 define <1 x i64> @bsl1xi64(<1 x i64> %v1, <1 x i64> %v2, <1 x i64> %v3) {
1097 ; CHECK-SD-LABEL: bsl1xi64:
1098 ; CHECK-SD: // %bb.0:
1099 ; CHECK-SD-NEXT: bsl v0.8b, v1.8b, v2.8b
1100 ; CHECK-SD-NEXT: ret
1101 ;
1102 ; CHECK-GI-LABEL: bsl1xi64:
1103 ; CHECK-GI: // %bb.0:
1104 ; CHECK-GI-NEXT: fmov x8, d0
1105 ; CHECK-GI-NEXT: fmov x9, d1
1106 ; CHECK-GI-NEXT: fmov x10, d2
1107 ; CHECK-GI-NEXT: and x9, x8, x9
1108 ; CHECK-GI-NEXT: bic x8, x10, x8
1109 ; CHECK-GI-NEXT: orr x8, x9, x8
1110 ; CHECK-GI-NEXT: fmov d0, x8
1111 ; CHECK-GI-NEXT: ret
1112 %1 = and <1 x i64> %v1, %v2
1113 %2 = xor <1 x i64> %v1, <i64 -1>
1114 %3 = and <1 x i64> %2, %v3
1115 %4 = or <1 x i64> %1, %3
1116 ret <1 x i64> %4
1117 }
1119 define <16 x i8> @bsl16xi8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3) {
1120 ; CHECK-LABEL: bsl16xi8:
1121 ; CHECK: // %bb.0:
1122 ; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
1123 ; CHECK-NEXT: ret
1124 %1 = and <16 x i8> %v1, %v2
1125 %2 = xor <16 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
1126 %3 = and <16 x i8> %2, %v3
1127 %4 = or <16 x i8> %1, %3
1128 ret <16 x i8> %4
1129 }
1131 define <8 x i16> @bsl8xi16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %v3) {
1132 ; CHECK-LABEL: bsl8xi16:
1133 ; CHECK: // %bb.0:
1134 ; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
1135 ; CHECK-NEXT: ret
1136 %1 = and <8 x i16> %v1, %v2
1137 %2 = xor <8 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
1138 %3 = and <8 x i16> %2, %v3
1139 %4 = or <8 x i16> %1, %3
1140 ret <8 x i16> %4
1141 }
1143 define <4 x i32> @bsl4xi32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
1144 ; CHECK-LABEL: bsl4xi32:
1145 ; CHECK: // %bb.0:
1146 ; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
1147 ; CHECK-NEXT: ret
1148 %1 = and <4 x i32> %v1, %v2
1149 %2 = xor <4 x i32> %v1, <i32 -1, i32 -1, i32 -1, i32 -1>
1150 %3 = and <4 x i32> %2, %v3
1151 %4 = or <4 x i32> %1, %3
1152 ret <4 x i32> %4
1153 }
1155 define <8 x i8> @vselect_constant_cond_zero_v8i8(<8 x i8> %a) {
1156 ; CHECK-SD-LABEL: vselect_constant_cond_zero_v8i8:
1157 ; CHECK-SD: // %bb.0:
1158 ; CHECK-SD-NEXT: movi d1, #0x00000000ff00ff
1159 ; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
1160 ; CHECK-SD-NEXT: ret
1161 ;
1162 ; CHECK-GI-LABEL: vselect_constant_cond_zero_v8i8:
1163 ; CHECK-GI: // %bb.0:
1164 ; CHECK-GI-NEXT: adrp x8, .LCPI83_0
1165 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI83_0]
1166 ; CHECK-GI-NEXT: shl v1.8b, v1.8b, #7
1167 ; CHECK-GI-NEXT: sshr v1.8b, v1.8b, #7
1168 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1169 ; CHECK-GI-NEXT: ret
1170 %b = select <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i8> %a, <8 x i8> zeroinitializer
1171 ret <8 x i8> %b
1172 }
1174 define <4 x i16> @vselect_constant_cond_zero_v4i16(<4 x i16> %a) {
1175 ; CHECK-SD-LABEL: vselect_constant_cond_zero_v4i16:
1176 ; CHECK-SD: // %bb.0:
1177 ; CHECK-SD-NEXT: movi d1, #0xffff00000000ffff
1178 ; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
1179 ; CHECK-SD-NEXT: ret
1180 ;
1181 ; CHECK-GI-LABEL: vselect_constant_cond_zero_v4i16:
1182 ; CHECK-GI: // %bb.0:
1183 ; CHECK-GI-NEXT: adrp x8, .LCPI84_0
1184 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI84_0]
1185 ; CHECK-GI-NEXT: shl v1.4h, v1.4h, #15
1186 ; CHECK-GI-NEXT: sshr v1.4h, v1.4h, #15
1187 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1188 ; CHECK-GI-NEXT: ret
1189 %b = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i16> %a, <4 x i16> zeroinitializer
1190 ret <4 x i16> %b
1191 }
1193 define <4 x i32> @vselect_constant_cond_zero_v4i32(<4 x i32> %a) {
1194 ; CHECK-SD-LABEL: vselect_constant_cond_zero_v4i32:
1195 ; CHECK-SD: // %bb.0:
1196 ; CHECK-SD-NEXT: adrp x8, .LCPI85_0
1197 ; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI85_0]
1198 ; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b
1199 ; CHECK-SD-NEXT: ret
1200 ;
1201 ; CHECK-GI-LABEL: vselect_constant_cond_zero_v4i32:
1202 ; CHECK-GI: // %bb.0:
1203 ; CHECK-GI-NEXT: adrp x8, .LCPI85_1
1204 ; CHECK-GI-NEXT: adrp x9, .LCPI85_0
1205 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI85_1]
1206 ; CHECK-GI-NEXT: ldr d2, [x9, :lo12:.LCPI85_0]
1207 ; CHECK-GI-NEXT: mov v1.d[1], v2.d[0]
1208 ; CHECK-GI-NEXT: shl v1.4s, v1.4s, #31
1209 ; CHECK-GI-NEXT: sshr v1.4s, v1.4s, #31
1210 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1211 ; CHECK-GI-NEXT: ret
1212 %b = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i32> %a, <4 x i32> zeroinitializer
1213 ret <4 x i32> %b
1214 }
1216 define <8 x i8> @vselect_constant_cond_v8i8(<8 x i8> %a, <8 x i8> %b) {
1217 ; CHECK-SD-LABEL: vselect_constant_cond_v8i8:
1218 ; CHECK-SD: // %bb.0:
1219 ; CHECK-SD-NEXT: movi d2, #0xffffffffff00ff00
1220 ; CHECK-SD-NEXT: movi d3, #0x00000000ff00ff
1221 ; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b
1222 ; CHECK-SD-NEXT: and v0.8b, v0.8b, v3.8b
1223 ; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
1224 ; CHECK-SD-NEXT: ret
1225 ;
1226 ; CHECK-GI-LABEL: vselect_constant_cond_v8i8:
1227 ; CHECK-GI: // %bb.0:
1228 ; CHECK-GI-NEXT: adrp x8, .LCPI86_0
1229 ; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI86_0]
1230 ; CHECK-GI-NEXT: shl v2.8b, v2.8b, #7
1231 ; CHECK-GI-NEXT: sshr v2.8b, v2.8b, #7
1232 ; CHECK-GI-NEXT: bif v0.8b, v1.8b, v2.8b
1233 ; CHECK-GI-NEXT: ret
1234 %c = select <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i8> %a, <8 x i8> %b
1235 ret <8 x i8> %c
1236 }
1238 define <4 x i16> @vselect_constant_cond_v4i16(<4 x i16> %a, <4 x i16> %b) {
1239 ; CHECK-SD-LABEL: vselect_constant_cond_v4i16:
1240 ; CHECK-SD: // %bb.0:
1241 ; CHECK-SD-NEXT: movi d2, #0x00ffffffff0000
1242 ; CHECK-SD-NEXT: movi d3, #0xffff00000000ffff
1243 ; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b
1244 ; CHECK-SD-NEXT: and v0.8b, v0.8b, v3.8b
1245 ; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
1246 ; CHECK-SD-NEXT: ret
1247 ;
1248 ; CHECK-GI-LABEL: vselect_constant_cond_v4i16:
1249 ; CHECK-GI: // %bb.0:
1250 ; CHECK-GI-NEXT: adrp x8, .LCPI87_0
1251 ; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI87_0]
1252 ; CHECK-GI-NEXT: shl v2.4h, v2.4h, #15
1253 ; CHECK-GI-NEXT: sshr v2.4h, v2.4h, #15
1254 ; CHECK-GI-NEXT: bif v0.8b, v1.8b, v2.8b
1255 ; CHECK-GI-NEXT: ret
1256 %c = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i16> %a, <4 x i16> %b
1257 ret <4 x i16> %c
1258 }
1260 define <4 x i32> @vselect_constant_cond_v4i32(<4 x i32> %a, <4 x i32> %b) {
1261 ; CHECK-SD-LABEL: vselect_constant_cond_v4i32:
1262 ; CHECK-SD: // %bb.0:
1263 ; CHECK-SD-NEXT: adrp x8, .LCPI88_0
1264 ; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI88_0]
1265 ; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b
1266 ; CHECK-SD-NEXT: ret
1267 ;
1268 ; CHECK-GI-LABEL: vselect_constant_cond_v4i32:
1269 ; CHECK-GI: // %bb.0:
1270 ; CHECK-GI-NEXT: adrp x8, .LCPI88_1
1271 ; CHECK-GI-NEXT: adrp x9, .LCPI88_0
1272 ; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI88_1]
1273 ; CHECK-GI-NEXT: ldr d3, [x9, :lo12:.LCPI88_0]
1274 ; CHECK-GI-NEXT: mov v2.d[1], v3.d[0]
1275 ; CHECK-GI-NEXT: shl v2.4s, v2.4s, #31
1276 ; CHECK-GI-NEXT: sshr v2.4s, v2.4s, #31
1277 ; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
1278 ; CHECK-GI-NEXT: ret
1279 %c = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i32> %a, <4 x i32> %b
1280 ret <4 x i32> %c
1281 }
1283 ; CHECK-SD: .byte 0
1284 ; CHECK-SD: .byte 8
1285 ; CHECK-SD: .byte 2
1286 ; CHECK-SD: .byte 9
1287 ; CHECK-SD: .byte 4
1288 ; CHECK-SD: .byte 5
1289 ; CHECK-SD: .byte 6
1290 ; CHECK-SD: .byte 7
1291 define <8 x i8> @vselect_equivalent_shuffle_v8i8(<8 x i8> %a, <8 x i8> %b) {
1292 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i8:
1293 ; CHECK-SD: // %bb.0:
1294 ; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
1295 ; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
1296 ; CHECK-SD-NEXT: adrp x8, .LCPI89_0
1297 ; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
1298 ; CHECK-SD-NEXT: ldr d1, [x8, :lo12:.LCPI89_0]
1299 ; CHECK-SD-NEXT: tbl v0.8b, { v0.16b }, v1.8b
1300 ; CHECK-SD-NEXT: ret
1301 ;
1302 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i8:
1303 ; CHECK-GI: // %bb.0:
1304 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
1305 ; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
1306 ; CHECK-GI-NEXT: adrp x8, .LCPI89_0
1307 ; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
1308 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI89_0]
1309 ; CHECK-GI-NEXT: tbl v0.16b, { v0.16b }, v1.16b
1310 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
1311 ; CHECK-GI-NEXT: ret
1312 %c = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 0, i32 8, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7>
1313 ret <8 x i8> %c
1314 }
1316 define <8 x i8> @vselect_equivalent_shuffle_v8i8_zero(<8 x i8> %a) {
1317 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i8_zero:
1318 ; CHECK-SD: // %bb.0:
1319 ; CHECK-SD-NEXT: movi d1, #0xffffffff00ff00ff
1320 ; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
1321 ; CHECK-SD-NEXT: ret
1322 ;
1323 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i8_zero:
1324 ; CHECK-GI: // %bb.0:
1325 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1326 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
1327 ; CHECK-GI-NEXT: adrp x8, .LCPI90_0
1328 ; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
1329 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI90_0]
1330 ; CHECK-GI-NEXT: tbl v0.16b, { v0.16b }, v1.16b
1331 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
1332 ; CHECK-GI-NEXT: ret
1333 %c = shufflevector <8 x i8> %a, <8 x i8> zeroinitializer, <8 x i32> <i32 0, i32 8, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7>
1334 ret <8 x i8> %c
1335 }
1337 ; CHECK-SD-LABEL: .LCPI91_0:
1338 ; CHECK-SD-NEXT: .byte 0
1339 ; CHECK-SD-NEXT: .byte 255
1340 ; CHECK-SD-NEXT: .byte 2
1341 ; CHECK-SD-NEXT: .byte 255
1342 ; CHECK-SD-NEXT: .byte 4
1343 ; CHECK-SD-NEXT: .byte 5
1344 ; CHECK-SD-NEXT: .byte 6
1345 ; CHECK-SD-NEXT: .byte 7
1346 define <8 x i8> @vselect_equivalent_shuffle_v8i8_zeroswap(<8 x i8> %a) {
1347 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i8_zeroswap:
1348 ; CHECK-SD: // %bb.0:
1349 ; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
1350 ; CHECK-SD-NEXT: adrp x8, .LCPI91_0
1351 ; CHECK-SD-NEXT: mov v0.d[1], v0.d[0]
1352 ; CHECK-SD-NEXT: ldr d1, [x8, :lo12:.LCPI91_0]
1353 ; CHECK-SD-NEXT: tbl v0.8b, { v0.16b }, v1.8b
1354 ; CHECK-SD-NEXT: ret
1355 ;
1356 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i8_zeroswap:
1357 ; CHECK-GI: // %bb.0:
1358 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1359 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
1360 ; CHECK-GI-NEXT: adrp x8, .LCPI91_0
1361 ; CHECK-GI-NEXT: mov v1.d[1], v0.d[0]
1362 ; CHECK-GI-NEXT: ldr d0, [x8, :lo12:.LCPI91_0]
1363 ; CHECK-GI-NEXT: tbl v0.16b, { v1.16b }, v0.16b
1364 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
1365 ; CHECK-GI-NEXT: ret
1366 %c = shufflevector <8 x i8> zeroinitializer, <8 x i8> %a, <8 x i32> <i32 8, i32 0, i32 10, i32 1, i32 12, i32 13, i32 14, i32 15>
1367 ret <8 x i8> %c
1368 }
1370 ; CHECK-SD-LABEL: .LCPI92_0:
1371 ; CHECK-SD-NEXT: .byte 0
1372 ; CHECK-SD-NEXT: .byte 1
1373 ; CHECK-SD-NEXT: .byte 16
1374 ; CHECK-SD-NEXT: .byte 17
1375 ; CHECK-SD-NEXT: .byte 4
1376 ; CHECK-SD-NEXT: .byte 5
1377 ; CHECK-SD-NEXT: .byte 18
1378 ; CHECK-SD-NEXT: .byte 19
1379 ; CHECK-SD-NEXT: .byte 8
1380 ; CHECK-SD-NEXT: .byte 9
1381 ; CHECK-SD-NEXT: .byte 10
1382 ; CHECK-SD-NEXT: .byte 11
1383 ; CHECK-SD-NEXT: .byte 12
1384 ; CHECK-SD-NEXT: .byte 13
1385 ; CHECK-SD-NEXT: .byte 14
1386 ; CHECK-SD-NEXT: .byte 15
1387 define <8 x i16> @vselect_equivalent_shuffle_v8i16(<8 x i16> %a, <8 x i16> %b) {
1388 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i16:
1389 ; CHECK-SD: // %bb.0:
1390 ; CHECK-SD-NEXT: adrp x8, .LCPI92_0
1391 ; CHECK-SD-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
1392 ; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI92_0]
1393 ; CHECK-SD-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
1394 ; CHECK-SD-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
1395 ; CHECK-SD-NEXT: ret
1396 ;
1397 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i16:
1398 ; CHECK-GI: // %bb.0:
1399 ; CHECK-GI-NEXT: adrp x8, .LCPI92_0
1400 ; CHECK-GI-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
1401 ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI92_0]
1402 ; CHECK-GI-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
1403 ; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
1404 ; CHECK-GI-NEXT: ret
1405 %c = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 8, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7>
1406 ret <8 x i16> %c
1407 }
1409 ; CHECK-SD-LABEL: .LCPI93_0:
1410 ; CHECK-SD-NEXT: .hword 65535 // 0xffff
1411 ; CHECK-SD-NEXT: .hword 0 // 0x0
1412 ; CHECK-SD-NEXT: .hword 65535 // 0xffff
1413 ; CHECK-SD-NEXT: .hword 0 // 0x0
1414 ; CHECK-SD-NEXT: .hword 65535 // 0xffff
1415 ; CHECK-SD-NEXT: .hword 65535 // 0xffff
1416 ; CHECK-SD-NEXT: .hword 65535 // 0xffff
1417 ; CHECK-SD-NEXT: .hword 65535 // 0xffff
1418 define <8 x i16> @vselect_equivalent_shuffle_v8i16_zero(<8 x i16> %a) {
1419 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i16_zero:
1420 ; CHECK-SD: // %bb.0:
1421 ; CHECK-SD-NEXT: adrp x8, .LCPI93_0
1422 ; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI93_0]
1423 ; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b
1424 ; CHECK-SD-NEXT: ret
1425 ;
1426 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i16_zero:
1427 ; CHECK-GI: // %bb.0:
1428 ; CHECK-GI-NEXT: // kill: def $q0 killed $q0 def $q0_q1
1429 ; CHECK-GI-NEXT: adrp x8, .LCPI93_0
1430 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1431 ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI93_0]
1432 ; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
1433 ; CHECK-GI-NEXT: ret
1434 %c = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 0, i32 8, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7>
1435 ret <8 x i16> %c
1436 }
1438 ; CHECK-SD: .byte 0
1439 ; CHECK-SD: .byte 1
1440 ; CHECK-SD: .byte 255
1441 ; CHECK-SD: .byte 255
1442 ; CHECK-SD: .byte 4
1443 ; CHECK-SD: .byte 5
1444 ; CHECK-SD: .byte 255
1445 ; CHECK-SD: .byte 255
1446 ; CHECK-SD: .byte 8
1447 ; CHECK-SD: .byte 9
1448 ; CHECK-SD: .byte 10
1449 ; CHECK-SD: .byte 11
1450 ; CHECK-SD: .byte 12
1451 ; CHECK-SD: .byte 13
1452 ; CHECK-SD: .byte 14
1453 ; CHECK-SD: .byte 15
1454 define <8 x i16> @vselect_equivalent_shuffle_v8i16_zeroswap(<8 x i16> %a) {
1455 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i16_zeroswap:
1456 ; CHECK-SD: // %bb.0:
1457 ; CHECK-SD-NEXT: adrp x8, .LCPI94_0
1458 ; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI94_0]
1459 ; CHECK-SD-NEXT: tbl v0.16b, { v0.16b }, v1.16b
1460 ; CHECK-SD-NEXT: ret
1461 ;
1462 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i16_zeroswap:
1463 ; CHECK-GI: // %bb.0:
1464 ; CHECK-GI-NEXT: // kill: def $q0 killed $q0 def $q31_q0
1465 ; CHECK-GI-NEXT: adrp x8, .LCPI94_0
1466 ; CHECK-GI-NEXT: movi v31.2d, #0000000000000000
1467 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI94_0]
1468 ; CHECK-GI-NEXT: tbl v0.16b, { v31.16b, v0.16b }, v1.16b
1469 ; CHECK-GI-NEXT: ret
1470 %c = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 8, i32 0, i32 10, i32 1, i32 12, i32 13, i32 14, i32 15>
1471 ret <8 x i16> %c
1472 }
1474 define <4 x i16> @vselect_equivalent_shuffle_v4i16(<4 x i16> %a, <4 x i16> %b) {
1475 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v4i16:
1476 ; CHECK-SD: // %bb.0:
1477 ; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
1478 ; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
1479 ; CHECK-SD-NEXT: mov v0.h[1], v1.h[0]
1480 ; CHECK-SD-NEXT: mov v0.h[2], v1.h[1]
1481 ; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
1482 ; CHECK-SD-NEXT: ret
1483 ;
1484 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v4i16:
1485 ; CHECK-GI: // %bb.0:
1486 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
1487 ; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
1488 ; CHECK-GI-NEXT: adrp x8, .LCPI95_0
1489 ; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
1490 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI95_0]
1491 ; CHECK-GI-NEXT: tbl v0.16b, { v0.16b }, v1.16b
1492 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
1493 ; CHECK-GI-NEXT: ret
1494 %c = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 0, i32 4, i32 5, i32 3>
1495 ret <4 x i16> %c
1496 }
1498 define <4 x i32> @vselect_equivalent_shuffle_v4i32(<4 x i32> %a, <4 x i32> %b) {
1499 ; CHECK-SD-LABEL: vselect_equivalent_shuffle_v4i32:
1500 ; CHECK-SD: // %bb.0:
1501 ; CHECK-SD-NEXT: mov v0.s[1], v1.s[0]
1502 ; CHECK-SD-NEXT: mov v0.s[2], v1.s[1]
1503 ; CHECK-SD-NEXT: ret
1504 ;
1505 ; CHECK-GI-LABEL: vselect_equivalent_shuffle_v4i32:
1506 ; CHECK-GI: // %bb.0:
1507 ; CHECK-GI-NEXT: adrp x8, .LCPI96_0
1508 ; CHECK-GI-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
1509 ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI96_0]
1510 ; CHECK-GI-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
1511 ; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
1512 ; CHECK-GI-NEXT: ret
1513 %c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 5, i32 3>
1514 ret <4 x i32> %c
1515 }
1517 define <8 x i8> @vselect_cmp_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
1518 ; CHECK-SD-LABEL: vselect_cmp_ne:
1519 ; CHECK-SD: // %bb.0:
1520 ; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, v1.8b
1521 ; CHECK-SD-NEXT: bsl v0.8b, v2.8b, v1.8b
1522 ; CHECK-SD-NEXT: ret
1523 ;
1524 ; CHECK-GI-LABEL: vselect_cmp_ne:
1525 ; CHECK-GI: // %bb.0:
1526 ; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v1.8b
1527 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
1528 ; CHECK-GI-NEXT: bsl v0.8b, v1.8b, v2.8b
1529 ; CHECK-GI-NEXT: ret
1530 %cmp = icmp ne <8 x i8> %a, %b
1531 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
1532 ret <8 x i8> %d
1533 }
1535 define <8 x i8> @vselect_cmp_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
1536 ; CHECK-LABEL: vselect_cmp_eq:
1537 ; CHECK: // %bb.0:
1538 ; CHECK-NEXT: cmeq v0.8b, v0.8b, v1.8b
1539 ; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
1540 ; CHECK-NEXT: ret
1541 %cmp = icmp eq <8 x i8> %a, %b
1542 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
1543 ret <8 x i8> %d
1544 }
1546 define <8 x i8> @vselect_cmpz_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
1547 ; CHECK-SD-LABEL: vselect_cmpz_ne:
1548 ; CHECK-SD: // %bb.0:
1549 ; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, #0
1550 ; CHECK-SD-NEXT: bsl v0.8b, v2.8b, v1.8b
1551 ; CHECK-SD-NEXT: ret
1552 ;
1553 ; CHECK-GI-LABEL: vselect_cmpz_ne:
1554 ; CHECK-GI: // %bb.0:
1555 ; CHECK-GI-NEXT: movi v3.2d, #0000000000000000
1556 ; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v3.8b
1557 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
1558 ; CHECK-GI-NEXT: bsl v0.8b, v1.8b, v2.8b
1559 ; CHECK-GI-NEXT: ret
1560 %cmp = icmp ne <8 x i8> %a, zeroinitializer
1561 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
1562 ret <8 x i8> %d
1563 }
1565 define <8 x i8> @vselect_cmpz_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
1566 ; CHECK-SD-LABEL: vselect_cmpz_eq:
1567 ; CHECK-SD: // %bb.0:
1568 ; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, #0
1569 ; CHECK-SD-NEXT: bsl v0.8b, v1.8b, v2.8b
1570 ; CHECK-SD-NEXT: ret
1571 ;
1572 ; CHECK-GI-LABEL: vselect_cmpz_eq:
1573 ; CHECK-GI: // %bb.0:
1574 ; CHECK-GI-NEXT: movi v3.2d, #0000000000000000
1575 ; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v3.8b
1576 ; CHECK-GI-NEXT: bsl v0.8b, v1.8b, v2.8b
1577 ; CHECK-GI-NEXT: ret
1578 %cmp = icmp eq <8 x i8> %a, zeroinitializer
1579 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
1580 ret <8 x i8> %d
1581 }
1583 define <8 x i8> @vselect_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
1584 ; CHECK-SD-LABEL: vselect_tst:
1585 ; CHECK-SD: // %bb.0:
1586 ; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
1587 ; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, #0
1588 ; CHECK-SD-NEXT: bsl v0.8b, v2.8b, v1.8b
1589 ; CHECK-SD-NEXT: ret
1590 ;
1591 ; CHECK-GI-LABEL: vselect_tst:
1592 ; CHECK-GI: // %bb.0:
1593 ; CHECK-GI-NEXT: movi v3.2d, #0000000000000000
1594 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1595 ; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v3.8b
1596 ; CHECK-GI-NEXT: bsl v0.8b, v2.8b, v1.8b
1597 ; CHECK-GI-NEXT: ret
1598 %tmp3 = and <8 x i8> %a, %b
1599 %tmp4 = icmp eq <8 x i8> %tmp3, zeroinitializer
1600 %d = select <8 x i1> %tmp4, <8 x i8> %c, <8 x i8> %b
1601 ret <8 x i8> %d
1602 }
1604 define <8 x i8> @sext_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
1605 ; CHECK-SD-LABEL: sext_tst:
1606 ; CHECK-SD: // %bb.0:
1607 ; CHECK-SD-NEXT: cmtst v0.8b, v0.8b, v1.8b
1608 ; CHECK-SD-NEXT: ret
1609 ;
1610 ; CHECK-GI-LABEL: sext_tst:
1611 ; CHECK-GI: // %bb.0:
1612 ; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
1613 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1614 ; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v2.8b
1615 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
1616 ; CHECK-GI-NEXT: ret
1617 %tmp3 = and <8 x i8> %a, %b
1618 %tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer
1619 %d = sext <8 x i1> %tmp4 to <8 x i8>
1620 ret <8 x i8> %d
1621 }
1623 define <2 x i64> @bsl2xi64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %v3) {
1624 ; CHECK-LABEL: bsl2xi64:
1625 ; CHECK: // %bb.0:
1626 ; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
1627 ; CHECK-NEXT: ret
1628 %1 = and <2 x i64> %v1, %v2
1629 %2 = xor <2 x i64> %v1, <i64 -1, i64 -1>
1630 %3 = and <2 x i64> %2, %v3
1631 %4 = or <2 x i64> %1, %3
1632 ret <2 x i64> %4
1633 }
1635 define <8 x i8> @orrimm8b_as_orrimm4h_lsl0(<8 x i8> %a) {
1636 ; CHECK-SD-LABEL: orrimm8b_as_orrimm4h_lsl0:
1637 ; CHECK-SD: // %bb.0:
1638 ; CHECK-SD-NEXT: orr v0.4h, #255
1639 ; CHECK-SD-NEXT: ret
1640 ;
1641 ; CHECK-GI-LABEL: orrimm8b_as_orrimm4h_lsl0:
1642 ; CHECK-GI: // %bb.0:
1643 ; CHECK-GI-NEXT: adrp x8, .LCPI104_0
1644 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI104_0]
1645 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
1646 ; CHECK-GI-NEXT: ret
1647 %val = or <8 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
1648 ret <8 x i8> %val
1649 }
1651 define <8 x i8> @orrimm8b_as_orimm4h_lsl8(<8 x i8> %a) {
1652 ; CHECK-SD-LABEL: orrimm8b_as_orimm4h_lsl8:
1653 ; CHECK-SD: // %bb.0:
1654 ; CHECK-SD-NEXT: orr v0.4h, #255, lsl #8
1655 ; CHECK-SD-NEXT: ret
1656 ;
1657 ; CHECK-GI-LABEL: orrimm8b_as_orimm4h_lsl8:
1658 ; CHECK-GI: // %bb.0:
1659 ; CHECK-GI-NEXT: adrp x8, .LCPI105_0
1660 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI105_0]
1661 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
1662 ; CHECK-GI-NEXT: ret
1663 %val = or <8 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
1664 ret <8 x i8> %val
1665 }
1667 define <16 x i8> @orimm16b_as_orrimm8h_lsl0(<16 x i8> %a) {
1668 ; CHECK-SD-LABEL: orimm16b_as_orrimm8h_lsl0:
1669 ; CHECK-SD: // %bb.0:
1670 ; CHECK-SD-NEXT: orr v0.8h, #255
1671 ; CHECK-SD-NEXT: ret
1672 ;
1673 ; CHECK-GI-LABEL: orimm16b_as_orrimm8h_lsl0:
1674 ; CHECK-GI: // %bb.0:
1675 ; CHECK-GI-NEXT: adrp x8, .LCPI106_0
1676 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI106_0]
1677 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
1678 ; CHECK-GI-NEXT: ret
1679 %val = or <16 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
1680 ret <16 x i8> %val
1681 }
1683 define <16 x i8> @orimm16b_as_orrimm8h_lsl8(<16 x i8> %a) {
1684 ; CHECK-SD-LABEL: orimm16b_as_orrimm8h_lsl8:
1685 ; CHECK-SD: // %bb.0:
1686 ; CHECK-SD-NEXT: orr v0.8h, #255, lsl #8
1687 ; CHECK-SD-NEXT: ret
1688 ;
1689 ; CHECK-GI-LABEL: orimm16b_as_orrimm8h_lsl8:
1690 ; CHECK-GI: // %bb.0:
1691 ; CHECK-GI-NEXT: adrp x8, .LCPI107_0
1692 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI107_0]
1693 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
1694 ; CHECK-GI-NEXT: ret
1695 %val = or <16 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
1696 ret <16 x i8> %val
1697 }
1699 define <8 x i8> @and8imm2s_lsl0(<8 x i8> %a) {
1700 ; CHECK-SD-LABEL: and8imm2s_lsl0:
1701 ; CHECK-SD: // %bb.0:
1702 ; CHECK-SD-NEXT: bic v0.2s, #255
1703 ; CHECK-SD-NEXT: ret
1704 ;
1705 ; CHECK-GI-LABEL: and8imm2s_lsl0:
1706 ; CHECK-GI: // %bb.0:
1707 ; CHECK-GI-NEXT: adrp x8, .LCPI108_0
1708 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI108_0]
1709 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1710 ; CHECK-GI-NEXT: ret
1711 %tmp1 = and <8 x i8> %a, < i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255>
1712 ret <8 x i8> %tmp1
1713 }
1715 define <8 x i8> @and8imm2s_lsl8(<8 x i8> %a) {
1716 ; CHECK-SD-LABEL: and8imm2s_lsl8:
1717 ; CHECK-SD: // %bb.0:
1718 ; CHECK-SD-NEXT: bic v0.2s, #255, lsl #8
1719 ; CHECK-SD-NEXT: ret
1720 ;
1721 ; CHECK-GI-LABEL: and8imm2s_lsl8:
1722 ; CHECK-GI: // %bb.0:
1723 ; CHECK-GI-NEXT: adrp x8, .LCPI109_0
1724 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI109_0]
1725 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1726 ; CHECK-GI-NEXT: ret
1727 %tmp1 = and <8 x i8> %a, < i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255>
1728 ret <8 x i8> %tmp1
1729 }
1731 define <8 x i8> @and8imm2s_lsl16(<8 x i8> %a) {
1732 ; CHECK-SD-LABEL: and8imm2s_lsl16:
1733 ; CHECK-SD: // %bb.0:
1734 ; CHECK-SD-NEXT: bic v0.2s, #255, lsl #16
1735 ; CHECK-SD-NEXT: ret
1736 ;
1737 ; CHECK-GI-LABEL: and8imm2s_lsl16:
1738 ; CHECK-GI: // %bb.0:
1739 ; CHECK-GI-NEXT: adrp x8, .LCPI110_0
1740 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI110_0]
1741 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1742 ; CHECK-GI-NEXT: ret
1743 %tmp1 = and <8 x i8> %a, < i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255>
1744 ret <8 x i8> %tmp1
1745 }
1747 define <8 x i8> @and8imm2s_lsl24(<8 x i8> %a) {
1748 ; CHECK-SD-LABEL: and8imm2s_lsl24:
1749 ; CHECK-SD: // %bb.0:
1750 ; CHECK-SD-NEXT: bic v0.2s, #254, lsl #24
1751 ; CHECK-SD-NEXT: ret
1752 ;
1753 ; CHECK-GI-LABEL: and8imm2s_lsl24:
1754 ; CHECK-GI: // %bb.0:
1755 ; CHECK-GI-NEXT: adrp x8, .LCPI111_0
1756 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI111_0]
1757 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1758 ; CHECK-GI-NEXT: ret
1759 %tmp1 = and <8 x i8> %a, < i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1>
1760 ret <8 x i8> %tmp1
1761 }
1763 define <4 x i16> @and16imm2s_lsl0(<4 x i16> %a) {
1764 ; CHECK-SD-LABEL: and16imm2s_lsl0:
1765 ; CHECK-SD: // %bb.0:
1766 ; CHECK-SD-NEXT: bic v0.2s, #255
1767 ; CHECK-SD-NEXT: ret
1768 ;
1769 ; CHECK-GI-LABEL: and16imm2s_lsl0:
1770 ; CHECK-GI: // %bb.0:
1771 ; CHECK-GI-NEXT: adrp x8, .LCPI112_0
1772 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI112_0]
1773 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1774 ; CHECK-GI-NEXT: ret
1775 %tmp1 = and <4 x i16> %a, < i16 65280, i16 65535, i16 65280, i16 65535>
1776 ret <4 x i16> %tmp1
1777 }
1779 define <4 x i16> @and16imm2s_lsl8(<4 x i16> %a) {
1780 ; CHECK-SD-LABEL: and16imm2s_lsl8:
1781 ; CHECK-SD: // %bb.0:
1782 ; CHECK-SD-NEXT: bic v0.2s, #255, lsl #8
1783 ; CHECK-SD-NEXT: ret
1784 ;
1785 ; CHECK-GI-LABEL: and16imm2s_lsl8:
1786 ; CHECK-GI: // %bb.0:
1787 ; CHECK-GI-NEXT: adrp x8, .LCPI113_0
1788 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI113_0]
1789 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1790 ; CHECK-GI-NEXT: ret
1791 %tmp1 = and <4 x i16> %a, < i16 255, i16 65535, i16 255, i16 65535>
1792 ret <4 x i16> %tmp1
1793 }
1795 define <4 x i16> @and16imm2s_lsl16(<4 x i16> %a) {
1796 ; CHECK-SD-LABEL: and16imm2s_lsl16:
1797 ; CHECK-SD: // %bb.0:
1798 ; CHECK-SD-NEXT: bic v0.2s, #255, lsl #16
1799 ; CHECK-SD-NEXT: ret
1800 ;
1801 ; CHECK-GI-LABEL: and16imm2s_lsl16:
1802 ; CHECK-GI: // %bb.0:
1803 ; CHECK-GI-NEXT: adrp x8, .LCPI114_0
1804 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI114_0]
1805 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1806 ; CHECK-GI-NEXT: ret
1807 %tmp1 = and <4 x i16> %a, < i16 65535, i16 65280, i16 65535, i16 65280>
1808 ret <4 x i16> %tmp1
1809 }
1811 define <4 x i16> @and16imm2s_lsl24(<4 x i16> %a) {
1812 ; CHECK-SD-LABEL: and16imm2s_lsl24:
1813 ; CHECK-SD: // %bb.0:
1814 ; CHECK-SD-NEXT: bic v0.2s, #254, lsl #24
1815 ; CHECK-SD-NEXT: ret
1816 ;
1817 ; CHECK-GI-LABEL: and16imm2s_lsl24:
1818 ; CHECK-GI: // %bb.0:
1819 ; CHECK-GI-NEXT: adrp x8, .LCPI115_0
1820 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI115_0]
1821 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
1822 ; CHECK-GI-NEXT: ret
1823 %tmp1 = and <4 x i16> %a, < i16 65535, i16 511, i16 65535, i16 511>
1824 ret <4 x i16> %tmp1
1825 }
1828 define <1 x i64> @and64imm2s_lsl0(<1 x i64> %a) {
1829 ; CHECK-SD-LABEL: and64imm2s_lsl0:
1830 ; CHECK-SD: // %bb.0:
1831 ; CHECK-SD-NEXT: bic v0.2s, #255
1832 ; CHECK-SD-NEXT: ret
1833 ;
1834 ; CHECK-GI-LABEL: and64imm2s_lsl0:
1835 ; CHECK-GI: // %bb.0:
1836 ; CHECK-GI-NEXT: fmov x8, d0
1837 ; CHECK-GI-NEXT: and x8, x8, #0xffffff00ffffff00
1838 ; CHECK-GI-NEXT: fmov d0, x8
1839 ; CHECK-GI-NEXT: ret
1840 %tmp1 = and <1 x i64> %a, < i64 -1095216660736>
1841 ret <1 x i64> %tmp1
1842 }
1844 define <1 x i64> @and64imm2s_lsl8(<1 x i64> %a) {
1845 ; CHECK-SD-LABEL: and64imm2s_lsl8:
1846 ; CHECK-SD: // %bb.0:
1847 ; CHECK-SD-NEXT: bic v0.2s, #255, lsl #8
1848 ; CHECK-SD-NEXT: ret
1849 ;
1850 ; CHECK-GI-LABEL: and64imm2s_lsl8:
1851 ; CHECK-GI: // %bb.0:
1852 ; CHECK-GI-NEXT: fmov x8, d0
1853 ; CHECK-GI-NEXT: and x8, x8, #0xffff00ffffff00ff
1854 ; CHECK-GI-NEXT: fmov d0, x8
1855 ; CHECK-GI-NEXT: ret
1856 %tmp1 = and <1 x i64> %a, < i64 -280375465148161>
1857 ret <1 x i64> %tmp1
1858 }
1860 define <1 x i64> @and64imm2s_lsl16(<1 x i64> %a) {
1861 ; CHECK-SD-LABEL: and64imm2s_lsl16:
1862 ; CHECK-SD: // %bb.0:
1863 ; CHECK-SD-NEXT: bic v0.2s, #255, lsl #16
1864 ; CHECK-SD-NEXT: ret
1865 ;
1866 ; CHECK-GI-LABEL: and64imm2s_lsl16:
1867 ; CHECK-GI: // %bb.0:
1868 ; CHECK-GI-NEXT: fmov x8, d0
1869 ; CHECK-GI-NEXT: and x8, x8, #0xff00ffffff00ffff
1870 ; CHECK-GI-NEXT: fmov d0, x8
1871 ; CHECK-GI-NEXT: ret
1872 %tmp1 = and <1 x i64> %a, < i64 -71776119077928961>
1873 ret <1 x i64> %tmp1
1874 }
1876 define <1 x i64> @and64imm2s_lsl24(<1 x i64> %a) {
1877 ; CHECK-SD-LABEL: and64imm2s_lsl24:
1878 ; CHECK-SD: // %bb.0:
1879 ; CHECK-SD-NEXT: bic v0.2s, #254, lsl #24
1880 ; CHECK-SD-NEXT: ret
1881 ;
1882 ; CHECK-GI-LABEL: and64imm2s_lsl24:
1883 ; CHECK-GI: // %bb.0:
1884 ; CHECK-GI-NEXT: fmov x8, d0
1885 ; CHECK-GI-NEXT: and x8, x8, #0x1ffffff01ffffff
1886 ; CHECK-GI-NEXT: fmov d0, x8
1887 ; CHECK-GI-NEXT: ret
1888 %tmp1 = and <1 x i64> %a, < i64 144115183814443007>
1889 ret <1 x i64> %tmp1
1890 }
1892 define <16 x i8> @and8imm4s_lsl0(<16 x i8> %a) {
1893 ; CHECK-SD-LABEL: and8imm4s_lsl0:
1894 ; CHECK-SD: // %bb.0:
1895 ; CHECK-SD-NEXT: bic v0.4s, #255
1896 ; CHECK-SD-NEXT: ret
1897 ;
1898 ; CHECK-GI-LABEL: and8imm4s_lsl0:
1899 ; CHECK-GI: // %bb.0:
1900 ; CHECK-GI-NEXT: adrp x8, .LCPI120_0
1901 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI120_0]
1902 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1903 ; CHECK-GI-NEXT: ret
1904 %tmp1 = and <16 x i8> %a, < i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255>
1905 ret <16 x i8> %tmp1
1906 }
1908 define <16 x i8> @and8imm4s_lsl8(<16 x i8> %a) {
1909 ; CHECK-SD-LABEL: and8imm4s_lsl8:
1910 ; CHECK-SD: // %bb.0:
1911 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #8
1912 ; CHECK-SD-NEXT: ret
1913 ;
1914 ; CHECK-GI-LABEL: and8imm4s_lsl8:
1915 ; CHECK-GI: // %bb.0:
1916 ; CHECK-GI-NEXT: adrp x8, .LCPI121_0
1917 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI121_0]
1918 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1919 ; CHECK-GI-NEXT: ret
1920 %tmp1 = and <16 x i8> %a, < i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255>
1921 ret <16 x i8> %tmp1
1922 }
1924 define <16 x i8> @and8imm4s_lsl16(<16 x i8> %a) {
1925 ; CHECK-SD-LABEL: and8imm4s_lsl16:
1926 ; CHECK-SD: // %bb.0:
1927 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #16
1928 ; CHECK-SD-NEXT: ret
1929 ;
1930 ; CHECK-GI-LABEL: and8imm4s_lsl16:
1931 ; CHECK-GI: // %bb.0:
1932 ; CHECK-GI-NEXT: adrp x8, .LCPI122_0
1933 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI122_0]
1934 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1935 ; CHECK-GI-NEXT: ret
1936 %tmp1 = and <16 x i8> %a, < i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255>
1937 ret <16 x i8> %tmp1
1938 }
1940 define <16 x i8> @and8imm4s_lsl24(<16 x i8> %a) {
1941 ; CHECK-SD-LABEL: and8imm4s_lsl24:
1942 ; CHECK-SD: // %bb.0:
1943 ; CHECK-SD-NEXT: bic v0.4s, #254, lsl #24
1944 ; CHECK-SD-NEXT: ret
1945 ;
1946 ; CHECK-GI-LABEL: and8imm4s_lsl24:
1947 ; CHECK-GI: // %bb.0:
1948 ; CHECK-GI-NEXT: adrp x8, .LCPI123_0
1949 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI123_0]
1950 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1951 ; CHECK-GI-NEXT: ret
1952 %tmp1 = and <16 x i8> %a, < i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1>
1953 ret <16 x i8> %tmp1
1954 }
1956 define <8 x i16> @and16imm4s_lsl0(<8 x i16> %a) {
1957 ; CHECK-SD-LABEL: and16imm4s_lsl0:
1958 ; CHECK-SD: // %bb.0:
1959 ; CHECK-SD-NEXT: bic v0.4s, #255
1960 ; CHECK-SD-NEXT: ret
1961 ;
1962 ; CHECK-GI-LABEL: and16imm4s_lsl0:
1963 ; CHECK-GI: // %bb.0:
1964 ; CHECK-GI-NEXT: adrp x8, .LCPI124_0
1965 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI124_0]
1966 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1967 ; CHECK-GI-NEXT: ret
1968 %tmp1 = and <8 x i16> %a, < i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535>
1969 ret <8 x i16> %tmp1
1970 }
1972 define <8 x i16> @and16imm4s_lsl8(<8 x i16> %a) {
1973 ; CHECK-SD-LABEL: and16imm4s_lsl8:
1974 ; CHECK-SD: // %bb.0:
1975 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #8
1976 ; CHECK-SD-NEXT: ret
1977 ;
1978 ; CHECK-GI-LABEL: and16imm4s_lsl8:
1979 ; CHECK-GI: // %bb.0:
1980 ; CHECK-GI-NEXT: adrp x8, .LCPI125_0
1981 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI125_0]
1982 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1983 ; CHECK-GI-NEXT: ret
1984 %tmp1 = and <8 x i16> %a, < i16 255, i16 65535, i16 255, i16 65535, i16 255, i16 65535, i16 255, i16 65535>
1985 ret <8 x i16> %tmp1
1986 }
1988 define <8 x i16> @and16imm4s_lsl16(<8 x i16> %a) {
1989 ; CHECK-SD-LABEL: and16imm4s_lsl16:
1990 ; CHECK-SD: // %bb.0:
1991 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #16
1992 ; CHECK-SD-NEXT: ret
1993 ;
1994 ; CHECK-GI-LABEL: and16imm4s_lsl16:
1995 ; CHECK-GI: // %bb.0:
1996 ; CHECK-GI-NEXT: adrp x8, .LCPI126_0
1997 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI126_0]
1998 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
1999 ; CHECK-GI-NEXT: ret
2000 %tmp1 = and <8 x i16> %a, < i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280>
2001 ret <8 x i16> %tmp1
2002 }
2004 define <8 x i16> @and16imm4s_lsl24(<8 x i16> %a) {
2005 ; CHECK-SD-LABEL: and16imm4s_lsl24:
2006 ; CHECK-SD: // %bb.0:
2007 ; CHECK-SD-NEXT: bic v0.4s, #254, lsl #24
2008 ; CHECK-SD-NEXT: ret
2009 ;
2010 ; CHECK-GI-LABEL: and16imm4s_lsl24:
2011 ; CHECK-GI: // %bb.0:
2012 ; CHECK-GI-NEXT: adrp x8, .LCPI127_0
2013 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI127_0]
2014 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2015 ; CHECK-GI-NEXT: ret
2016 %tmp1 = and <8 x i16> %a, < i16 65535, i16 511, i16 65535, i16 511, i16 65535, i16 511, i16 65535, i16 511>
2017 ret <8 x i16> %tmp1
2018 }
2020 define <2 x i64> @and64imm4s_lsl0(<2 x i64> %a) {
2021 ; CHECK-SD-LABEL: and64imm4s_lsl0:
2022 ; CHECK-SD: // %bb.0:
2023 ; CHECK-SD-NEXT: bic v0.4s, #255
2024 ; CHECK-SD-NEXT: ret
2025 ;
2026 ; CHECK-GI-LABEL: and64imm4s_lsl0:
2027 ; CHECK-GI: // %bb.0:
2028 ; CHECK-GI-NEXT: adrp x8, .LCPI128_0
2029 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI128_0]
2030 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2031 ; CHECK-GI-NEXT: ret
2032 %tmp1 = and <2 x i64> %a, < i64 -1095216660736, i64 -1095216660736>
2033 ret <2 x i64> %tmp1
2034 }
2036 define <2 x i64> @and64imm4s_lsl8(<2 x i64> %a) {
2037 ; CHECK-SD-LABEL: and64imm4s_lsl8:
2038 ; CHECK-SD: // %bb.0:
2039 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #8
2040 ; CHECK-SD-NEXT: ret
2041 ;
2042 ; CHECK-GI-LABEL: and64imm4s_lsl8:
2043 ; CHECK-GI: // %bb.0:
2044 ; CHECK-GI-NEXT: adrp x8, .LCPI129_0
2045 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI129_0]
2046 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2047 ; CHECK-GI-NEXT: ret
2048 %tmp1 = and <2 x i64> %a, < i64 -280375465148161, i64 -280375465148161>
2049 ret <2 x i64> %tmp1
2050 }
2052 define <2 x i64> @and64imm4s_lsl16(<2 x i64> %a) {
2053 ; CHECK-SD-LABEL: and64imm4s_lsl16:
2054 ; CHECK-SD: // %bb.0:
2055 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #16
2056 ; CHECK-SD-NEXT: ret
2057 ;
2058 ; CHECK-GI-LABEL: and64imm4s_lsl16:
2059 ; CHECK-GI: // %bb.0:
2060 ; CHECK-GI-NEXT: adrp x8, .LCPI130_0
2061 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI130_0]
2062 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2063 ; CHECK-GI-NEXT: ret
2064 %tmp1 = and <2 x i64> %a, < i64 -71776119077928961, i64 -71776119077928961>
2065 ret <2 x i64> %tmp1
2066 }
2068 define <2 x i64> @and64imm4s_lsl24(<2 x i64> %a) {
2069 ; CHECK-SD-LABEL: and64imm4s_lsl24:
2070 ; CHECK-SD: // %bb.0:
2071 ; CHECK-SD-NEXT: bic v0.4s, #254, lsl #24
2072 ; CHECK-SD-NEXT: ret
2073 ;
2074 ; CHECK-GI-LABEL: and64imm4s_lsl24:
2075 ; CHECK-GI: // %bb.0:
2076 ; CHECK-GI-NEXT: adrp x8, .LCPI131_0
2077 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI131_0]
2078 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2079 ; CHECK-GI-NEXT: ret
2080 %tmp1 = and <2 x i64> %a, < i64 144115183814443007, i64 144115183814443007>
2081 ret <2 x i64> %tmp1
2082 }
2084 define <8 x i8> @and8imm4h_lsl0(<8 x i8> %a) {
2085 ; CHECK-SD-LABEL: and8imm4h_lsl0:
2086 ; CHECK-SD: // %bb.0:
2087 ; CHECK-SD-NEXT: bic v0.4h, #255
2088 ; CHECK-SD-NEXT: ret
2089 ;
2090 ; CHECK-GI-LABEL: and8imm4h_lsl0:
2091 ; CHECK-GI: // %bb.0:
2092 ; CHECK-GI-NEXT: adrp x8, .LCPI132_0
2093 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI132_0]
2094 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
2095 ; CHECK-GI-NEXT: ret
2096 %tmp1 = and <8 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
2097 ret <8 x i8> %tmp1
2098 }
2100 define <8 x i8> @and8imm4h_lsl8(<8 x i8> %a) {
2101 ; CHECK-SD-LABEL: and8imm4h_lsl8:
2102 ; CHECK-SD: // %bb.0:
2103 ; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
2104 ; CHECK-SD-NEXT: ret
2105 ;
2106 ; CHECK-GI-LABEL: and8imm4h_lsl8:
2107 ; CHECK-GI: // %bb.0:
2108 ; CHECK-GI-NEXT: adrp x8, .LCPI133_0
2109 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI133_0]
2110 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
2111 ; CHECK-GI-NEXT: ret
2112 %tmp1 = and <8 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
2113 ret <8 x i8> %tmp1
2114 }
2116 define <2 x i32> @and16imm4h_lsl0(<2 x i32> %a) {
2117 ; CHECK-SD-LABEL: and16imm4h_lsl0:
2118 ; CHECK-SD: // %bb.0:
2119 ; CHECK-SD-NEXT: bic v0.4h, #255
2120 ; CHECK-SD-NEXT: ret
2121 ;
2122 ; CHECK-GI-LABEL: and16imm4h_lsl0:
2123 ; CHECK-GI: // %bb.0:
2124 ; CHECK-GI-NEXT: adrp x8, .LCPI134_0
2125 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI134_0]
2126 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
2127 ; CHECK-GI-NEXT: ret
2128 %tmp1 = and <2 x i32> %a, < i32 4278255360, i32 4278255360>
2129 ret <2 x i32> %tmp1
2130 }
2132 define <2 x i32> @and16imm4h_lsl8(<2 x i32> %a) {
2133 ; CHECK-SD-LABEL: and16imm4h_lsl8:
2134 ; CHECK-SD: // %bb.0:
2135 ; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
2136 ; CHECK-SD-NEXT: ret
2137 ;
2138 ; CHECK-GI-LABEL: and16imm4h_lsl8:
2139 ; CHECK-GI: // %bb.0:
2140 ; CHECK-GI-NEXT: adrp x8, .LCPI135_0
2141 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI135_0]
2142 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
2143 ; CHECK-GI-NEXT: ret
2144 %tmp1 = and <2 x i32> %a, < i32 16711935, i32 16711935>
2145 ret <2 x i32> %tmp1
2146 }
2148 define <1 x i64> @and64imm4h_lsl0(<1 x i64> %a) {
2149 ; CHECK-SD-LABEL: and64imm4h_lsl0:
2150 ; CHECK-SD: // %bb.0:
2151 ; CHECK-SD-NEXT: bic v0.4h, #255
2152 ; CHECK-SD-NEXT: ret
2153 ;
2154 ; CHECK-GI-LABEL: and64imm4h_lsl0:
2155 ; CHECK-GI: // %bb.0:
2156 ; CHECK-GI-NEXT: fmov x8, d0
2157 ; CHECK-GI-NEXT: and x8, x8, #0xff00ff00ff00ff00
2158 ; CHECK-GI-NEXT: fmov d0, x8
2159 ; CHECK-GI-NEXT: ret
2160 %tmp1 = and <1 x i64> %a, < i64 -71777214294589696>
2161 ret <1 x i64> %tmp1
2162 }
2164 define <1 x i64> @and64imm4h_lsl8(<1 x i64> %a) {
2165 ; CHECK-SD-LABEL: and64imm4h_lsl8:
2166 ; CHECK-SD: // %bb.0:
2167 ; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
2168 ; CHECK-SD-NEXT: ret
2169 ;
2170 ; CHECK-GI-LABEL: and64imm4h_lsl8:
2171 ; CHECK-GI: // %bb.0:
2172 ; CHECK-GI-NEXT: fmov x8, d0
2173 ; CHECK-GI-NEXT: and x8, x8, #0xff00ff00ff00ff
2174 ; CHECK-GI-NEXT: fmov d0, x8
2175 ; CHECK-GI-NEXT: ret
2176 %tmp1 = and <1 x i64> %a, < i64 71777214294589695>
2177 ret <1 x i64> %tmp1
2178 }
2180 define <16 x i8> @and8imm8h_lsl0(<16 x i8> %a) {
2181 ; CHECK-SD-LABEL: and8imm8h_lsl0:
2182 ; CHECK-SD: // %bb.0:
2183 ; CHECK-SD-NEXT: bic v0.8h, #255
2184 ; CHECK-SD-NEXT: ret
2185 ;
2186 ; CHECK-GI-LABEL: and8imm8h_lsl0:
2187 ; CHECK-GI: // %bb.0:
2188 ; CHECK-GI-NEXT: adrp x8, .LCPI138_0
2189 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI138_0]
2190 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2191 ; CHECK-GI-NEXT: ret
2192 %tmp1 = and <16 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255 >
2193 ret <16 x i8> %tmp1
2194 }
2196 define <16 x i8> @and8imm8h_lsl8(<16 x i8> %a) {
2197 ; CHECK-SD-LABEL: and8imm8h_lsl8:
2198 ; CHECK-SD: // %bb.0:
2199 ; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8
2200 ; CHECK-SD-NEXT: ret
2201 ;
2202 ; CHECK-GI-LABEL: and8imm8h_lsl8:
2203 ; CHECK-GI: // %bb.0:
2204 ; CHECK-GI-NEXT: adrp x8, .LCPI139_0
2205 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI139_0]
2206 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2207 ; CHECK-GI-NEXT: ret
2208 %tmp1 = and <16 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0 >
2209 ret <16 x i8> %tmp1
2210 }
2212 define <4 x i32> @and16imm8h_lsl0(<4 x i32> %a) {
2213 ; CHECK-SD-LABEL: and16imm8h_lsl0:
2214 ; CHECK-SD: // %bb.0:
2215 ; CHECK-SD-NEXT: bic v0.8h, #255
2216 ; CHECK-SD-NEXT: ret
2217 ;
2218 ; CHECK-GI-LABEL: and16imm8h_lsl0:
2219 ; CHECK-GI: // %bb.0:
2220 ; CHECK-GI-NEXT: adrp x8, .LCPI140_0
2221 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI140_0]
2222 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2223 ; CHECK-GI-NEXT: ret
2224 %tmp1 = and <4 x i32> %a, < i32 4278255360, i32 4278255360, i32 4278255360, i32 4278255360>
2225 ret <4 x i32> %tmp1
2226 }
2228 define <4 x i32> @and16imm8h_lsl8(<4 x i32> %a) {
2229 ; CHECK-SD-LABEL: and16imm8h_lsl8:
2230 ; CHECK-SD: // %bb.0:
2231 ; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8
2232 ; CHECK-SD-NEXT: ret
2233 ;
2234 ; CHECK-GI-LABEL: and16imm8h_lsl8:
2235 ; CHECK-GI: // %bb.0:
2236 ; CHECK-GI-NEXT: adrp x8, .LCPI141_0
2237 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI141_0]
2238 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2239 ; CHECK-GI-NEXT: ret
2240 %tmp1 = and <4 x i32> %a, < i32 16711935, i32 16711935, i32 16711935, i32 16711935>
2241 ret <4 x i32> %tmp1
2242 }
2244 define <2 x i64> @and64imm8h_lsl0(<2 x i64> %a) {
2245 ; CHECK-SD-LABEL: and64imm8h_lsl0:
2246 ; CHECK-SD: // %bb.0:
2247 ; CHECK-SD-NEXT: bic v0.8h, #255
2248 ; CHECK-SD-NEXT: ret
2249 ;
2250 ; CHECK-GI-LABEL: and64imm8h_lsl0:
2251 ; CHECK-GI: // %bb.0:
2252 ; CHECK-GI-NEXT: adrp x8, .LCPI142_0
2253 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI142_0]
2254 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2255 ; CHECK-GI-NEXT: ret
2256 %tmp1 = and <2 x i64> %a, < i64 -71777214294589696, i64 -71777214294589696>
2257 ret <2 x i64> %tmp1
2258 }
2260 define <2 x i64> @and64imm8h_lsl8(<2 x i64> %a) {
2261 ; CHECK-SD-LABEL: and64imm8h_lsl8:
2262 ; CHECK-SD: // %bb.0:
2263 ; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8
2264 ; CHECK-SD-NEXT: ret
2265 ;
2266 ; CHECK-GI-LABEL: and64imm8h_lsl8:
2267 ; CHECK-GI: // %bb.0:
2268 ; CHECK-GI-NEXT: adrp x8, .LCPI143_0
2269 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI143_0]
2270 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2271 ; CHECK-GI-NEXT: ret
2272 %tmp1 = and <2 x i64> %a, < i64 71777214294589695, i64 71777214294589695>
2273 ret <2 x i64> %tmp1
2274 }
2276 define <8 x i16> @bic_shifted_knownbits(<8 x i16> %v) {
2277 ; CHECK-SD-LABEL: bic_shifted_knownbits:
2278 ; CHECK-SD: // %bb.0: // %entry
2279 ; CHECK-SD-NEXT: ushr v0.8h, v0.8h, #9
2280 ; CHECK-SD-NEXT: bic v0.8h, #126
2281 ; CHECK-SD-NEXT: ret
2282 ;
2283 ; CHECK-GI-LABEL: bic_shifted_knownbits:
2284 ; CHECK-GI: // %bb.0: // %entry
2285 ; CHECK-GI-NEXT: adrp x8, .LCPI144_0
2286 ; CHECK-GI-NEXT: ushr v0.8h, v0.8h, #9
2287 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI144_0]
2288 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
2289 ; CHECK-GI-NEXT: ret
2290 entry:
2291 %vshr_n = lshr <8 x i16> %v, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
2292 %and.i = and <8 x i16> %vshr_n, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
2293 ret <8 x i16> %and.i
2294 }
2296 define <8 x i32> @bic_shifted_knownbits2(<8 x i16> %v) {
2297 ; CHECK-SD-LABEL: bic_shifted_knownbits2:
2298 ; CHECK-SD: // %bb.0: // %entry
2299 ; CHECK-SD-NEXT: ushll v2.4s, v0.4h, #0
2300 ; CHECK-SD-NEXT: ushll2 v1.4s, v0.8h, #0
2301 ; CHECK-SD-NEXT: bic v2.4s, #255, lsl #8
2302 ; CHECK-SD-NEXT: bic v1.4s, #255, lsl #8
2303 ; CHECK-SD-NEXT: mov v0.16b, v2.16b
2304 ; CHECK-SD-NEXT: ret
2305 ;
2306 ; CHECK-GI-LABEL: bic_shifted_knownbits2:
2307 ; CHECK-GI: // %bb.0: // %entry
2308 ; CHECK-GI-NEXT: adrp x8, .LCPI145_0
2309 ; CHECK-GI-NEXT: ushll v1.4s, v0.4h, #0
2310 ; CHECK-GI-NEXT: ushll2 v2.4s, v0.8h, #0
2311 ; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI145_0]
2312 ; CHECK-GI-NEXT: and v0.16b, v1.16b, v3.16b
2313 ; CHECK-GI-NEXT: and v1.16b, v2.16b, v3.16b
2314 ; CHECK-GI-NEXT: ret
2315 entry:
2316 %vshr_n = zext <8 x i16> %v to <8 x i32>
2317 %and.i = and <8 x i32> %vshr_n, <i32 4293918975, i32 4293918975, i32 4293918975, i32 4293918975, i32 4293918975, i32 4293918975, i32 4293918975, i32 4293918975>
2318 ret <8 x i32> %and.i
2319 }
2321 define <8 x i32> @bic_shifted_knownbits3(<8 x i16> %v) {
2322 ; CHECK-SD-LABEL: bic_shifted_knownbits3:
2323 ; CHECK-SD: // %bb.0:
2324 ; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8
2325 ; CHECK-SD-NEXT: ushll2 v1.4s, v0.8h, #0
2326 ; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
2327 ; CHECK-SD-NEXT: ret
2328 ;
2329 ; CHECK-GI-LABEL: bic_shifted_knownbits3:
2330 ; CHECK-GI: // %bb.0:
2331 ; CHECK-GI-NEXT: adrp x8, .LCPI146_0
2332 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI146_0]
2333 ; CHECK-GI-NEXT: and v1.16b, v0.16b, v1.16b
2334 ; CHECK-GI-NEXT: ushll v0.4s, v1.4h, #0
2335 ; CHECK-GI-NEXT: ushll2 v1.4s, v1.8h, #0
2336 ; CHECK-GI-NEXT: ret
2337 %a = and <8 x i16> %v, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
2338 %and.i = zext <8 x i16> %a to <8 x i32>
2339 ret <8 x i32> %and.i
2340 }
2343 define <8 x i32> @bic_shifted_knownbits4(<8 x i32> %v) {
2344 ; CHECK-SD-LABEL: bic_shifted_knownbits4:
2345 ; CHECK-SD: // %bb.0: // %entry
2346 ; CHECK-SD-NEXT: shl v1.4s, v1.4s, #8
2347 ; CHECK-SD-NEXT: shl v0.4s, v0.4s, #8
2348 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #8
2349 ; CHECK-SD-NEXT: bic v1.4s, #255, lsl #8
2350 ; CHECK-SD-NEXT: ret
2351 ;
2352 ; CHECK-GI-LABEL: bic_shifted_knownbits4:
2353 ; CHECK-GI: // %bb.0: // %entry
2354 ; CHECK-GI-NEXT: adrp x8, .LCPI147_0
2355 ; CHECK-GI-NEXT: shl v0.4s, v0.4s, #8
2356 ; CHECK-GI-NEXT: shl v1.4s, v1.4s, #8
2357 ; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI147_0]
2358 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b
2359 ; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b
2360 ; CHECK-GI-NEXT: ret
2361 entry:
2362 %vshr_n = shl <8 x i32> %v, <i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
2363 %and.i = and <8 x i32> %vshr_n, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>
2364 ret <8 x i32> %and.i
2365 }
2367 define <8 x i8> @orr8imm2s_lsl0(<8 x i8> %a) {
2368 ; CHECK-SD-LABEL: orr8imm2s_lsl0:
2369 ; CHECK-SD: // %bb.0:
2370 ; CHECK-SD-NEXT: orr v0.2s, #255
2371 ; CHECK-SD-NEXT: ret
2372 ;
2373 ; CHECK-GI-LABEL: orr8imm2s_lsl0:
2374 ; CHECK-GI: // %bb.0:
2375 ; CHECK-GI-NEXT: adrp x8, .LCPI148_0
2376 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI148_0]
2377 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2378 ; CHECK-GI-NEXT: ret
2379 %tmp1 = or <8 x i8> %a, < i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0>
2380 ret <8 x i8> %tmp1
2381 }
2383 define <8 x i8> @orr8imm2s_lsl8(<8 x i8> %a) {
2384 ; CHECK-SD-LABEL: orr8imm2s_lsl8:
2385 ; CHECK-SD: // %bb.0:
2386 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #8
2387 ; CHECK-SD-NEXT: ret
2388 ;
2389 ; CHECK-GI-LABEL: orr8imm2s_lsl8:
2390 ; CHECK-GI: // %bb.0:
2391 ; CHECK-GI-NEXT: adrp x8, .LCPI149_0
2392 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI149_0]
2393 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2394 ; CHECK-GI-NEXT: ret
2395 %tmp1 = or <8 x i8> %a, < i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0>
2396 ret <8 x i8> %tmp1
2397 }
2399 define <8 x i8> @orr8imm2s_lsl16(<8 x i8> %a) {
2400 ; CHECK-SD-LABEL: orr8imm2s_lsl16:
2401 ; CHECK-SD: // %bb.0:
2402 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #16
2403 ; CHECK-SD-NEXT: ret
2404 ;
2405 ; CHECK-GI-LABEL: orr8imm2s_lsl16:
2406 ; CHECK-GI: // %bb.0:
2407 ; CHECK-GI-NEXT: adrp x8, .LCPI150_0
2408 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI150_0]
2409 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2410 ; CHECK-GI-NEXT: ret
2411 %tmp1 = or <8 x i8> %a, < i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0>
2412 ret <8 x i8> %tmp1
2413 }
2415 define <8 x i8> @orr8imm2s_lsl24(<8 x i8> %a) {
2416 ; CHECK-SD-LABEL: orr8imm2s_lsl24:
2417 ; CHECK-SD: // %bb.0:
2418 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #24
2419 ; CHECK-SD-NEXT: ret
2420 ;
2421 ; CHECK-GI-LABEL: orr8imm2s_lsl24:
2422 ; CHECK-GI: // %bb.0:
2423 ; CHECK-GI-NEXT: adrp x8, .LCPI151_0
2424 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI151_0]
2425 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2426 ; CHECK-GI-NEXT: ret
2427 %tmp1 = or <8 x i8> %a, < i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255>
2428 ret <8 x i8> %tmp1
2429 }
2431 define <4 x i16> @orr16imm2s_lsl0(<4 x i16> %a) {
2432 ; CHECK-SD-LABEL: orr16imm2s_lsl0:
2433 ; CHECK-SD: // %bb.0:
2434 ; CHECK-SD-NEXT: orr v0.2s, #255
2435 ; CHECK-SD-NEXT: ret
2436 ;
2437 ; CHECK-GI-LABEL: orr16imm2s_lsl0:
2438 ; CHECK-GI: // %bb.0:
2439 ; CHECK-GI-NEXT: adrp x8, .LCPI152_0
2440 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI152_0]
2441 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2442 ; CHECK-GI-NEXT: ret
2443 %tmp1 = or <4 x i16> %a, < i16 255, i16 0, i16 255, i16 0>
2444 ret <4 x i16> %tmp1
2445 }
2447 define <4 x i16> @orr16imm2s_lsl8(<4 x i16> %a) {
2448 ; CHECK-SD-LABEL: orr16imm2s_lsl8:
2449 ; CHECK-SD: // %bb.0:
2450 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #8
2451 ; CHECK-SD-NEXT: ret
2452 ;
2453 ; CHECK-GI-LABEL: orr16imm2s_lsl8:
2454 ; CHECK-GI: // %bb.0:
2455 ; CHECK-GI-NEXT: adrp x8, .LCPI153_0
2456 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI153_0]
2457 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2458 ; CHECK-GI-NEXT: ret
2459 %tmp1 = or <4 x i16> %a, < i16 65280, i16 0, i16 65280, i16 0>
2460 ret <4 x i16> %tmp1
2461 }
2463 define <4 x i16> @orr16imm2s_lsl16(<4 x i16> %a) {
2464 ; CHECK-SD-LABEL: orr16imm2s_lsl16:
2465 ; CHECK-SD: // %bb.0:
2466 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #16
2467 ; CHECK-SD-NEXT: ret
2468 ;
2469 ; CHECK-GI-LABEL: orr16imm2s_lsl16:
2470 ; CHECK-GI: // %bb.0:
2471 ; CHECK-GI-NEXT: adrp x8, .LCPI154_0
2472 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI154_0]
2473 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2474 ; CHECK-GI-NEXT: ret
2475 %tmp1 = or <4 x i16> %a, < i16 0, i16 255, i16 0, i16 255>
2476 ret <4 x i16> %tmp1
2477 }
2479 define <4 x i16> @orr16imm2s_lsl24(<4 x i16> %a) {
2480 ; CHECK-SD-LABEL: orr16imm2s_lsl24:
2481 ; CHECK-SD: // %bb.0:
2482 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #24
2483 ; CHECK-SD-NEXT: ret
2484 ;
2485 ; CHECK-GI-LABEL: orr16imm2s_lsl24:
2486 ; CHECK-GI: // %bb.0:
2487 ; CHECK-GI-NEXT: adrp x8, .LCPI155_0
2488 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI155_0]
2489 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2490 ; CHECK-GI-NEXT: ret
2491 %tmp1 = or <4 x i16> %a, < i16 0, i16 65280, i16 0, i16 65280>
2492 ret <4 x i16> %tmp1
2493 }
2495 define <1 x i64> @orr64imm2s_lsl0(<1 x i64> %a) {
2496 ; CHECK-SD-LABEL: orr64imm2s_lsl0:
2497 ; CHECK-SD: // %bb.0:
2498 ; CHECK-SD-NEXT: orr v0.2s, #255
2499 ; CHECK-SD-NEXT: ret
2500 ;
2501 ; CHECK-GI-LABEL: orr64imm2s_lsl0:
2502 ; CHECK-GI: // %bb.0:
2503 ; CHECK-GI-NEXT: fmov x8, d0
2504 ; CHECK-GI-NEXT: orr x8, x8, #0xff000000ff
2505 ; CHECK-GI-NEXT: fmov d0, x8
2506 ; CHECK-GI-NEXT: ret
2507 %tmp1 = or <1 x i64> %a, < i64 1095216660735>
2508 ret <1 x i64> %tmp1
2509 }
2511 define <1 x i64> @orr64imm2s_lsl8(<1 x i64> %a) {
2512 ; CHECK-SD-LABEL: orr64imm2s_lsl8:
2513 ; CHECK-SD: // %bb.0:
2514 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #8
2515 ; CHECK-SD-NEXT: ret
2516 ;
2517 ; CHECK-GI-LABEL: orr64imm2s_lsl8:
2518 ; CHECK-GI: // %bb.0:
2519 ; CHECK-GI-NEXT: fmov x8, d0
2520 ; CHECK-GI-NEXT: orr x8, x8, #0xff000000ff00
2521 ; CHECK-GI-NEXT: fmov d0, x8
2522 ; CHECK-GI-NEXT: ret
2523 %tmp1 = or <1 x i64> %a, < i64 280375465148160>
2524 ret <1 x i64> %tmp1
2525 }
2527 define <1 x i64> @orr64imm2s_lsl16(<1 x i64> %a) {
2528 ; CHECK-SD-LABEL: orr64imm2s_lsl16:
2529 ; CHECK-SD: // %bb.0:
2530 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #16
2531 ; CHECK-SD-NEXT: ret
2532 ;
2533 ; CHECK-GI-LABEL: orr64imm2s_lsl16:
2534 ; CHECK-GI: // %bb.0:
2535 ; CHECK-GI-NEXT: fmov x8, d0
2536 ; CHECK-GI-NEXT: orr x8, x8, #0xff000000ff0000
2537 ; CHECK-GI-NEXT: fmov d0, x8
2538 ; CHECK-GI-NEXT: ret
2539 %tmp1 = or <1 x i64> %a, < i64 71776119077928960>
2540 ret <1 x i64> %tmp1
2541 }
2543 define <1 x i64> @orr64imm2s_lsl24(<1 x i64> %a) {
2544 ; CHECK-SD-LABEL: orr64imm2s_lsl24:
2545 ; CHECK-SD: // %bb.0:
2546 ; CHECK-SD-NEXT: orr v0.2s, #255, lsl #24
2547 ; CHECK-SD-NEXT: ret
2548 ;
2549 ; CHECK-GI-LABEL: orr64imm2s_lsl24:
2550 ; CHECK-GI: // %bb.0:
2551 ; CHECK-GI-NEXT: fmov x8, d0
2552 ; CHECK-GI-NEXT: orr x8, x8, #0xff000000ff000000
2553 ; CHECK-GI-NEXT: fmov d0, x8
2554 ; CHECK-GI-NEXT: ret
2555 %tmp1 = or <1 x i64> %a, < i64 -72057589759737856>
2556 ret <1 x i64> %tmp1
2557 }
2559 define <16 x i8> @orr8imm4s_lsl0(<16 x i8> %a) {
2560 ; CHECK-SD-LABEL: orr8imm4s_lsl0:
2561 ; CHECK-SD: // %bb.0:
2562 ; CHECK-SD-NEXT: orr v0.4s, #255
2563 ; CHECK-SD-NEXT: ret
2564 ;
2565 ; CHECK-GI-LABEL: orr8imm4s_lsl0:
2566 ; CHECK-GI: // %bb.0:
2567 ; CHECK-GI-NEXT: adrp x8, .LCPI160_0
2568 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI160_0]
2569 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2570 ; CHECK-GI-NEXT: ret
2571 %tmp1 = or <16 x i8> %a, < i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0>
2572 ret <16 x i8> %tmp1
2573 }
2575 define <16 x i8> @orr8imm4s_lsl8(<16 x i8> %a) {
2576 ; CHECK-SD-LABEL: orr8imm4s_lsl8:
2577 ; CHECK-SD: // %bb.0:
2578 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #8
2579 ; CHECK-SD-NEXT: ret
2580 ;
2581 ; CHECK-GI-LABEL: orr8imm4s_lsl8:
2582 ; CHECK-GI: // %bb.0:
2583 ; CHECK-GI-NEXT: adrp x8, .LCPI161_0
2584 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI161_0]
2585 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2586 ; CHECK-GI-NEXT: ret
2587 %tmp1 = or <16 x i8> %a, < i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0>
2588 ret <16 x i8> %tmp1
2589 }
2591 define <16 x i8> @orr8imm4s_lsl16(<16 x i8> %a) {
2592 ; CHECK-SD-LABEL: orr8imm4s_lsl16:
2593 ; CHECK-SD: // %bb.0:
2594 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #16
2595 ; CHECK-SD-NEXT: ret
2596 ;
2597 ; CHECK-GI-LABEL: orr8imm4s_lsl16:
2598 ; CHECK-GI: // %bb.0:
2599 ; CHECK-GI-NEXT: adrp x8, .LCPI162_0
2600 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI162_0]
2601 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2602 ; CHECK-GI-NEXT: ret
2603 %tmp1 = or <16 x i8> %a, < i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0>
2604 ret <16 x i8> %tmp1
2605 }
2607 define <16 x i8> @orr8imm4s_lsl24(<16 x i8> %a) {
2608 ; CHECK-SD-LABEL: orr8imm4s_lsl24:
2609 ; CHECK-SD: // %bb.0:
2610 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #24
2611 ; CHECK-SD-NEXT: ret
2612 ;
2613 ; CHECK-GI-LABEL: orr8imm4s_lsl24:
2614 ; CHECK-GI: // %bb.0:
2615 ; CHECK-GI-NEXT: adrp x8, .LCPI163_0
2616 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI163_0]
2617 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2618 ; CHECK-GI-NEXT: ret
2619 %tmp1 = or <16 x i8> %a, < i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255>
2620 ret <16 x i8> %tmp1
2621 }
2623 define <8 x i16> @orr16imm4s_lsl0(<8 x i16> %a) {
2624 ; CHECK-SD-LABEL: orr16imm4s_lsl0:
2625 ; CHECK-SD: // %bb.0:
2626 ; CHECK-SD-NEXT: orr v0.4s, #255
2627 ; CHECK-SD-NEXT: ret
2628 ;
2629 ; CHECK-GI-LABEL: orr16imm4s_lsl0:
2630 ; CHECK-GI: // %bb.0:
2631 ; CHECK-GI-NEXT: adrp x8, .LCPI164_0
2632 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI164_0]
2633 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2634 ; CHECK-GI-NEXT: ret
2635 %tmp1 = or <8 x i16> %a, < i16 255, i16 0, i16 255, i16 0, i16 255, i16 0, i16 255, i16 0>
2636 ret <8 x i16> %tmp1
2637 }
2639 define <8 x i16> @orr16imm4s_lsl8(<8 x i16> %a) {
2640 ; CHECK-SD-LABEL: orr16imm4s_lsl8:
2641 ; CHECK-SD: // %bb.0:
2642 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #8
2643 ; CHECK-SD-NEXT: ret
2644 ;
2645 ; CHECK-GI-LABEL: orr16imm4s_lsl8:
2646 ; CHECK-GI: // %bb.0:
2647 ; CHECK-GI-NEXT: adrp x8, .LCPI165_0
2648 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI165_0]
2649 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2650 ; CHECK-GI-NEXT: ret
2651 %tmp1 = or <8 x i16> %a, < i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0>
2652 ret <8 x i16> %tmp1
2653 }
2655 define <8 x i16> @orr16imm4s_lsl16(<8 x i16> %a) {
2656 ; CHECK-SD-LABEL: orr16imm4s_lsl16:
2657 ; CHECK-SD: // %bb.0:
2658 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #16
2659 ; CHECK-SD-NEXT: ret
2660 ;
2661 ; CHECK-GI-LABEL: orr16imm4s_lsl16:
2662 ; CHECK-GI: // %bb.0:
2663 ; CHECK-GI-NEXT: adrp x8, .LCPI166_0
2664 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI166_0]
2665 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2666 ; CHECK-GI-NEXT: ret
2667 %tmp1 = or <8 x i16> %a, < i16 0, i16 255, i16 0, i16 255, i16 0, i16 255, i16 0, i16 255>
2668 ret <8 x i16> %tmp1
2669 }
2671 define <8 x i16> @orr16imm4s_lsl24(<8 x i16> %a) {
2672 ; CHECK-SD-LABEL: orr16imm4s_lsl24:
2673 ; CHECK-SD: // %bb.0:
2674 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #24
2675 ; CHECK-SD-NEXT: ret
2676 ;
2677 ; CHECK-GI-LABEL: orr16imm4s_lsl24:
2678 ; CHECK-GI: // %bb.0:
2679 ; CHECK-GI-NEXT: adrp x8, .LCPI167_0
2680 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI167_0]
2681 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2682 ; CHECK-GI-NEXT: ret
2683 %tmp1 = or <8 x i16> %a, < i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280>
2684 ret <8 x i16> %tmp1
2685 }
2687 define <2 x i64> @orr64imm4s_lsl0(<2 x i64> %a) {
2688 ; CHECK-SD-LABEL: orr64imm4s_lsl0:
2689 ; CHECK-SD: // %bb.0:
2690 ; CHECK-SD-NEXT: orr v0.4s, #255
2691 ; CHECK-SD-NEXT: ret
2692 ;
2693 ; CHECK-GI-LABEL: orr64imm4s_lsl0:
2694 ; CHECK-GI: // %bb.0:
2695 ; CHECK-GI-NEXT: adrp x8, .LCPI168_0
2696 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI168_0]
2697 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2698 ; CHECK-GI-NEXT: ret
2699 %tmp1 = or <2 x i64> %a, < i64 1095216660735, i64 1095216660735>
2700 ret <2 x i64> %tmp1
2701 }
2703 define <2 x i64> @orr64imm4s_lsl8(<2 x i64> %a) {
2704 ; CHECK-SD-LABEL: orr64imm4s_lsl8:
2705 ; CHECK-SD: // %bb.0:
2706 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #8
2707 ; CHECK-SD-NEXT: ret
2708 ;
2709 ; CHECK-GI-LABEL: orr64imm4s_lsl8:
2710 ; CHECK-GI: // %bb.0:
2711 ; CHECK-GI-NEXT: adrp x8, .LCPI169_0
2712 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI169_0]
2713 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2714 ; CHECK-GI-NEXT: ret
2715 %tmp1 = or <2 x i64> %a, < i64 280375465148160, i64 280375465148160>
2716 ret <2 x i64> %tmp1
2717 }
2719 define <2 x i64> @orr64imm4s_lsl16(<2 x i64> %a) {
2720 ; CHECK-SD-LABEL: orr64imm4s_lsl16:
2721 ; CHECK-SD: // %bb.0:
2722 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #16
2723 ; CHECK-SD-NEXT: ret
2724 ;
2725 ; CHECK-GI-LABEL: orr64imm4s_lsl16:
2726 ; CHECK-GI: // %bb.0:
2727 ; CHECK-GI-NEXT: adrp x8, .LCPI170_0
2728 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI170_0]
2729 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2730 ; CHECK-GI-NEXT: ret
2731 %tmp1 = or <2 x i64> %a, < i64 71776119077928960, i64 71776119077928960>
2732 ret <2 x i64> %tmp1
2733 }
2735 define <2 x i64> @orr64imm4s_lsl24(<2 x i64> %a) {
2736 ; CHECK-SD-LABEL: orr64imm4s_lsl24:
2737 ; CHECK-SD: // %bb.0:
2738 ; CHECK-SD-NEXT: orr v0.4s, #255, lsl #24
2739 ; CHECK-SD-NEXT: ret
2740 ;
2741 ; CHECK-GI-LABEL: orr64imm4s_lsl24:
2742 ; CHECK-GI: // %bb.0:
2743 ; CHECK-GI-NEXT: adrp x8, .LCPI171_0
2744 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI171_0]
2745 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2746 ; CHECK-GI-NEXT: ret
2747 %tmp1 = or <2 x i64> %a, < i64 -72057589759737856, i64 -72057589759737856>
2748 ret <2 x i64> %tmp1
2749 }
2751 define <8 x i8> @orr8imm4h_lsl0(<8 x i8> %a) {
2752 ; CHECK-SD-LABEL: orr8imm4h_lsl0:
2753 ; CHECK-SD: // %bb.0:
2754 ; CHECK-SD-NEXT: orr v0.4h, #255
2755 ; CHECK-SD-NEXT: ret
2756 ;
2757 ; CHECK-GI-LABEL: orr8imm4h_lsl0:
2758 ; CHECK-GI: // %bb.0:
2759 ; CHECK-GI-NEXT: adrp x8, .LCPI172_0
2760 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI172_0]
2761 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2762 ; CHECK-GI-NEXT: ret
2763 %tmp1 = or <8 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
2764 ret <8 x i8> %tmp1
2765 }
2767 define <8 x i8> @orr8imm4h_lsl8(<8 x i8> %a) {
2768 ; CHECK-SD-LABEL: orr8imm4h_lsl8:
2769 ; CHECK-SD: // %bb.0:
2770 ; CHECK-SD-NEXT: orr v0.4h, #255, lsl #8
2771 ; CHECK-SD-NEXT: ret
2772 ;
2773 ; CHECK-GI-LABEL: orr8imm4h_lsl8:
2774 ; CHECK-GI: // %bb.0:
2775 ; CHECK-GI-NEXT: adrp x8, .LCPI173_0
2776 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI173_0]
2777 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2778 ; CHECK-GI-NEXT: ret
2779 %tmp1 = or <8 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
2780 ret <8 x i8> %tmp1
2781 }
2783 define <2 x i32> @orr16imm4h_lsl0(<2 x i32> %a) {
2784 ; CHECK-SD-LABEL: orr16imm4h_lsl0:
2785 ; CHECK-SD: // %bb.0:
2786 ; CHECK-SD-NEXT: orr v0.4h, #255
2787 ; CHECK-SD-NEXT: ret
2788 ;
2789 ; CHECK-GI-LABEL: orr16imm4h_lsl0:
2790 ; CHECK-GI: // %bb.0:
2791 ; CHECK-GI-NEXT: adrp x8, .LCPI174_0
2792 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI174_0]
2793 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2794 ; CHECK-GI-NEXT: ret
2795 %tmp1 = or <2 x i32> %a, < i32 16711935, i32 16711935>
2796 ret <2 x i32> %tmp1
2797 }
2799 define <2 x i32> @orr16imm4h_lsl8(<2 x i32> %a) {
2800 ; CHECK-SD-LABEL: orr16imm4h_lsl8:
2801 ; CHECK-SD: // %bb.0:
2802 ; CHECK-SD-NEXT: orr v0.4h, #255, lsl #8
2803 ; CHECK-SD-NEXT: ret
2804 ;
2805 ; CHECK-GI-LABEL: orr16imm4h_lsl8:
2806 ; CHECK-GI: // %bb.0:
2807 ; CHECK-GI-NEXT: adrp x8, .LCPI175_0
2808 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI175_0]
2809 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
2810 ; CHECK-GI-NEXT: ret
2811 %tmp1 = or <2 x i32> %a, < i32 4278255360, i32 4278255360>
2812 ret <2 x i32> %tmp1
2813 }
2815 define <1 x i64> @orr64imm4h_lsl0(<1 x i64> %a) {
2816 ; CHECK-SD-LABEL: orr64imm4h_lsl0:
2817 ; CHECK-SD: // %bb.0:
2818 ; CHECK-SD-NEXT: orr v0.4h, #255
2819 ; CHECK-SD-NEXT: ret
2820 ;
2821 ; CHECK-GI-LABEL: orr64imm4h_lsl0:
2822 ; CHECK-GI: // %bb.0:
2823 ; CHECK-GI-NEXT: fmov x8, d0
2824 ; CHECK-GI-NEXT: orr x8, x8, #0xff00ff00ff00ff
2825 ; CHECK-GI-NEXT: fmov d0, x8
2826 ; CHECK-GI-NEXT: ret
2827 %tmp1 = or <1 x i64> %a, < i64 71777214294589695>
2828 ret <1 x i64> %tmp1
2829 }
2831 define <1 x i64> @orr64imm4h_lsl8(<1 x i64> %a) {
2832 ; CHECK-SD-LABEL: orr64imm4h_lsl8:
2833 ; CHECK-SD: // %bb.0:
2834 ; CHECK-SD-NEXT: orr v0.4h, #255, lsl #8
2835 ; CHECK-SD-NEXT: ret
2836 ;
2837 ; CHECK-GI-LABEL: orr64imm4h_lsl8:
2838 ; CHECK-GI: // %bb.0:
2839 ; CHECK-GI-NEXT: fmov x8, d0
2840 ; CHECK-GI-NEXT: orr x8, x8, #0xff00ff00ff00ff00
2841 ; CHECK-GI-NEXT: fmov d0, x8
2842 ; CHECK-GI-NEXT: ret
2843 %tmp1 = or <1 x i64> %a, < i64 -71777214294589696>
2844 ret <1 x i64> %tmp1
2845 }
2847 define <16 x i8> @orr8imm8h_lsl0(<16 x i8> %a) {
2848 ; CHECK-SD-LABEL: orr8imm8h_lsl0:
2849 ; CHECK-SD: // %bb.0:
2850 ; CHECK-SD-NEXT: orr v0.8h, #255
2851 ; CHECK-SD-NEXT: ret
2852 ;
2853 ; CHECK-GI-LABEL: orr8imm8h_lsl0:
2854 ; CHECK-GI: // %bb.0:
2855 ; CHECK-GI-NEXT: adrp x8, .LCPI178_0
2856 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI178_0]
2857 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2858 ; CHECK-GI-NEXT: ret
2859 %tmp1 = or <16 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
2860 ret <16 x i8> %tmp1
2861 }
2863 define <16 x i8> @orr8imm8h_lsl8(<16 x i8> %a) {
2864 ; CHECK-SD-LABEL: orr8imm8h_lsl8:
2865 ; CHECK-SD: // %bb.0:
2866 ; CHECK-SD-NEXT: orr v0.8h, #255, lsl #8
2867 ; CHECK-SD-NEXT: ret
2868 ;
2869 ; CHECK-GI-LABEL: orr8imm8h_lsl8:
2870 ; CHECK-GI: // %bb.0:
2871 ; CHECK-GI-NEXT: adrp x8, .LCPI179_0
2872 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI179_0]
2873 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2874 ; CHECK-GI-NEXT: ret
2875 %tmp1 = or <16 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
2876 ret <16 x i8> %tmp1
2877 }
2879 define <4 x i32> @orr16imm8h_lsl0(<4 x i32> %a) {
2880 ; CHECK-SD-LABEL: orr16imm8h_lsl0:
2881 ; CHECK-SD: // %bb.0:
2882 ; CHECK-SD-NEXT: orr v0.8h, #255
2883 ; CHECK-SD-NEXT: ret
2884 ;
2885 ; CHECK-GI-LABEL: orr16imm8h_lsl0:
2886 ; CHECK-GI: // %bb.0:
2887 ; CHECK-GI-NEXT: adrp x8, .LCPI180_0
2888 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI180_0]
2889 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2890 ; CHECK-GI-NEXT: ret
2891 %tmp1 = or <4 x i32> %a, < i32 16711935, i32 16711935, i32 16711935, i32 16711935>
2892 ret <4 x i32> %tmp1
2893 }
2895 define <4 x i32> @orr16imm8h_lsl8(<4 x i32> %a) {
2896 ; CHECK-SD-LABEL: orr16imm8h_lsl8:
2897 ; CHECK-SD: // %bb.0:
2898 ; CHECK-SD-NEXT: orr v0.8h, #255, lsl #8
2899 ; CHECK-SD-NEXT: ret
2900 ;
2901 ; CHECK-GI-LABEL: orr16imm8h_lsl8:
2902 ; CHECK-GI: // %bb.0:
2903 ; CHECK-GI-NEXT: adrp x8, .LCPI181_0
2904 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI181_0]
2905 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2906 ; CHECK-GI-NEXT: ret
2907 %tmp1 = or <4 x i32> %a, < i32 4278255360, i32 4278255360, i32 4278255360, i32 4278255360>
2908 ret <4 x i32> %tmp1
2909 }
2911 define <2 x i64> @orr64imm8h_lsl0(<2 x i64> %a) {
2912 ; CHECK-SD-LABEL: orr64imm8h_lsl0:
2913 ; CHECK-SD: // %bb.0:
2914 ; CHECK-SD-NEXT: orr v0.8h, #255
2915 ; CHECK-SD-NEXT: ret
2916 ;
2917 ; CHECK-GI-LABEL: orr64imm8h_lsl0:
2918 ; CHECK-GI: // %bb.0:
2919 ; CHECK-GI-NEXT: adrp x8, .LCPI182_0
2920 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI182_0]
2921 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2922 ; CHECK-GI-NEXT: ret
2923 %tmp1 = or <2 x i64> %a, < i64 71777214294589695, i64 71777214294589695>
2924 ret <2 x i64> %tmp1
2925 }
2927 define <2 x i64> @orr64imm8h_lsl8(<2 x i64> %a) {
2928 ; CHECK-SD-LABEL: orr64imm8h_lsl8:
2929 ; CHECK-SD: // %bb.0:
2930 ; CHECK-SD-NEXT: orr v0.8h, #255, lsl #8
2931 ; CHECK-SD-NEXT: ret
2932 ;
2933 ; CHECK-GI-LABEL: orr64imm8h_lsl8:
2934 ; CHECK-GI: // %bb.0:
2935 ; CHECK-GI-NEXT: adrp x8, .LCPI183_0
2936 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI183_0]
2937 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
2938 ; CHECK-GI-NEXT: ret
2939 %tmp1 = or <2 x i64> %a, < i64 -71777214294589696, i64 -71777214294589696>
2940 ret <2 x i64> %tmp1
2941 }