| blob | a0008e884e27fabc32632eaf6540f56ff0d696f6 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-PWR9,CHECK-PWR9-LE
3 ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-PWR9,CHECK-PWR9-BE
4 ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-PWR78,CHECK-PWR8 -implicit-check-not vabsdu
5 ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs | FileCheck %s -check-prefixes=CHECK,CHECK-PWR78,CHECK-PWR7 -implicit-check-not vmaxsd
7 define <4 x i32> @simple_absv_32(<4 x i32> %a) local_unnamed_addr {
8 ; CHECK-PWR9-LABEL: simple_absv_32:
9 ; CHECK-PWR9: # %bb.0: # %entry
10 ; CHECK-PWR9-NEXT: vnegw v3, v2
11 ; CHECK-PWR9-NEXT: vmaxsw v2, v2, v3
12 ; CHECK-PWR9-NEXT: blr
13 ;
14 ; CHECK-PWR78-LABEL: simple_absv_32:
15 ; CHECK-PWR78: # %bb.0: # %entry
16 ; CHECK-PWR78-NEXT: xxlxor v3, v3, v3
17 ; CHECK-PWR78-NEXT: vsubuwm v3, v3, v2
18 ; CHECK-PWR78-NEXT: vmaxsw v2, v2, v3
19 ; CHECK-PWR78-NEXT: blr
20 entry:
21 %sub.i = sub <4 x i32> zeroinitializer, %a
22 %0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %a, <4 x i32> %sub.i)
23 ret <4 x i32> %0
24 }
26 define <4 x i32> @simple_absv_32_swap(<4 x i32> %a) local_unnamed_addr {
27 ; CHECK-PWR9-LABEL: simple_absv_32_swap:
28 ; CHECK-PWR9: # %bb.0: # %entry
29 ; CHECK-PWR9-NEXT: vnegw v3, v2
30 ; CHECK-PWR9-NEXT: vmaxsw v2, v2, v3
31 ; CHECK-PWR9-NEXT: blr
32 ;
33 ; CHECK-PWR78-LABEL: simple_absv_32_swap:
34 ; CHECK-PWR78: # %bb.0: # %entry
35 ; CHECK-PWR78-NEXT: xxlxor v3, v3, v3
36 ; CHECK-PWR78-NEXT: vsubuwm v3, v3, v2
37 ; CHECK-PWR78-NEXT: vmaxsw v2, v3, v2
38 ; CHECK-PWR78-NEXT: blr
39 entry:
40 %sub.i = sub <4 x i32> zeroinitializer, %a
41 %0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %sub.i, <4 x i32> %a)
42 ret <4 x i32> %0
43 }
45 define <8 x i16> @simple_absv_16(<8 x i16> %a) local_unnamed_addr {
46 ; CHECK-LABEL: simple_absv_16:
47 ; CHECK: # %bb.0: # %entry
48 ; CHECK-NEXT: xxlxor v3, v3, v3
49 ; CHECK-NEXT: vsubuhm v3, v3, v2
50 ; CHECK-NEXT: vmaxsh v2, v2, v3
51 ; CHECK-NEXT: blr
52 entry:
53 %sub.i = sub <8 x i16> zeroinitializer, %a
54 %0 = tail call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %a, <8 x i16> %sub.i)
55 ret <8 x i16> %0
56 }
58 define <16 x i8> @simple_absv_8(<16 x i8> %a) local_unnamed_addr {
59 ; CHECK-LABEL: simple_absv_8:
60 ; CHECK: # %bb.0: # %entry
61 ; CHECK-NEXT: xxlxor v3, v3, v3
62 ; CHECK-NEXT: vsububm v3, v3, v2
63 ; CHECK-NEXT: vmaxsb v2, v2, v3
64 ; CHECK-NEXT: blr
65 entry:
66 %sub.i = sub <16 x i8> zeroinitializer, %a
67 %0 = tail call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %a, <16 x i8> %sub.i)
68 ret <16 x i8> %0
69 }
71 ; v2i64 vmax isn't avaiable on pwr7
72 define <2 x i64> @sub_absv_64(<2 x i64> %a, <2 x i64> %b) local_unnamed_addr {
73 ; CHECK-PWR9-LABEL: sub_absv_64:
74 ; CHECK-PWR9: # %bb.0: # %entry
75 ; CHECK-PWR9-NEXT: vsubudm v2, v2, v3
76 ; CHECK-PWR9-NEXT: vnegd v3, v2
77 ; CHECK-PWR9-NEXT: vmaxsd v2, v2, v3
78 ; CHECK-PWR9-NEXT: blr
79 ;
80 ; CHECK-PWR8-LABEL: sub_absv_64:
81 ; CHECK-PWR8: # %bb.0: # %entry
82 ; CHECK-PWR8-NEXT: vsubudm v2, v2, v3
83 ; CHECK-PWR8-NEXT: xxlxor v3, v3, v3
84 ; CHECK-PWR8-NEXT: vsubudm v3, v3, v2
85 ; CHECK-PWR8-NEXT: vmaxsd v2, v2, v3
86 ; CHECK-PWR8-NEXT: blr
87 ;
88 ; CHECK-PWR7-LABEL: sub_absv_64:
89 ; CHECK-PWR7: # %bb.0: # %entry
90 ; CHECK-PWR7-NEXT: addi r3, r1, -48
91 ; CHECK-PWR7-NEXT: addi r4, r1, -32
92 ; CHECK-PWR7-NEXT: stxvd2x v2, 0, r3
93 ; CHECK-PWR7-NEXT: stxvd2x v3, 0, r4
94 ; CHECK-PWR7-NEXT: ld r3, -40(r1)
95 ; CHECK-PWR7-NEXT: ld r4, -24(r1)
96 ; CHECK-PWR7-NEXT: ld r5, -48(r1)
97 ; CHECK-PWR7-NEXT: ld r6, -32(r1)
98 ; CHECK-PWR7-NEXT: sub r3, r3, r4
99 ; CHECK-PWR7-NEXT: sub r4, r5, r6
100 ; CHECK-PWR7-NEXT: sradi r5, r3, 63
101 ; CHECK-PWR7-NEXT: sradi r6, r4, 63
102 ; CHECK-PWR7-NEXT: xor r3, r3, r5
103 ; CHECK-PWR7-NEXT: xor r4, r4, r6
104 ; CHECK-PWR7-NEXT: sub r3, r3, r5
105 ; CHECK-PWR7-NEXT: sub r4, r4, r6
106 ; CHECK-PWR7-NEXT: std r3, -8(r1)
107 ; CHECK-PWR7-NEXT: addi r3, r1, -16
108 ; CHECK-PWR7-NEXT: std r4, -16(r1)
109 ; CHECK-PWR7-NEXT: lxvd2x v2, 0, r3
110 ; CHECK-PWR7-NEXT: blr
111 entry:
112 %0 = sub nsw <2 x i64> %a, %b
113 %1 = icmp sgt <2 x i64> %0, <i64 -1, i64 -1>
114 %2 = sub <2 x i64> zeroinitializer, %0
115 %3 = select <2 x i1> %1, <2 x i64> %0, <2 x i64> %2
116 ret <2 x i64> %3
117 }
119 ; The select pattern can only be detected for v4i32.
120 define <4 x i32> @sub_absv_32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr {
121 ; CHECK-PWR9-LABEL: sub_absv_32:
122 ; CHECK-PWR9: # %bb.0: # %entry
123 ; CHECK-PWR9-NEXT: xvnegsp v3, v3
124 ; CHECK-PWR9-NEXT: xvnegsp v2, v2
125 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
126 ; CHECK-PWR9-NEXT: blr
127 ;
128 ; CHECK-PWR8-LABEL: sub_absv_32:
129 ; CHECK-PWR8: # %bb.0: # %entry
130 ; CHECK-PWR8-NEXT: vsubuwm v2, v2, v3
131 ; CHECK-PWR8-NEXT: xxlxor v3, v3, v3
132 ; CHECK-PWR8-NEXT: vsubuwm v3, v3, v2
133 ; CHECK-PWR8-NEXT: vmaxsw v2, v2, v3
134 ; CHECK-PWR8-NEXT: blr
135 ;
136 ; CHECK-PWR7-LABEL: sub_absv_32:
137 ; CHECK-PWR7: # %bb.0: # %entry
138 ; CHECK-PWR7-NEXT: xxlxor v4, v4, v4
139 ; CHECK-PWR7-NEXT: vsubuwm v2, v2, v3
140 ; CHECK-PWR7-NEXT: vsubuwm v3, v4, v2
141 ; CHECK-PWR7-NEXT: vmaxsw v2, v2, v3
142 ; CHECK-PWR7-NEXT: blr
143 entry:
144 %0 = sub nsw <4 x i32> %a, %b
145 %1 = icmp sgt <4 x i32> %0, <i32 -1, i32 -1, i32 -1, i32 -1>
146 %2 = sub <4 x i32> zeroinitializer, %0
147 %3 = select <4 x i1> %1, <4 x i32> %0, <4 x i32> %2
148 ret <4 x i32> %3
149 }
151 define <8 x i16> @sub_absv_16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr {
152 ; CHECK-PWR9-LABEL: sub_absv_16:
153 ; CHECK-PWR9: # %bb.0: # %entry
154 ; CHECK-PWR9-NEXT: vsubuhm v2, v2, v3
155 ; CHECK-PWR9-NEXT: xxlxor v3, v3, v3
156 ; CHECK-PWR9-NEXT: vsubuhm v3, v3, v2
157 ; CHECK-PWR9-NEXT: vmaxsh v2, v2, v3
158 ; CHECK-PWR9-NEXT: blr
159 ;
160 ; CHECK-PWR8-LABEL: sub_absv_16:
161 ; CHECK-PWR8: # %bb.0: # %entry
162 ; CHECK-PWR8-NEXT: vsubuhm v2, v2, v3
163 ; CHECK-PWR8-NEXT: xxlxor v3, v3, v3
164 ; CHECK-PWR8-NEXT: vsubuhm v3, v3, v2
165 ; CHECK-PWR8-NEXT: vmaxsh v2, v2, v3
166 ; CHECK-PWR8-NEXT: blr
167 ;
168 ; CHECK-PWR7-LABEL: sub_absv_16:
169 ; CHECK-PWR7: # %bb.0: # %entry
170 ; CHECK-PWR7-NEXT: xxlxor v4, v4, v4
171 ; CHECK-PWR7-NEXT: vsubuhm v2, v2, v3
172 ; CHECK-PWR7-NEXT: vsubuhm v3, v4, v2
173 ; CHECK-PWR7-NEXT: vmaxsh v2, v2, v3
174 ; CHECK-PWR7-NEXT: blr
175 entry:
176 %0 = sub nsw <8 x i16> %a, %b
177 %1 = icmp sgt <8 x i16> %0, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
178 %2 = sub <8 x i16> zeroinitializer, %0
179 %3 = select <8 x i1> %1, <8 x i16> %0, <8 x i16> %2
180 ret <8 x i16> %3
181 }
183 define <16 x i8> @sub_absv_8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr {
184 ; CHECK-PWR9-LABEL: sub_absv_8:
185 ; CHECK-PWR9: # %bb.0: # %entry
186 ; CHECK-PWR9-NEXT: vsububm v2, v2, v3
187 ; CHECK-PWR9-NEXT: xxlxor v3, v3, v3
188 ; CHECK-PWR9-NEXT: vsububm v3, v3, v2
189 ; CHECK-PWR9-NEXT: vmaxsb v2, v2, v3
190 ; CHECK-PWR9-NEXT: blr
191 ;
192 ; CHECK-PWR8-LABEL: sub_absv_8:
193 ; CHECK-PWR8: # %bb.0: # %entry
194 ; CHECK-PWR8-NEXT: vsububm v2, v2, v3
195 ; CHECK-PWR8-NEXT: xxlxor v3, v3, v3
196 ; CHECK-PWR8-NEXT: vsububm v3, v3, v2
197 ; CHECK-PWR8-NEXT: vmaxsb v2, v2, v3
198 ; CHECK-PWR8-NEXT: blr
199 ;
200 ; CHECK-PWR7-LABEL: sub_absv_8:
201 ; CHECK-PWR7: # %bb.0: # %entry
202 ; CHECK-PWR7-NEXT: xxlxor v4, v4, v4
203 ; CHECK-PWR7-NEXT: vsububm v2, v2, v3
204 ; CHECK-PWR7-NEXT: vsububm v3, v4, v2
205 ; CHECK-PWR7-NEXT: vmaxsb v2, v2, v3
206 ; CHECK-PWR7-NEXT: blr
207 entry:
208 %0 = sub nsw <16 x i8> %a, %b
209 %1 = icmp sgt <16 x i8> %0, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
210 %2 = sub <16 x i8> zeroinitializer, %0
211 %3 = select <16 x i1> %1, <16 x i8> %0, <16 x i8> %2
212 ret <16 x i8> %3
213 }
215 ; FIXME: This does not produce the ISD::ABS that we are looking for.
216 ; We should fix the missing canonicalization.
217 ; We do manage to find the word version of ABS but not the halfword.
218 ; Threfore, we end up doing more work than is required with a pair of abs for word
219 ; instead of just one for the halfword.
220 define <8 x i16> @sub_absv_16_ext(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr {
221 ; CHECK-PWR9-LABEL: sub_absv_16_ext:
222 ; CHECK-PWR9: # %bb.0: # %entry
223 ; CHECK-PWR9-NEXT: vmrghh v4, v2, v2
224 ; CHECK-PWR9-NEXT: vmrglh v2, v2, v2
225 ; CHECK-PWR9-NEXT: vmrghh v5, v3, v3
226 ; CHECK-PWR9-NEXT: vmrglh v3, v3, v3
227 ; CHECK-PWR9-NEXT: vextsh2w v2, v2
228 ; CHECK-PWR9-NEXT: vextsh2w v3, v3
229 ; CHECK-PWR9-NEXT: vextsh2w v4, v4
230 ; CHECK-PWR9-NEXT: vextsh2w v5, v5
231 ; CHECK-PWR9-NEXT: xvnegsp v3, v3
232 ; CHECK-PWR9-NEXT: xvnegsp v2, v2
233 ; CHECK-PWR9-NEXT: xvnegsp v4, v4
234 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
235 ; CHECK-PWR9-NEXT: xvnegsp v3, v5
236 ; CHECK-PWR9-NEXT: vabsduw v3, v4, v3
237 ; CHECK-PWR9-NEXT: vpkuwum v2, v3, v2
238 ; CHECK-PWR9-NEXT: blr
239 ;
240 ; CHECK-PWR8-LABEL: sub_absv_16_ext:
241 ; CHECK-PWR8: # %bb.0: # %entry
242 ; CHECK-PWR8-NEXT: vspltisw v4, 8
243 ; CHECK-PWR8-NEXT: vmrglh v5, v2, v2
244 ; CHECK-PWR8-NEXT: vadduwm v4, v4, v4
245 ; CHECK-PWR8-NEXT: vmrghh v2, v2, v2
246 ; CHECK-PWR8-NEXT: vmrglh v0, v3, v3
247 ; CHECK-PWR8-NEXT: vmrghh v3, v3, v3
248 ; CHECK-PWR8-NEXT: vslw v5, v5, v4
249 ; CHECK-PWR8-NEXT: vslw v2, v2, v4
250 ; CHECK-PWR8-NEXT: vslw v0, v0, v4
251 ; CHECK-PWR8-NEXT: vslw v3, v3, v4
252 ; CHECK-PWR8-NEXT: vsraw v5, v5, v4
253 ; CHECK-PWR8-NEXT: vsraw v2, v2, v4
254 ; CHECK-PWR8-NEXT: vsraw v0, v0, v4
255 ; CHECK-PWR8-NEXT: vsraw v3, v3, v4
256 ; CHECK-PWR8-NEXT: xxlxor v4, v4, v4
257 ; CHECK-PWR8-NEXT: vsubuwm v2, v2, v3
258 ; CHECK-PWR8-NEXT: vsubuwm v3, v5, v0
259 ; CHECK-PWR8-NEXT: vsubuwm v5, v4, v3
260 ; CHECK-PWR8-NEXT: vsubuwm v4, v4, v2
261 ; CHECK-PWR8-NEXT: vmaxsw v3, v3, v5
262 ; CHECK-PWR8-NEXT: vmaxsw v2, v2, v4
263 ; CHECK-PWR8-NEXT: vpkuwum v2, v2, v3
264 ; CHECK-PWR8-NEXT: blr
265 ;
266 ; CHECK-PWR7-LABEL: sub_absv_16_ext:
267 ; CHECK-PWR7: # %bb.0: # %entry
268 ; CHECK-PWR7-NEXT: vmrglh v5, v2, v2
269 ; CHECK-PWR7-NEXT: vmrghh v2, v2, v2
270 ; CHECK-PWR7-NEXT: vmrglh v0, v3, v3
271 ; CHECK-PWR7-NEXT: vmrghh v3, v3, v3
272 ; CHECK-PWR7-NEXT: vspltisw v4, 8
273 ; CHECK-PWR7-NEXT: vadduwm v4, v4, v4
274 ; CHECK-PWR7-NEXT: vslw v5, v5, v4
275 ; CHECK-PWR7-NEXT: vslw v2, v2, v4
276 ; CHECK-PWR7-NEXT: vslw v0, v0, v4
277 ; CHECK-PWR7-NEXT: vslw v3, v3, v4
278 ; CHECK-PWR7-NEXT: vsraw v5, v5, v4
279 ; CHECK-PWR7-NEXT: vsraw v2, v2, v4
280 ; CHECK-PWR7-NEXT: vsraw v0, v0, v4
281 ; CHECK-PWR7-NEXT: vsraw v3, v3, v4
282 ; CHECK-PWR7-NEXT: xxlxor v4, v4, v4
283 ; CHECK-PWR7-NEXT: vsubuwm v5, v5, v0
284 ; CHECK-PWR7-NEXT: vsubuwm v2, v2, v3
285 ; CHECK-PWR7-NEXT: vsubuwm v3, v4, v5
286 ; CHECK-PWR7-NEXT: vsubuwm v4, v4, v2
287 ; CHECK-PWR7-NEXT: vmaxsw v3, v5, v3
288 ; CHECK-PWR7-NEXT: vmaxsw v2, v2, v4
289 ; CHECK-PWR7-NEXT: vpkuwum v2, v2, v3
290 ; CHECK-PWR7-NEXT: blr
291 entry:
292 %0 = sext <8 x i16> %a to <8 x i32>
293 %1 = sext <8 x i16> %b to <8 x i32>
294 %2 = sub nsw <8 x i32> %0, %1
295 %3 = icmp sgt <8 x i32> %2, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
296 %4 = sub nsw <8 x i32> zeroinitializer, %2
297 %5 = select <8 x i1> %3, <8 x i32> %2, <8 x i32> %4
298 %6 = trunc <8 x i32> %5 to <8 x i16>
299 ret <8 x i16> %6
300 }
302 ; FIXME: This does not produce ISD::ABS. This does not even vectorize correctly!
303 ; This function should look like sub_absv_32 and sub_absv_16 except that the type is v16i8.
304 ; Function Attrs: norecurse nounwind readnone
305 define <16 x i8> @sub_absv_8_ext(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr {
306 ; CHECK-PWR9-LE-LABEL: sub_absv_8_ext:
307 ; CHECK-PWR9-LE: # %bb.0: # %entry
308 ; CHECK-PWR9-LE-NEXT: li r3, 0
309 ; CHECK-PWR9-LE-NEXT: li r5, 2
310 ; CHECK-PWR9-LE-NEXT: li r4, 1
311 ; CHECK-PWR9-LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
312 ; CHECK-PWR9-LE-NEXT: vextubrx r6, r3, v2
313 ; CHECK-PWR9-LE-NEXT: vextubrx r3, r3, v3
314 ; CHECK-PWR9-LE-NEXT: vextubrx r8, r5, v2
315 ; CHECK-PWR9-LE-NEXT: vextubrx r5, r5, v3
316 ; CHECK-PWR9-LE-NEXT: std r29, -24(r1) # 8-byte Folded Spill
317 ; CHECK-PWR9-LE-NEXT: std r28, -32(r1) # 8-byte Folded Spill
318 ; CHECK-PWR9-LE-NEXT: std r27, -40(r1) # 8-byte Folded Spill
319 ; CHECK-PWR9-LE-NEXT: std r26, -48(r1) # 8-byte Folded Spill
320 ; CHECK-PWR9-LE-NEXT: std r25, -56(r1) # 8-byte Folded Spill
321 ; CHECK-PWR9-LE-NEXT: clrlwi r6, r6, 24
322 ; CHECK-PWR9-LE-NEXT: clrlwi r3, r3, 24
323 ; CHECK-PWR9-LE-NEXT: vextubrx r7, r4, v2
324 ; CHECK-PWR9-LE-NEXT: vextubrx r4, r4, v3
325 ; CHECK-PWR9-LE-NEXT: clrlwi r8, r8, 24
326 ; CHECK-PWR9-LE-NEXT: sub r3, r6, r3
327 ; CHECK-PWR9-LE-NEXT: clrlwi r5, r5, 24
328 ; CHECK-PWR9-LE-NEXT: clrlwi r7, r7, 24
329 ; CHECK-PWR9-LE-NEXT: clrlwi r4, r4, 24
330 ; CHECK-PWR9-LE-NEXT: sub r5, r8, r5
331 ; CHECK-PWR9-LE-NEXT: sub r4, r7, r4
332 ; CHECK-PWR9-LE-NEXT: srawi r6, r3, 31
333 ; CHECK-PWR9-LE-NEXT: srawi r7, r4, 31
334 ; CHECK-PWR9-LE-NEXT: xor r3, r3, r6
335 ; CHECK-PWR9-LE-NEXT: xor r4, r4, r7
336 ; CHECK-PWR9-LE-NEXT: sub r6, r3, r6
337 ; CHECK-PWR9-LE-NEXT: srawi r3, r5, 31
338 ; CHECK-PWR9-LE-NEXT: sub r4, r4, r7
339 ; CHECK-PWR9-LE-NEXT: xor r5, r5, r3
340 ; CHECK-PWR9-LE-NEXT: sub r3, r5, r3
341 ; CHECK-PWR9-LE-NEXT: li r5, 3
342 ; CHECK-PWR9-LE-NEXT: vextubrx r7, r5, v2
343 ; CHECK-PWR9-LE-NEXT: vextubrx r5, r5, v3
344 ; CHECK-PWR9-LE-NEXT: clrlwi r7, r7, 24
345 ; CHECK-PWR9-LE-NEXT: clrlwi r5, r5, 24
346 ; CHECK-PWR9-LE-NEXT: sub r5, r7, r5
347 ; CHECK-PWR9-LE-NEXT: srawi r7, r5, 31
348 ; CHECK-PWR9-LE-NEXT: xor r5, r5, r7
349 ; CHECK-PWR9-LE-NEXT: sub r5, r5, r7
350 ; CHECK-PWR9-LE-NEXT: li r7, 4
351 ; CHECK-PWR9-LE-NEXT: vextubrx r8, r7, v2
352 ; CHECK-PWR9-LE-NEXT: vextubrx r7, r7, v3
353 ; CHECK-PWR9-LE-NEXT: mtvsrd v4, r5
354 ; CHECK-PWR9-LE-NEXT: clrlwi r8, r8, 24
355 ; CHECK-PWR9-LE-NEXT: clrlwi r7, r7, 24
356 ; CHECK-PWR9-LE-NEXT: sub r7, r8, r7
357 ; CHECK-PWR9-LE-NEXT: srawi r8, r7, 31
358 ; CHECK-PWR9-LE-NEXT: xor r7, r7, r8
359 ; CHECK-PWR9-LE-NEXT: sub r7, r7, r8
360 ; CHECK-PWR9-LE-NEXT: li r8, 5
361 ; CHECK-PWR9-LE-NEXT: vextubrx r9, r8, v2
362 ; CHECK-PWR9-LE-NEXT: vextubrx r8, r8, v3
363 ; CHECK-PWR9-LE-NEXT: clrlwi r9, r9, 24
364 ; CHECK-PWR9-LE-NEXT: clrlwi r8, r8, 24
365 ; CHECK-PWR9-LE-NEXT: sub r8, r9, r8
366 ; CHECK-PWR9-LE-NEXT: srawi r9, r8, 31
367 ; CHECK-PWR9-LE-NEXT: xor r8, r8, r9
368 ; CHECK-PWR9-LE-NEXT: sub r8, r8, r9
369 ; CHECK-PWR9-LE-NEXT: li r9, 6
370 ; CHECK-PWR9-LE-NEXT: vextubrx r10, r9, v2
371 ; CHECK-PWR9-LE-NEXT: vextubrx r9, r9, v3
372 ; CHECK-PWR9-LE-NEXT: clrlwi r10, r10, 24
373 ; CHECK-PWR9-LE-NEXT: clrlwi r9, r9, 24
374 ; CHECK-PWR9-LE-NEXT: sub r9, r10, r9
375 ; CHECK-PWR9-LE-NEXT: srawi r10, r9, 31
376 ; CHECK-PWR9-LE-NEXT: xor r9, r9, r10
377 ; CHECK-PWR9-LE-NEXT: sub r9, r9, r10
378 ; CHECK-PWR9-LE-NEXT: li r10, 7
379 ; CHECK-PWR9-LE-NEXT: vextubrx r11, r10, v2
380 ; CHECK-PWR9-LE-NEXT: vextubrx r10, r10, v3
381 ; CHECK-PWR9-LE-NEXT: clrlwi r11, r11, 24
382 ; CHECK-PWR9-LE-NEXT: clrlwi r10, r10, 24
383 ; CHECK-PWR9-LE-NEXT: sub r10, r11, r10
384 ; CHECK-PWR9-LE-NEXT: srawi r11, r10, 31
385 ; CHECK-PWR9-LE-NEXT: xor r10, r10, r11
386 ; CHECK-PWR9-LE-NEXT: sub r10, r10, r11
387 ; CHECK-PWR9-LE-NEXT: li r11, 8
388 ; CHECK-PWR9-LE-NEXT: vextubrx r12, r11, v2
389 ; CHECK-PWR9-LE-NEXT: vextubrx r11, r11, v3
390 ; CHECK-PWR9-LE-NEXT: mtvsrd v5, r10
391 ; CHECK-PWR9-LE-NEXT: clrlwi r12, r12, 24
392 ; CHECK-PWR9-LE-NEXT: clrlwi r11, r11, 24
393 ; CHECK-PWR9-LE-NEXT: sub r11, r12, r11
394 ; CHECK-PWR9-LE-NEXT: srawi r12, r11, 31
395 ; CHECK-PWR9-LE-NEXT: xor r11, r11, r12
396 ; CHECK-PWR9-LE-NEXT: sub r11, r11, r12
397 ; CHECK-PWR9-LE-NEXT: li r12, 9
398 ; CHECK-PWR9-LE-NEXT: vextubrx r0, r12, v2
399 ; CHECK-PWR9-LE-NEXT: vextubrx r12, r12, v3
400 ; CHECK-PWR9-LE-NEXT: clrlwi r0, r0, 24
401 ; CHECK-PWR9-LE-NEXT: clrlwi r12, r12, 24
402 ; CHECK-PWR9-LE-NEXT: sub r12, r0, r12
403 ; CHECK-PWR9-LE-NEXT: srawi r0, r12, 31
404 ; CHECK-PWR9-LE-NEXT: xor r12, r12, r0
405 ; CHECK-PWR9-LE-NEXT: sub r12, r12, r0
406 ; CHECK-PWR9-LE-NEXT: li r0, 10
407 ; CHECK-PWR9-LE-NEXT: vextubrx r30, r0, v2
408 ; CHECK-PWR9-LE-NEXT: vextubrx r0, r0, v3
409 ; CHECK-PWR9-LE-NEXT: clrlwi r30, r30, 24
410 ; CHECK-PWR9-LE-NEXT: clrlwi r0, r0, 24
411 ; CHECK-PWR9-LE-NEXT: sub r0, r30, r0
412 ; CHECK-PWR9-LE-NEXT: srawi r30, r0, 31
413 ; CHECK-PWR9-LE-NEXT: xor r0, r0, r30
414 ; CHECK-PWR9-LE-NEXT: sub r0, r0, r30
415 ; CHECK-PWR9-LE-NEXT: li r30, 11
416 ; CHECK-PWR9-LE-NEXT: vextubrx r29, r30, v2
417 ; CHECK-PWR9-LE-NEXT: vextubrx r30, r30, v3
418 ; CHECK-PWR9-LE-NEXT: clrlwi r29, r29, 24
419 ; CHECK-PWR9-LE-NEXT: clrlwi r30, r30, 24
420 ; CHECK-PWR9-LE-NEXT: sub r30, r29, r30
421 ; CHECK-PWR9-LE-NEXT: srawi r29, r30, 31
422 ; CHECK-PWR9-LE-NEXT: xor r30, r30, r29
423 ; CHECK-PWR9-LE-NEXT: sub r30, r30, r29
424 ; CHECK-PWR9-LE-NEXT: li r29, 12
425 ; CHECK-PWR9-LE-NEXT: vextubrx r28, r29, v2
426 ; CHECK-PWR9-LE-NEXT: vextubrx r29, r29, v3
427 ; CHECK-PWR9-LE-NEXT: clrlwi r28, r28, 24
428 ; CHECK-PWR9-LE-NEXT: clrlwi r29, r29, 24
429 ; CHECK-PWR9-LE-NEXT: sub r29, r28, r29
430 ; CHECK-PWR9-LE-NEXT: srawi r28, r29, 31
431 ; CHECK-PWR9-LE-NEXT: xor r29, r29, r28
432 ; CHECK-PWR9-LE-NEXT: sub r29, r29, r28
433 ; CHECK-PWR9-LE-NEXT: li r28, 13
434 ; CHECK-PWR9-LE-NEXT: vextubrx r27, r28, v2
435 ; CHECK-PWR9-LE-NEXT: vextubrx r28, r28, v3
436 ; CHECK-PWR9-LE-NEXT: clrlwi r27, r27, 24
437 ; CHECK-PWR9-LE-NEXT: clrlwi r28, r28, 24
438 ; CHECK-PWR9-LE-NEXT: sub r28, r27, r28
439 ; CHECK-PWR9-LE-NEXT: srawi r27, r28, 31
440 ; CHECK-PWR9-LE-NEXT: xor r28, r28, r27
441 ; CHECK-PWR9-LE-NEXT: sub r28, r28, r27
442 ; CHECK-PWR9-LE-NEXT: li r27, 14
443 ; CHECK-PWR9-LE-NEXT: vextubrx r26, r27, v2
444 ; CHECK-PWR9-LE-NEXT: vextubrx r27, r27, v3
445 ; CHECK-PWR9-LE-NEXT: clrlwi r26, r26, 24
446 ; CHECK-PWR9-LE-NEXT: clrlwi r27, r27, 24
447 ; CHECK-PWR9-LE-NEXT: sub r27, r26, r27
448 ; CHECK-PWR9-LE-NEXT: srawi r26, r27, 31
449 ; CHECK-PWR9-LE-NEXT: xor r27, r27, r26
450 ; CHECK-PWR9-LE-NEXT: sub r27, r27, r26
451 ; CHECK-PWR9-LE-NEXT: li r26, 15
452 ; CHECK-PWR9-LE-NEXT: vextubrx r25, r26, v2
453 ; CHECK-PWR9-LE-NEXT: vextubrx r26, r26, v3
454 ; CHECK-PWR9-LE-NEXT: mtvsrd v2, r6
455 ; CHECK-PWR9-LE-NEXT: mtvsrd v3, r4
456 ; CHECK-PWR9-LE-NEXT: vmrghb v2, v3, v2
457 ; CHECK-PWR9-LE-NEXT: mtvsrd v3, r3
458 ; CHECK-PWR9-LE-NEXT: clrlwi r25, r25, 24
459 ; CHECK-PWR9-LE-NEXT: clrlwi r26, r26, 24
460 ; CHECK-PWR9-LE-NEXT: vmrghb v3, v4, v3
461 ; CHECK-PWR9-LE-NEXT: mtvsrd v4, r8
462 ; CHECK-PWR9-LE-NEXT: sub r26, r25, r26
463 ; CHECK-PWR9-LE-NEXT: vmrglh v2, v3, v2
464 ; CHECK-PWR9-LE-NEXT: mtvsrd v3, r7
465 ; CHECK-PWR9-LE-NEXT: srawi r25, r26, 31
466 ; CHECK-PWR9-LE-NEXT: vmrghb v3, v4, v3
467 ; CHECK-PWR9-LE-NEXT: mtvsrd v4, r9
468 ; CHECK-PWR9-LE-NEXT: xor r26, r26, r25
469 ; CHECK-PWR9-LE-NEXT: vmrghb v4, v5, v4
470 ; CHECK-PWR9-LE-NEXT: sub r26, r26, r25
471 ; CHECK-PWR9-LE-NEXT: ld r25, -56(r1) # 8-byte Folded Reload
472 ; CHECK-PWR9-LE-NEXT: mtvsrd v5, r26
473 ; CHECK-PWR9-LE-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
474 ; CHECK-PWR9-LE-NEXT: vmrglh v3, v4, v3
475 ; CHECK-PWR9-LE-NEXT: mtvsrd v4, r30
476 ; CHECK-PWR9-LE-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
477 ; CHECK-PWR9-LE-NEXT: xxmrglw vs0, v3, v2
478 ; CHECK-PWR9-LE-NEXT: mtvsrd v2, r11
479 ; CHECK-PWR9-LE-NEXT: mtvsrd v3, r12
480 ; CHECK-PWR9-LE-NEXT: vmrghb v2, v3, v2
481 ; CHECK-PWR9-LE-NEXT: mtvsrd v3, r0
482 ; CHECK-PWR9-LE-NEXT: vmrghb v3, v4, v3
483 ; CHECK-PWR9-LE-NEXT: mtvsrd v4, r28
484 ; CHECK-PWR9-LE-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
485 ; CHECK-PWR9-LE-NEXT: vmrglh v2, v3, v2
486 ; CHECK-PWR9-LE-NEXT: mtvsrd v3, r29
487 ; CHECK-PWR9-LE-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
488 ; CHECK-PWR9-LE-NEXT: vmrghb v3, v4, v3
489 ; CHECK-PWR9-LE-NEXT: mtvsrd v4, r27
490 ; CHECK-PWR9-LE-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
491 ; CHECK-PWR9-LE-NEXT: vmrghb v4, v5, v4
492 ; CHECK-PWR9-LE-NEXT: vmrglh v3, v4, v3
493 ; CHECK-PWR9-LE-NEXT: xxmrglw vs1, v3, v2
494 ; CHECK-PWR9-LE-NEXT: xxmrgld v2, vs1, vs0
495 ; CHECK-PWR9-LE-NEXT: blr
496 ;
497 ; CHECK-PWR9-BE-LABEL: sub_absv_8_ext:
498 ; CHECK-PWR9-BE: # %bb.0: # %entry
499 ; CHECK-PWR9-BE-NEXT: li r3, 0
500 ; CHECK-PWR9-BE-NEXT: li r4, 1
501 ; CHECK-PWR9-BE-NEXT: li r5, 2
502 ; CHECK-PWR9-BE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
503 ; CHECK-PWR9-BE-NEXT: vextublx r6, r3, v2
504 ; CHECK-PWR9-BE-NEXT: vextublx r3, r3, v3
505 ; CHECK-PWR9-BE-NEXT: vextublx r7, r4, v2
506 ; CHECK-PWR9-BE-NEXT: vextublx r4, r4, v3
507 ; CHECK-PWR9-BE-NEXT: std r29, -24(r1) # 8-byte Folded Spill
508 ; CHECK-PWR9-BE-NEXT: std r28, -32(r1) # 8-byte Folded Spill
509 ; CHECK-PWR9-BE-NEXT: std r27, -40(r1) # 8-byte Folded Spill
510 ; CHECK-PWR9-BE-NEXT: std r26, -48(r1) # 8-byte Folded Spill
511 ; CHECK-PWR9-BE-NEXT: std r25, -56(r1) # 8-byte Folded Spill
512 ; CHECK-PWR9-BE-NEXT: clrlwi r6, r6, 24
513 ; CHECK-PWR9-BE-NEXT: clrlwi r3, r3, 24
514 ; CHECK-PWR9-BE-NEXT: clrlwi r7, r7, 24
515 ; CHECK-PWR9-BE-NEXT: clrlwi r4, r4, 24
516 ; CHECK-PWR9-BE-NEXT: vextublx r8, r5, v2
517 ; CHECK-PWR9-BE-NEXT: vextublx r5, r5, v3
518 ; CHECK-PWR9-BE-NEXT: sub r3, r6, r3
519 ; CHECK-PWR9-BE-NEXT: sub r4, r7, r4
520 ; CHECK-PWR9-BE-NEXT: clrlwi r8, r8, 24
521 ; CHECK-PWR9-BE-NEXT: clrlwi r5, r5, 24
522 ; CHECK-PWR9-BE-NEXT: sub r5, r8, r5
523 ; CHECK-PWR9-BE-NEXT: srawi r6, r3, 31
524 ; CHECK-PWR9-BE-NEXT: srawi r7, r4, 31
525 ; CHECK-PWR9-BE-NEXT: srawi r8, r5, 31
526 ; CHECK-PWR9-BE-NEXT: xor r3, r3, r6
527 ; CHECK-PWR9-BE-NEXT: xor r4, r4, r7
528 ; CHECK-PWR9-BE-NEXT: xor r5, r5, r8
529 ; CHECK-PWR9-BE-NEXT: sub r3, r3, r6
530 ; CHECK-PWR9-BE-NEXT: li r6, 3
531 ; CHECK-PWR9-BE-NEXT: sub r4, r4, r7
532 ; CHECK-PWR9-BE-NEXT: sub r5, r5, r8
533 ; CHECK-PWR9-BE-NEXT: vextublx r7, r6, v2
534 ; CHECK-PWR9-BE-NEXT: vextublx r6, r6, v3
535 ; CHECK-PWR9-BE-NEXT: clrlwi r7, r7, 24
536 ; CHECK-PWR9-BE-NEXT: clrlwi r6, r6, 24
537 ; CHECK-PWR9-BE-NEXT: sub r6, r7, r6
538 ; CHECK-PWR9-BE-NEXT: srawi r7, r6, 31
539 ; CHECK-PWR9-BE-NEXT: xor r6, r6, r7
540 ; CHECK-PWR9-BE-NEXT: sub r6, r6, r7
541 ; CHECK-PWR9-BE-NEXT: li r7, 4
542 ; CHECK-PWR9-BE-NEXT: vextublx r8, r7, v2
543 ; CHECK-PWR9-BE-NEXT: vextublx r7, r7, v3
544 ; CHECK-PWR9-BE-NEXT: clrlwi r8, r8, 24
545 ; CHECK-PWR9-BE-NEXT: clrlwi r7, r7, 24
546 ; CHECK-PWR9-BE-NEXT: sub r7, r8, r7
547 ; CHECK-PWR9-BE-NEXT: srawi r8, r7, 31
548 ; CHECK-PWR9-BE-NEXT: xor r7, r7, r8
549 ; CHECK-PWR9-BE-NEXT: sub r7, r7, r8
550 ; CHECK-PWR9-BE-NEXT: li r8, 5
551 ; CHECK-PWR9-BE-NEXT: vextublx r9, r8, v2
552 ; CHECK-PWR9-BE-NEXT: vextublx r8, r8, v3
553 ; CHECK-PWR9-BE-NEXT: clrlwi r9, r9, 24
554 ; CHECK-PWR9-BE-NEXT: clrlwi r8, r8, 24
555 ; CHECK-PWR9-BE-NEXT: sub r8, r9, r8
556 ; CHECK-PWR9-BE-NEXT: srawi r9, r8, 31
557 ; CHECK-PWR9-BE-NEXT: xor r8, r8, r9
558 ; CHECK-PWR9-BE-NEXT: sub r8, r8, r9
559 ; CHECK-PWR9-BE-NEXT: li r9, 6
560 ; CHECK-PWR9-BE-NEXT: vextublx r10, r9, v2
561 ; CHECK-PWR9-BE-NEXT: vextublx r9, r9, v3
562 ; CHECK-PWR9-BE-NEXT: clrlwi r10, r10, 24
563 ; CHECK-PWR9-BE-NEXT: clrlwi r9, r9, 24
564 ; CHECK-PWR9-BE-NEXT: sub r9, r10, r9
565 ; CHECK-PWR9-BE-NEXT: srawi r10, r9, 31
566 ; CHECK-PWR9-BE-NEXT: xor r9, r9, r10
567 ; CHECK-PWR9-BE-NEXT: sub r9, r9, r10
568 ; CHECK-PWR9-BE-NEXT: li r10, 7
569 ; CHECK-PWR9-BE-NEXT: vextublx r11, r10, v2
570 ; CHECK-PWR9-BE-NEXT: vextublx r10, r10, v3
571 ; CHECK-PWR9-BE-NEXT: mtfprwz f2, r9
572 ; CHECK-PWR9-BE-NEXT: clrlwi r11, r11, 24
573 ; CHECK-PWR9-BE-NEXT: clrlwi r10, r10, 24
574 ; CHECK-PWR9-BE-NEXT: sub r10, r11, r10
575 ; CHECK-PWR9-BE-NEXT: srawi r11, r10, 31
576 ; CHECK-PWR9-BE-NEXT: xor r10, r10, r11
577 ; CHECK-PWR9-BE-NEXT: sub r10, r10, r11
578 ; CHECK-PWR9-BE-NEXT: li r11, 8
579 ; CHECK-PWR9-BE-NEXT: vextublx r12, r11, v2
580 ; CHECK-PWR9-BE-NEXT: vextublx r11, r11, v3
581 ; CHECK-PWR9-BE-NEXT: clrlwi r12, r12, 24
582 ; CHECK-PWR9-BE-NEXT: clrlwi r11, r11, 24
583 ; CHECK-PWR9-BE-NEXT: sub r11, r12, r11
584 ; CHECK-PWR9-BE-NEXT: srawi r12, r11, 31
585 ; CHECK-PWR9-BE-NEXT: xor r11, r11, r12
586 ; CHECK-PWR9-BE-NEXT: sub r11, r11, r12
587 ; CHECK-PWR9-BE-NEXT: li r12, 9
588 ; CHECK-PWR9-BE-NEXT: vextublx r0, r12, v2
589 ; CHECK-PWR9-BE-NEXT: vextublx r12, r12, v3
590 ; CHECK-PWR9-BE-NEXT: clrlwi r0, r0, 24
591 ; CHECK-PWR9-BE-NEXT: clrlwi r12, r12, 24
592 ; CHECK-PWR9-BE-NEXT: sub r12, r0, r12
593 ; CHECK-PWR9-BE-NEXT: srawi r0, r12, 31
594 ; CHECK-PWR9-BE-NEXT: xor r12, r12, r0
595 ; CHECK-PWR9-BE-NEXT: sub r12, r12, r0
596 ; CHECK-PWR9-BE-NEXT: li r0, 10
597 ; CHECK-PWR9-BE-NEXT: vextublx r30, r0, v2
598 ; CHECK-PWR9-BE-NEXT: vextublx r0, r0, v3
599 ; CHECK-PWR9-BE-NEXT: mtvsrwz v4, r12
600 ; CHECK-PWR9-BE-NEXT: clrlwi r30, r30, 24
601 ; CHECK-PWR9-BE-NEXT: clrlwi r0, r0, 24
602 ; CHECK-PWR9-BE-NEXT: sub r0, r30, r0
603 ; CHECK-PWR9-BE-NEXT: srawi r30, r0, 31
604 ; CHECK-PWR9-BE-NEXT: xor r0, r0, r30
605 ; CHECK-PWR9-BE-NEXT: sub r0, r0, r30
606 ; CHECK-PWR9-BE-NEXT: li r30, 11
607 ; CHECK-PWR9-BE-NEXT: vextublx r29, r30, v2
608 ; CHECK-PWR9-BE-NEXT: vextublx r30, r30, v3
609 ; CHECK-PWR9-BE-NEXT: clrlwi r29, r29, 24
610 ; CHECK-PWR9-BE-NEXT: clrlwi r30, r30, 24
611 ; CHECK-PWR9-BE-NEXT: sub r30, r29, r30
612 ; CHECK-PWR9-BE-NEXT: srawi r29, r30, 31
613 ; CHECK-PWR9-BE-NEXT: xor r30, r30, r29
614 ; CHECK-PWR9-BE-NEXT: sub r30, r30, r29
615 ; CHECK-PWR9-BE-NEXT: li r29, 12
616 ; CHECK-PWR9-BE-NEXT: vextublx r28, r29, v2
617 ; CHECK-PWR9-BE-NEXT: vextublx r29, r29, v3
618 ; CHECK-PWR9-BE-NEXT: clrlwi r28, r28, 24
619 ; CHECK-PWR9-BE-NEXT: clrlwi r29, r29, 24
620 ; CHECK-PWR9-BE-NEXT: sub r29, r28, r29
621 ; CHECK-PWR9-BE-NEXT: srawi r28, r29, 31
622 ; CHECK-PWR9-BE-NEXT: xor r29, r29, r28
623 ; CHECK-PWR9-BE-NEXT: sub r29, r29, r28
624 ; CHECK-PWR9-BE-NEXT: li r28, 13
625 ; CHECK-PWR9-BE-NEXT: vextublx r27, r28, v2
626 ; CHECK-PWR9-BE-NEXT: vextublx r28, r28, v3
627 ; CHECK-PWR9-BE-NEXT: clrlwi r27, r27, 24
628 ; CHECK-PWR9-BE-NEXT: clrlwi r28, r28, 24
629 ; CHECK-PWR9-BE-NEXT: sub r28, r27, r28
630 ; CHECK-PWR9-BE-NEXT: srawi r27, r28, 31
631 ; CHECK-PWR9-BE-NEXT: xor r28, r28, r27
632 ; CHECK-PWR9-BE-NEXT: sub r28, r28, r27
633 ; CHECK-PWR9-BE-NEXT: li r27, 14
634 ; CHECK-PWR9-BE-NEXT: vextublx r26, r27, v2
635 ; CHECK-PWR9-BE-NEXT: vextublx r27, r27, v3
636 ; CHECK-PWR9-BE-NEXT: clrlwi r26, r26, 24
637 ; CHECK-PWR9-BE-NEXT: clrlwi r27, r27, 24
638 ; CHECK-PWR9-BE-NEXT: sub r27, r26, r27
639 ; CHECK-PWR9-BE-NEXT: srawi r26, r27, 31
640 ; CHECK-PWR9-BE-NEXT: xor r27, r27, r26
641 ; CHECK-PWR9-BE-NEXT: sub r27, r27, r26
642 ; CHECK-PWR9-BE-NEXT: li r26, 15
643 ; CHECK-PWR9-BE-NEXT: vextublx r25, r26, v2
644 ; CHECK-PWR9-BE-NEXT: vextublx r26, r26, v3
645 ; CHECK-PWR9-BE-NEXT: mtfprwz f0, r27
646 ; CHECK-PWR9-BE-NEXT: addis r27, r2, .LCPI9_0@toc@ha
647 ; CHECK-PWR9-BE-NEXT: mtvsrwz v3, r28
648 ; CHECK-PWR9-BE-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
649 ; CHECK-PWR9-BE-NEXT: addi r27, r27, .LCPI9_0@toc@l
650 ; CHECK-PWR9-BE-NEXT: clrlwi r25, r25, 24
651 ; CHECK-PWR9-BE-NEXT: clrlwi r26, r26, 24
652 ; CHECK-PWR9-BE-NEXT: lxv vs1, 0(r27)
653 ; CHECK-PWR9-BE-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
654 ; CHECK-PWR9-BE-NEXT: sub r26, r25, r26
655 ; CHECK-PWR9-BE-NEXT: srawi r25, r26, 31
656 ; CHECK-PWR9-BE-NEXT: xor r26, r26, r25
657 ; CHECK-PWR9-BE-NEXT: sub r26, r26, r25
658 ; CHECK-PWR9-BE-NEXT: ld r25, -56(r1) # 8-byte Folded Reload
659 ; CHECK-PWR9-BE-NEXT: mtvsrwz v2, r26
660 ; CHECK-PWR9-BE-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
661 ; CHECK-PWR9-BE-NEXT: xxperm v2, vs0, vs1
662 ; CHECK-PWR9-BE-NEXT: mtfprwz f0, r29
663 ; CHECK-PWR9-BE-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
664 ; CHECK-PWR9-BE-NEXT: xxperm v3, vs0, vs1
665 ; CHECK-PWR9-BE-NEXT: mtfprwz f0, r0
666 ; CHECK-PWR9-BE-NEXT: vmrghh v2, v3, v2
667 ; CHECK-PWR9-BE-NEXT: mtvsrwz v3, r30
668 ; CHECK-PWR9-BE-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
669 ; CHECK-PWR9-BE-NEXT: xxperm v3, vs0, vs1
670 ; CHECK-PWR9-BE-NEXT: mtfprwz f0, r11
671 ; CHECK-PWR9-BE-NEXT: xxperm v4, vs0, vs1
672 ; CHECK-PWR9-BE-NEXT: vmrghh v3, v4, v3
673 ; CHECK-PWR9-BE-NEXT: mtvsrwz v4, r4
674 ; CHECK-PWR9-BE-NEXT: xxmrghw vs0, v3, v2
675 ; CHECK-PWR9-BE-NEXT: mtvsrwz v2, r10
676 ; CHECK-PWR9-BE-NEXT: mtvsrwz v3, r8
677 ; CHECK-PWR9-BE-NEXT: xxperm v2, vs2, vs1
678 ; CHECK-PWR9-BE-NEXT: mtfprwz f2, r7
679 ; CHECK-PWR9-BE-NEXT: xxperm v3, vs2, vs1
680 ; CHECK-PWR9-BE-NEXT: mtfprwz f2, r5
681 ; CHECK-PWR9-BE-NEXT: vmrghh v2, v3, v2
682 ; CHECK-PWR9-BE-NEXT: mtvsrwz v3, r6
683 ; CHECK-PWR9-BE-NEXT: xxperm v3, vs2, vs1
684 ; CHECK-PWR9-BE-NEXT: mtfprwz f2, r3
685 ; CHECK-PWR9-BE-NEXT: xxperm v4, vs2, vs1
686 ; CHECK-PWR9-BE-NEXT: vmrghh v3, v4, v3
687 ; CHECK-PWR9-BE-NEXT: xxmrghw vs1, v3, v2
688 ; CHECK-PWR9-BE-NEXT: xxmrghd v2, vs1, vs0
689 ; CHECK-PWR9-BE-NEXT: blr
690 ;
691 ; CHECK-PWR8-LABEL: sub_absv_8_ext:
692 ; CHECK-PWR8: # %bb.0: # %entry
693 ; CHECK-PWR8-NEXT: xxswapd vs0, v2
694 ; CHECK-PWR8-NEXT: xxswapd vs1, v3
695 ; CHECK-PWR8-NEXT: std r28, -32(r1) # 8-byte Folded Spill
696 ; CHECK-PWR8-NEXT: std r29, -24(r1) # 8-byte Folded Spill
697 ; CHECK-PWR8-NEXT: std r27, -40(r1) # 8-byte Folded Spill
698 ; CHECK-PWR8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
699 ; CHECK-PWR8-NEXT: mffprd r5, f0
700 ; CHECK-PWR8-NEXT: mffprd r11, f1
701 ; CHECK-PWR8-NEXT: std r25, -56(r1) # 8-byte Folded Spill
702 ; CHECK-PWR8-NEXT: std r26, -48(r1) # 8-byte Folded Spill
703 ; CHECK-PWR8-NEXT: clrldi r3, r5, 56
704 ; CHECK-PWR8-NEXT: clrldi r4, r11, 56
705 ; CHECK-PWR8-NEXT: rldicl r6, r5, 56, 56
706 ; CHECK-PWR8-NEXT: rldicl r7, r11, 56, 56
707 ; CHECK-PWR8-NEXT: rldicl r10, r5, 40, 56
708 ; CHECK-PWR8-NEXT: rldicl r12, r11, 40, 56
709 ; CHECK-PWR8-NEXT: rldicl r8, r5, 48, 56
710 ; CHECK-PWR8-NEXT: rldicl r9, r11, 48, 56
711 ; CHECK-PWR8-NEXT: rldicl r29, r5, 24, 56
712 ; CHECK-PWR8-NEXT: rldicl r28, r11, 24, 56
713 ; CHECK-PWR8-NEXT: rldicl r27, r5, 16, 56
714 ; CHECK-PWR8-NEXT: rldicl r0, r5, 32, 56
715 ; CHECK-PWR8-NEXT: rldicl r30, r11, 32, 56
716 ; CHECK-PWR8-NEXT: rldicl r5, r5, 8, 56
717 ; CHECK-PWR8-NEXT: std r24, -64(r1) # 8-byte Folded Spill
718 ; CHECK-PWR8-NEXT: clrlwi r3, r3, 24
719 ; CHECK-PWR8-NEXT: clrlwi r4, r4, 24
720 ; CHECK-PWR8-NEXT: clrlwi r6, r6, 24
721 ; CHECK-PWR8-NEXT: clrlwi r7, r7, 24
722 ; CHECK-PWR8-NEXT: clrlwi r10, r10, 24
723 ; CHECK-PWR8-NEXT: clrlwi r12, r12, 24
724 ; CHECK-PWR8-NEXT: sub r3, r3, r4
725 ; CHECK-PWR8-NEXT: sub r4, r6, r7
726 ; CHECK-PWR8-NEXT: sub r7, r10, r12
727 ; CHECK-PWR8-NEXT: clrlwi r8, r8, 24
728 ; CHECK-PWR8-NEXT: clrlwi r9, r9, 24
729 ; CHECK-PWR8-NEXT: clrlwi r29, r29, 24
730 ; CHECK-PWR8-NEXT: clrlwi r28, r28, 24
731 ; CHECK-PWR8-NEXT: sub r6, r8, r9
732 ; CHECK-PWR8-NEXT: sub r9, r29, r28
733 ; CHECK-PWR8-NEXT: clrlwi r27, r27, 24
734 ; CHECK-PWR8-NEXT: clrlwi r0, r0, 24
735 ; CHECK-PWR8-NEXT: clrlwi r30, r30, 24
736 ; CHECK-PWR8-NEXT: sub r8, r0, r30
737 ; CHECK-PWR8-NEXT: clrlwi r5, r5, 24
738 ; CHECK-PWR8-NEXT: srawi r10, r3, 31
739 ; CHECK-PWR8-NEXT: srawi r12, r4, 31
740 ; CHECK-PWR8-NEXT: srawi r28, r9, 31
741 ; CHECK-PWR8-NEXT: srawi r0, r6, 31
742 ; CHECK-PWR8-NEXT: srawi r29, r8, 31
743 ; CHECK-PWR8-NEXT: srawi r30, r7, 31
744 ; CHECK-PWR8-NEXT: xor r3, r3, r10
745 ; CHECK-PWR8-NEXT: sub r10, r3, r10
746 ; CHECK-PWR8-NEXT: rldicl r3, r11, 16, 56
747 ; CHECK-PWR8-NEXT: xor r4, r4, r12
748 ; CHECK-PWR8-NEXT: rldicl r11, r11, 8, 56
749 ; CHECK-PWR8-NEXT: xor r25, r9, r28
750 ; CHECK-PWR8-NEXT: sub r9, r4, r12
751 ; CHECK-PWR8-NEXT: sub r4, r25, r28
752 ; CHECK-PWR8-NEXT: mtvsrd v1, r9
753 ; CHECK-PWR8-NEXT: clrlwi r3, r3, 24
754 ; CHECK-PWR8-NEXT: mtvsrd v7, r4
755 ; CHECK-PWR8-NEXT: sub r3, r27, r3
756 ; CHECK-PWR8-NEXT: clrlwi r11, r11, 24
757 ; CHECK-PWR8-NEXT: xor r6, r6, r0
758 ; CHECK-PWR8-NEXT: sub r5, r5, r11
759 ; CHECK-PWR8-NEXT: xor r26, r8, r29
760 ; CHECK-PWR8-NEXT: sub r8, r6, r0
761 ; CHECK-PWR8-NEXT: mfvsrd r0, v3
762 ; CHECK-PWR8-NEXT: xor r7, r7, r30
763 ; CHECK-PWR8-NEXT: sub r7, r7, r30
764 ; CHECK-PWR8-NEXT: sub r6, r26, r29
765 ; CHECK-PWR8-NEXT: mtvsrd v6, r7
766 ; CHECK-PWR8-NEXT: clrldi r30, r0, 56
767 ; CHECK-PWR8-NEXT: rldicl r29, r0, 56, 56
768 ; CHECK-PWR8-NEXT: rldicl r28, r0, 48, 56
769 ; CHECK-PWR8-NEXT: rldicl r27, r0, 40, 56
770 ; CHECK-PWR8-NEXT: rldicl r26, r0, 32, 56
771 ; CHECK-PWR8-NEXT: rldicl r25, r0, 24, 56
772 ; CHECK-PWR8-NEXT: rldicl r24, r0, 16, 56
773 ; CHECK-PWR8-NEXT: rldicl r0, r0, 8, 56
774 ; CHECK-PWR8-NEXT: srawi r12, r3, 31
775 ; CHECK-PWR8-NEXT: srawi r11, r5, 31
776 ; CHECK-PWR8-NEXT: clrlwi r30, r30, 24
777 ; CHECK-PWR8-NEXT: clrlwi r29, r29, 24
778 ; CHECK-PWR8-NEXT: clrlwi r28, r28, 24
779 ; CHECK-PWR8-NEXT: clrlwi r27, r27, 24
780 ; CHECK-PWR8-NEXT: clrlwi r26, r26, 24
781 ; CHECK-PWR8-NEXT: clrlwi r25, r25, 24
782 ; CHECK-PWR8-NEXT: clrlwi r24, r24, 24
783 ; CHECK-PWR8-NEXT: clrlwi r0, r0, 24
784 ; CHECK-PWR8-NEXT: xor r3, r3, r12
785 ; CHECK-PWR8-NEXT: sub r3, r3, r12
786 ; CHECK-PWR8-NEXT: mfvsrd r12, v2
787 ; CHECK-PWR8-NEXT: xor r5, r5, r11
788 ; CHECK-PWR8-NEXT: sub r5, r5, r11
789 ; CHECK-PWR8-NEXT: mtvsrd v8, r5
790 ; CHECK-PWR8-NEXT: clrldi r11, r12, 56
791 ; CHECK-PWR8-NEXT: clrlwi r11, r11, 24
792 ; CHECK-PWR8-NEXT: sub r11, r11, r30
793 ; CHECK-PWR8-NEXT: srawi r30, r11, 31
794 ; CHECK-PWR8-NEXT: xor r11, r11, r30
795 ; CHECK-PWR8-NEXT: sub r11, r11, r30
796 ; CHECK-PWR8-NEXT: rldicl r30, r12, 56, 56
797 ; CHECK-PWR8-NEXT: clrlwi r30, r30, 24
798 ; CHECK-PWR8-NEXT: mtvsrd v2, r11
799 ; CHECK-PWR8-NEXT: sub r30, r30, r29
800 ; CHECK-PWR8-NEXT: srawi r29, r30, 31
801 ; CHECK-PWR8-NEXT: xor r30, r30, r29
802 ; CHECK-PWR8-NEXT: sub r30, r30, r29
803 ; CHECK-PWR8-NEXT: rldicl r29, r12, 48, 56
804 ; CHECK-PWR8-NEXT: clrlwi r29, r29, 24
805 ; CHECK-PWR8-NEXT: mtvsrd v3, r30
806 ; CHECK-PWR8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
807 ; CHECK-PWR8-NEXT: sub r29, r29, r28
808 ; CHECK-PWR8-NEXT: srawi r28, r29, 31
809 ; CHECK-PWR8-NEXT: xor r29, r29, r28
810 ; CHECK-PWR8-NEXT: sub r29, r29, r28
811 ; CHECK-PWR8-NEXT: rldicl r28, r12, 40, 56
812 ; CHECK-PWR8-NEXT: clrlwi r28, r28, 24
813 ; CHECK-PWR8-NEXT: sub r28, r28, r27
814 ; CHECK-PWR8-NEXT: srawi r27, r28, 31
815 ; CHECK-PWR8-NEXT: xor r28, r28, r27
816 ; CHECK-PWR8-NEXT: sub r28, r28, r27
817 ; CHECK-PWR8-NEXT: rldicl r27, r12, 32, 56
818 ; CHECK-PWR8-NEXT: clrlwi r27, r27, 24
819 ; CHECK-PWR8-NEXT: mtvsrd v4, r28
820 ; CHECK-PWR8-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
821 ; CHECK-PWR8-NEXT: sub r27, r27, r26
822 ; CHECK-PWR8-NEXT: srawi r26, r27, 31
823 ; CHECK-PWR8-NEXT: xor r27, r27, r26
824 ; CHECK-PWR8-NEXT: sub r27, r27, r26
825 ; CHECK-PWR8-NEXT: rldicl r26, r12, 24, 56
826 ; CHECK-PWR8-NEXT: clrlwi r26, r26, 24
827 ; CHECK-PWR8-NEXT: sub r26, r26, r25
828 ; CHECK-PWR8-NEXT: srawi r25, r26, 31
829 ; CHECK-PWR8-NEXT: xor r26, r26, r25
830 ; CHECK-PWR8-NEXT: sub r26, r26, r25
831 ; CHECK-PWR8-NEXT: rldicl r25, r12, 16, 56
832 ; CHECK-PWR8-NEXT: rldicl r12, r12, 8, 56
833 ; CHECK-PWR8-NEXT: clrlwi r25, r25, 24
834 ; CHECK-PWR8-NEXT: clrlwi r12, r12, 24
835 ; CHECK-PWR8-NEXT: mtvsrd v5, r26
836 ; CHECK-PWR8-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
837 ; CHECK-PWR8-NEXT: sub r25, r25, r24
838 ; CHECK-PWR8-NEXT: sub r12, r12, r0
839 ; CHECK-PWR8-NEXT: srawi r24, r25, 31
840 ; CHECK-PWR8-NEXT: srawi r0, r12, 31
841 ; CHECK-PWR8-NEXT: xor r25, r25, r24
842 ; CHECK-PWR8-NEXT: xor r12, r12, r0
843 ; CHECK-PWR8-NEXT: sub r25, r25, r24
844 ; CHECK-PWR8-NEXT: sub r12, r12, r0
845 ; CHECK-PWR8-NEXT: ld r24, -64(r1) # 8-byte Folded Reload
846 ; CHECK-PWR8-NEXT: mtvsrd v0, r12
847 ; CHECK-PWR8-NEXT: vmrghb v2, v3, v2
848 ; CHECK-PWR8-NEXT: mtvsrd v3, r29
849 ; CHECK-PWR8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
850 ; CHECK-PWR8-NEXT: vmrghb v3, v4, v3
851 ; CHECK-PWR8-NEXT: mtvsrd v4, r27
852 ; CHECK-PWR8-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
853 ; CHECK-PWR8-NEXT: vmrglh v2, v3, v2
854 ; CHECK-PWR8-NEXT: vmrghb v4, v5, v4
855 ; CHECK-PWR8-NEXT: mtvsrd v5, r25
856 ; CHECK-PWR8-NEXT: ld r25, -56(r1) # 8-byte Folded Reload
857 ; CHECK-PWR8-NEXT: vmrghb v5, v0, v5
858 ; CHECK-PWR8-NEXT: mtvsrd v0, r10
859 ; CHECK-PWR8-NEXT: vmrglh v3, v5, v4
860 ; CHECK-PWR8-NEXT: xxmrglw vs0, v3, v2
861 ; CHECK-PWR8-NEXT: vmrghb v0, v1, v0
862 ; CHECK-PWR8-NEXT: mtvsrd v1, r8
863 ; CHECK-PWR8-NEXT: vmrghb v1, v6, v1
864 ; CHECK-PWR8-NEXT: mtvsrd v6, r6
865 ; CHECK-PWR8-NEXT: vmrglh v4, v1, v0
866 ; CHECK-PWR8-NEXT: vmrghb v6, v7, v6
867 ; CHECK-PWR8-NEXT: mtvsrd v7, r3
868 ; CHECK-PWR8-NEXT: vmrghb v7, v8, v7
869 ; CHECK-PWR8-NEXT: vmrglh v5, v7, v6
870 ; CHECK-PWR8-NEXT: xxmrglw vs1, v5, v4
871 ; CHECK-PWR8-NEXT: xxmrgld v2, vs0, vs1
872 ; CHECK-PWR8-NEXT: blr
873 ;
874 ; CHECK-PWR7-LABEL: sub_absv_8_ext:
875 ; CHECK-PWR7: # %bb.0: # %entry
876 ; CHECK-PWR7-NEXT: stdu r1, -416(r1)
877 ; CHECK-PWR7-NEXT: .cfi_def_cfa_offset 416
878 ; CHECK-PWR7-NEXT: .cfi_offset r23, -72
879 ; CHECK-PWR7-NEXT: .cfi_offset r24, -64
880 ; CHECK-PWR7-NEXT: .cfi_offset r25, -56
881 ; CHECK-PWR7-NEXT: .cfi_offset r26, -48
882 ; CHECK-PWR7-NEXT: .cfi_offset r27, -40
883 ; CHECK-PWR7-NEXT: .cfi_offset r28, -32
884 ; CHECK-PWR7-NEXT: .cfi_offset r29, -24
885 ; CHECK-PWR7-NEXT: .cfi_offset r30, -16
886 ; CHECK-PWR7-NEXT: addi r3, r1, 304
887 ; CHECK-PWR7-NEXT: std r23, 344(r1) # 8-byte Folded Spill
888 ; CHECK-PWR7-NEXT: addi r4, r1, 320
889 ; CHECK-PWR7-NEXT: std r24, 352(r1) # 8-byte Folded Spill
890 ; CHECK-PWR7-NEXT: std r25, 360(r1) # 8-byte Folded Spill
891 ; CHECK-PWR7-NEXT: std r26, 368(r1) # 8-byte Folded Spill
892 ; CHECK-PWR7-NEXT: std r27, 376(r1) # 8-byte Folded Spill
893 ; CHECK-PWR7-NEXT: std r28, 384(r1) # 8-byte Folded Spill
894 ; CHECK-PWR7-NEXT: std r29, 392(r1) # 8-byte Folded Spill
895 ; CHECK-PWR7-NEXT: std r30, 400(r1) # 8-byte Folded Spill
896 ; CHECK-PWR7-NEXT: stxvw4x v2, 0, r3
897 ; CHECK-PWR7-NEXT: lbz r3, 304(r1)
898 ; CHECK-PWR7-NEXT: stxvw4x v3, 0, r4
899 ; CHECK-PWR7-NEXT: lbz r9, 307(r1)
900 ; CHECK-PWR7-NEXT: lbz r10, 323(r1)
901 ; CHECK-PWR7-NEXT: lbz r11, 308(r1)
902 ; CHECK-PWR7-NEXT: lbz r12, 324(r1)
903 ; CHECK-PWR7-NEXT: lbz r0, 309(r1)
904 ; CHECK-PWR7-NEXT: lbz r30, 325(r1)
905 ; CHECK-PWR7-NEXT: sub r9, r9, r10
906 ; CHECK-PWR7-NEXT: lbz r29, 310(r1)
907 ; CHECK-PWR7-NEXT: lbz r28, 326(r1)
908 ; CHECK-PWR7-NEXT: sub r11, r11, r12
909 ; CHECK-PWR7-NEXT: lbz r27, 311(r1)
910 ; CHECK-PWR7-NEXT: lbz r26, 327(r1)
911 ; CHECK-PWR7-NEXT: sub r0, r0, r30
912 ; CHECK-PWR7-NEXT: lbz r25, 312(r1)
913 ; CHECK-PWR7-NEXT: lbz r24, 328(r1)
914 ; CHECK-PWR7-NEXT: sub r29, r29, r28
915 ; CHECK-PWR7-NEXT: lbz r10, 315(r1)
916 ; CHECK-PWR7-NEXT: lbz r12, 331(r1)
917 ; CHECK-PWR7-NEXT: sub r27, r27, r26
918 ; CHECK-PWR7-NEXT: lbz r30, 316(r1)
919 ; CHECK-PWR7-NEXT: lbz r28, 332(r1)
920 ; CHECK-PWR7-NEXT: sub r25, r25, r24
921 ; CHECK-PWR7-NEXT: lbz r4, 320(r1)
922 ; CHECK-PWR7-NEXT: lbz r5, 305(r1)
923 ; CHECK-PWR7-NEXT: sub r10, r10, r12
924 ; CHECK-PWR7-NEXT: lbz r6, 321(r1)
925 ; CHECK-PWR7-NEXT: lbz r26, 317(r1)
926 ; CHECK-PWR7-NEXT: sub r30, r30, r28
927 ; CHECK-PWR7-NEXT: lbz r24, 333(r1)
928 ; CHECK-PWR7-NEXT: lbz r12, 319(r1)
929 ; CHECK-PWR7-NEXT: sub r3, r3, r4
930 ; CHECK-PWR7-NEXT: lbz r28, 335(r1)
931 ; CHECK-PWR7-NEXT: lbz r7, 306(r1)
932 ; CHECK-PWR7-NEXT: sub r5, r5, r6
933 ; CHECK-PWR7-NEXT: lbz r8, 322(r1)
934 ; CHECK-PWR7-NEXT: sub r26, r26, r24
935 ; CHECK-PWR7-NEXT: srawi r24, r5, 31
936 ; CHECK-PWR7-NEXT: lbz r23, 313(r1)
937 ; CHECK-PWR7-NEXT: sub r12, r12, r28
938 ; CHECK-PWR7-NEXT: srawi r28, r3, 31
939 ; CHECK-PWR7-NEXT: xor r5, r5, r24
940 ; CHECK-PWR7-NEXT: lbz r4, 329(r1)
941 ; CHECK-PWR7-NEXT: sub r7, r7, r8
942 ; CHECK-PWR7-NEXT: xor r3, r3, r28
943 ; CHECK-PWR7-NEXT: lbz r6, 314(r1)
944 ; CHECK-PWR7-NEXT: lbz r8, 330(r1)
945 ; CHECK-PWR7-NEXT: sub r3, r3, r28
946 ; CHECK-PWR7-NEXT: srawi r28, r7, 31
947 ; CHECK-PWR7-NEXT: sub r5, r5, r24
948 ; CHECK-PWR7-NEXT: srawi r24, r9, 31
949 ; CHECK-PWR7-NEXT: xor r7, r7, r28
950 ; CHECK-PWR7-NEXT: xor r9, r9, r24
951 ; CHECK-PWR7-NEXT: sub r7, r7, r28
952 ; CHECK-PWR7-NEXT: srawi r28, r11, 31
953 ; CHECK-PWR7-NEXT: sub r9, r9, r24
954 ; CHECK-PWR7-NEXT: srawi r24, r0, 31
955 ; CHECK-PWR7-NEXT: xor r11, r11, r28
956 ; CHECK-PWR7-NEXT: xor r0, r0, r24
957 ; CHECK-PWR7-NEXT: sub r11, r11, r28
958 ; CHECK-PWR7-NEXT: srawi r28, r29, 31
959 ; CHECK-PWR7-NEXT: sub r0, r0, r24
960 ; CHECK-PWR7-NEXT: srawi r24, r27, 31
961 ; CHECK-PWR7-NEXT: sub r4, r23, r4
962 ; CHECK-PWR7-NEXT: xor r29, r29, r28
963 ; CHECK-PWR7-NEXT: lbz r23, 318(r1)
964 ; CHECK-PWR7-NEXT: xor r27, r27, r24
965 ; CHECK-PWR7-NEXT: sub r29, r29, r28
966 ; CHECK-PWR7-NEXT: srawi r28, r25, 31
967 ; CHECK-PWR7-NEXT: sub r27, r27, r24
968 ; CHECK-PWR7-NEXT: srawi r24, r4, 31
969 ; CHECK-PWR7-NEXT: sub r6, r6, r8
970 ; CHECK-PWR7-NEXT: xor r25, r25, r28
971 ; CHECK-PWR7-NEXT: lbz r8, 334(r1)
972 ; CHECK-PWR7-NEXT: xor r4, r4, r24
973 ; CHECK-PWR7-NEXT: sub r28, r25, r28
974 ; CHECK-PWR7-NEXT: srawi r25, r6, 31
975 ; CHECK-PWR7-NEXT: sub r4, r4, r24
976 ; CHECK-PWR7-NEXT: srawi r24, r10, 31
977 ; CHECK-PWR7-NEXT: xor r6, r6, r25
978 ; CHECK-PWR7-NEXT: xor r10, r10, r24
979 ; CHECK-PWR7-NEXT: sub r6, r6, r25
980 ; CHECK-PWR7-NEXT: srawi r25, r30, 31
981 ; CHECK-PWR7-NEXT: sub r10, r10, r24
982 ; CHECK-PWR7-NEXT: srawi r24, r26, 31
983 ; CHECK-PWR7-NEXT: sub r8, r23, r8
984 ; CHECK-PWR7-NEXT: xor r30, r30, r25
985 ; CHECK-PWR7-NEXT: ld r23, 344(r1) # 8-byte Folded Reload
986 ; CHECK-PWR7-NEXT: xor r26, r26, r24
987 ; CHECK-PWR7-NEXT: sub r30, r30, r25
988 ; CHECK-PWR7-NEXT: srawi r25, r12, 31
989 ; CHECK-PWR7-NEXT: sub r26, r26, r24
990 ; CHECK-PWR7-NEXT: srawi r24, r8, 31
991 ; CHECK-PWR7-NEXT: xor r12, r12, r25
992 ; CHECK-PWR7-NEXT: xor r8, r8, r24
993 ; CHECK-PWR7-NEXT: sub r12, r12, r25
994 ; CHECK-PWR7-NEXT: addi r25, r1, 272
995 ; CHECK-PWR7-NEXT: sub r8, r8, r24
996 ; CHECK-PWR7-NEXT: stb r12, 288(r1)
997 ; CHECK-PWR7-NEXT: addi r12, r1, 288
998 ; CHECK-PWR7-NEXT: stb r8, 272(r1)
999 ; CHECK-PWR7-NEXT: stb r26, 256(r1)
1000 ; CHECK-PWR7-NEXT: stb r30, 240(r1)
1001 ; CHECK-PWR7-NEXT: stb r10, 224(r1)
1002 ; CHECK-PWR7-NEXT: stb r6, 208(r1)
1003 ; CHECK-PWR7-NEXT: stb r4, 192(r1)
1004 ; CHECK-PWR7-NEXT: stb r28, 176(r1)
1005 ; CHECK-PWR7-NEXT: stb r27, 160(r1)
1006 ; CHECK-PWR7-NEXT: stb r29, 144(r1)
1007 ; CHECK-PWR7-NEXT: stb r0, 128(r1)
1008 ; CHECK-PWR7-NEXT: stb r11, 112(r1)
1009 ; CHECK-PWR7-NEXT: stb r9, 96(r1)
1010 ; CHECK-PWR7-NEXT: stb r7, 80(r1)
1011 ; CHECK-PWR7-NEXT: stb r5, 64(r1)
1012 ; CHECK-PWR7-NEXT: stb r3, 48(r1)
1013 ; CHECK-PWR7-NEXT: addi r8, r1, 256
1014 ; CHECK-PWR7-NEXT: addi r26, r1, 240
1015 ; CHECK-PWR7-NEXT: lxvw4x v2, 0, r12
1016 ; CHECK-PWR7-NEXT: lxvw4x v3, 0, r25
1017 ; CHECK-PWR7-NEXT: addi r10, r1, 224
1018 ; CHECK-PWR7-NEXT: addi r30, r1, 208
1019 ; CHECK-PWR7-NEXT: addi r3, r1, 192
1020 ; CHECK-PWR7-NEXT: addi r4, r1, 176
1021 ; CHECK-PWR7-NEXT: addi r5, r1, 160
1022 ; CHECK-PWR7-NEXT: addi r6, r1, 144
1023 ; CHECK-PWR7-NEXT: lxvw4x v4, 0, r8
1024 ; CHECK-PWR7-NEXT: lxvw4x v5, 0, r26
1025 ; CHECK-PWR7-NEXT: addi r7, r1, 128
1026 ; CHECK-PWR7-NEXT: addi r8, r1, 112
1027 ; CHECK-PWR7-NEXT: lxvw4x v0, 0, r10
1028 ; CHECK-PWR7-NEXT: lxvw4x v1, 0, r30
1029 ; CHECK-PWR7-NEXT: vmrghb v2, v3, v2
1030 ; CHECK-PWR7-NEXT: addi r9, r1, 96
1031 ; CHECK-PWR7-NEXT: lxvw4x v6, 0, r3
1032 ; CHECK-PWR7-NEXT: lxvw4x v7, 0, r4
1033 ; CHECK-PWR7-NEXT: addi r3, r1, 80
1034 ; CHECK-PWR7-NEXT: addi r4, r1, 64
1035 ; CHECK-PWR7-NEXT: lxvw4x v3, 0, r5
1036 ; CHECK-PWR7-NEXT: lxvw4x v8, 0, r6
1037 ; CHECK-PWR7-NEXT: addi r5, r1, 48
1038 ; CHECK-PWR7-NEXT: vmrghb v4, v5, v4
1039 ; CHECK-PWR7-NEXT: lxvw4x v5, 0, r7
1040 ; CHECK-PWR7-NEXT: lxvw4x v9, 0, r8
1041 ; CHECK-PWR7-NEXT: vmrghb v0, v1, v0
1042 ; CHECK-PWR7-NEXT: lxvw4x v1, 0, r9
1043 ; CHECK-PWR7-NEXT: lxvw4x v10, 0, r3
1044 ; CHECK-PWR7-NEXT: vmrghb v6, v7, v6
1045 ; CHECK-PWR7-NEXT: lxvw4x v7, 0, r4
1046 ; CHECK-PWR7-NEXT: vmrghb v3, v8, v3
1047 ; CHECK-PWR7-NEXT: lxvw4x v8, 0, r5
1048 ; CHECK-PWR7-NEXT: vmrghb v5, v9, v5
1049 ; CHECK-PWR7-NEXT: ld r30, 400(r1) # 8-byte Folded Reload
1050 ; CHECK-PWR7-NEXT: ld r29, 392(r1) # 8-byte Folded Reload
1051 ; CHECK-PWR7-NEXT: vmrghb v1, v10, v1
1052 ; CHECK-PWR7-NEXT: ld r28, 384(r1) # 8-byte Folded Reload
1053 ; CHECK-PWR7-NEXT: ld r27, 376(r1) # 8-byte Folded Reload
1054 ; CHECK-PWR7-NEXT: vmrghb v7, v8, v7
1055 ; CHECK-PWR7-NEXT: ld r26, 368(r1) # 8-byte Folded Reload
1056 ; CHECK-PWR7-NEXT: ld r25, 360(r1) # 8-byte Folded Reload
1057 ; CHECK-PWR7-NEXT: vmrghh v2, v4, v2
1058 ; CHECK-PWR7-NEXT: ld r24, 352(r1) # 8-byte Folded Reload
1059 ; CHECK-PWR7-NEXT: vmrghh v4, v6, v0
1060 ; CHECK-PWR7-NEXT: vmrghh v3, v5, v3
1061 ; CHECK-PWR7-NEXT: vmrghh v5, v7, v1
1062 ; CHECK-PWR7-NEXT: xxmrghw vs0, v4, v2
1063 ; CHECK-PWR7-NEXT: xxmrghw vs1, v5, v3
1064 ; CHECK-PWR7-NEXT: xxmrghd v2, vs1, vs0
1065 ; CHECK-PWR7-NEXT: addi r1, r1, 416
1066 ; CHECK-PWR7-NEXT: blr
1067 entry:
1068 %vecext = extractelement <16 x i8> %a, i32 0
1069 %conv = zext i8 %vecext to i32
1070 %vecext1 = extractelement <16 x i8> %b, i32 0
1071 %conv2 = zext i8 %vecext1 to i32
1072 %sub = sub nsw i32 %conv, %conv2
1073 %ispos = icmp sgt i32 %sub, -1
1074 %neg = sub nsw i32 0, %sub
1075 %0 = select i1 %ispos, i32 %sub, i32 %neg
1076 %conv3 = trunc i32 %0 to i8
1077 %vecins = insertelement <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, i8 %conv3, i32 0
1078 %vecext4 = extractelement <16 x i8> %a, i32 1
1079 %conv5 = zext i8 %vecext4 to i32
1080 %vecext6 = extractelement <16 x i8> %b, i32 1
1081 %conv7 = zext i8 %vecext6 to i32
1082 %sub8 = sub nsw i32 %conv5, %conv7
1083 %ispos171 = icmp sgt i32 %sub8, -1
1084 %neg172 = sub nsw i32 0, %sub8
1085 %1 = select i1 %ispos171, i32 %sub8, i32 %neg172
1086 %conv10 = trunc i32 %1 to i8
1087 %vecins11 = insertelement <16 x i8> %vecins, i8 %conv10, i32 1
1088 %vecext12 = extractelement <16 x i8> %a, i32 2
1089 %conv13 = zext i8 %vecext12 to i32
1090 %vecext14 = extractelement <16 x i8> %b, i32 2
1091 %conv15 = zext i8 %vecext14 to i32
1092 %sub16 = sub nsw i32 %conv13, %conv15
1093 %ispos173 = icmp sgt i32 %sub16, -1
1094 %neg174 = sub nsw i32 0, %sub16
1095 %2 = select i1 %ispos173, i32 %sub16, i32 %neg174
1096 %conv18 = trunc i32 %2 to i8
1097 %vecins19 = insertelement <16 x i8> %vecins11, i8 %conv18, i32 2
1098 %vecext20 = extractelement <16 x i8> %a, i32 3
1099 %conv21 = zext i8 %vecext20 to i32
1100 %vecext22 = extractelement <16 x i8> %b, i32 3
1101 %conv23 = zext i8 %vecext22 to i32
1102 %sub24 = sub nsw i32 %conv21, %conv23
1103 %ispos175 = icmp sgt i32 %sub24, -1
1104 %neg176 = sub nsw i32 0, %sub24
1105 %3 = select i1 %ispos175, i32 %sub24, i32 %neg176
1106 %conv26 = trunc i32 %3 to i8
1107 %vecins27 = insertelement <16 x i8> %vecins19, i8 %conv26, i32 3
1108 %vecext28 = extractelement <16 x i8> %a, i32 4
1109 %conv29 = zext i8 %vecext28 to i32
1110 %vecext30 = extractelement <16 x i8> %b, i32 4
1111 %conv31 = zext i8 %vecext30 to i32
1112 %sub32 = sub nsw i32 %conv29, %conv31
1113 %ispos177 = icmp sgt i32 %sub32, -1
1114 %neg178 = sub nsw i32 0, %sub32
1115 %4 = select i1 %ispos177, i32 %sub32, i32 %neg178
1116 %conv34 = trunc i32 %4 to i8
1117 %vecins35 = insertelement <16 x i8> %vecins27, i8 %conv34, i32 4
1118 %vecext36 = extractelement <16 x i8> %a, i32 5
1119 %conv37 = zext i8 %vecext36 to i32
1120 %vecext38 = extractelement <16 x i8> %b, i32 5
1121 %conv39 = zext i8 %vecext38 to i32
1122 %sub40 = sub nsw i32 %conv37, %conv39
1123 %ispos179 = icmp sgt i32 %sub40, -1
1124 %neg180 = sub nsw i32 0, %sub40
1125 %5 = select i1 %ispos179, i32 %sub40, i32 %neg180
1126 %conv42 = trunc i32 %5 to i8
1127 %vecins43 = insertelement <16 x i8> %vecins35, i8 %conv42, i32 5
1128 %vecext44 = extractelement <16 x i8> %a, i32 6
1129 %conv45 = zext i8 %vecext44 to i32
1130 %vecext46 = extractelement <16 x i8> %b, i32 6
1131 %conv47 = zext i8 %vecext46 to i32
1132 %sub48 = sub nsw i32 %conv45, %conv47
1133 %ispos181 = icmp sgt i32 %sub48, -1
1134 %neg182 = sub nsw i32 0, %sub48
1135 %6 = select i1 %ispos181, i32 %sub48, i32 %neg182
1136 %conv50 = trunc i32 %6 to i8
1137 %vecins51 = insertelement <16 x i8> %vecins43, i8 %conv50, i32 6
1138 %vecext52 = extractelement <16 x i8> %a, i32 7
1139 %conv53 = zext i8 %vecext52 to i32
1140 %vecext54 = extractelement <16 x i8> %b, i32 7
1141 %conv55 = zext i8 %vecext54 to i32
1142 %sub56 = sub nsw i32 %conv53, %conv55
1143 %ispos183 = icmp sgt i32 %sub56, -1
1144 %neg184 = sub nsw i32 0, %sub56
1145 %7 = select i1 %ispos183, i32 %sub56, i32 %neg184
1146 %conv58 = trunc i32 %7 to i8
1147 %vecins59 = insertelement <16 x i8> %vecins51, i8 %conv58, i32 7
1148 %vecext60 = extractelement <16 x i8> %a, i32 8
1149 %conv61 = zext i8 %vecext60 to i32
1150 %vecext62 = extractelement <16 x i8> %b, i32 8
1151 %conv63 = zext i8 %vecext62 to i32
1152 %sub64 = sub nsw i32 %conv61, %conv63
1153 %ispos185 = icmp sgt i32 %sub64, -1
1154 %neg186 = sub nsw i32 0, %sub64
1155 %8 = select i1 %ispos185, i32 %sub64, i32 %neg186
1156 %conv66 = trunc i32 %8 to i8
1157 %vecins67 = insertelement <16 x i8> %vecins59, i8 %conv66, i32 8
1158 %vecext68 = extractelement <16 x i8> %a, i32 9
1159 %conv69 = zext i8 %vecext68 to i32
1160 %vecext70 = extractelement <16 x i8> %b, i32 9
1161 %conv71 = zext i8 %vecext70 to i32
1162 %sub72 = sub nsw i32 %conv69, %conv71
1163 %ispos187 = icmp sgt i32 %sub72, -1
1164 %neg188 = sub nsw i32 0, %sub72
1165 %9 = select i1 %ispos187, i32 %sub72, i32 %neg188
1166 %conv74 = trunc i32 %9 to i8
1167 %vecins75 = insertelement <16 x i8> %vecins67, i8 %conv74, i32 9
1168 %vecext76 = extractelement <16 x i8> %a, i32 10
1169 %conv77 = zext i8 %vecext76 to i32
1170 %vecext78 = extractelement <16 x i8> %b, i32 10
1171 %conv79 = zext i8 %vecext78 to i32
1172 %sub80 = sub nsw i32 %conv77, %conv79
1173 %ispos189 = icmp sgt i32 %sub80, -1
1174 %neg190 = sub nsw i32 0, %sub80
1175 %10 = select i1 %ispos189, i32 %sub80, i32 %neg190
1176 %conv82 = trunc i32 %10 to i8
1177 %vecins83 = insertelement <16 x i8> %vecins75, i8 %conv82, i32 10
1178 %vecext84 = extractelement <16 x i8> %a, i32 11
1179 %conv85 = zext i8 %vecext84 to i32
1180 %vecext86 = extractelement <16 x i8> %b, i32 11
1181 %conv87 = zext i8 %vecext86 to i32
1182 %sub88 = sub nsw i32 %conv85, %conv87
1183 %ispos191 = icmp sgt i32 %sub88, -1
1184 %neg192 = sub nsw i32 0, %sub88
1185 %11 = select i1 %ispos191, i32 %sub88, i32 %neg192
1186 %conv90 = trunc i32 %11 to i8
1187 %vecins91 = insertelement <16 x i8> %vecins83, i8 %conv90, i32 11
1188 %vecext92 = extractelement <16 x i8> %a, i32 12
1189 %conv93 = zext i8 %vecext92 to i32
1190 %vecext94 = extractelement <16 x i8> %b, i32 12
1191 %conv95 = zext i8 %vecext94 to i32
1192 %sub96 = sub nsw i32 %conv93, %conv95
1193 %ispos193 = icmp sgt i32 %sub96, -1
1194 %neg194 = sub nsw i32 0, %sub96
1195 %12 = select i1 %ispos193, i32 %sub96, i32 %neg194
1196 %conv98 = trunc i32 %12 to i8
1197 %vecins99 = insertelement <16 x i8> %vecins91, i8 %conv98, i32 12
1198 %vecext100 = extractelement <16 x i8> %a, i32 13
1199 %conv101 = zext i8 %vecext100 to i32
1200 %vecext102 = extractelement <16 x i8> %b, i32 13
1201 %conv103 = zext i8 %vecext102 to i32
1202 %sub104 = sub nsw i32 %conv101, %conv103
1203 %ispos195 = icmp sgt i32 %sub104, -1
1204 %neg196 = sub nsw i32 0, %sub104
1205 %13 = select i1 %ispos195, i32 %sub104, i32 %neg196
1206 %conv106 = trunc i32 %13 to i8
1207 %vecins107 = insertelement <16 x i8> %vecins99, i8 %conv106, i32 13
1208 %vecext108 = extractelement <16 x i8> %a, i32 14
1209 %conv109 = zext i8 %vecext108 to i32
1210 %vecext110 = extractelement <16 x i8> %b, i32 14
1211 %conv111 = zext i8 %vecext110 to i32
1212 %sub112 = sub nsw i32 %conv109, %conv111
1213 %ispos197 = icmp sgt i32 %sub112, -1
1214 %neg198 = sub nsw i32 0, %sub112
1215 %14 = select i1 %ispos197, i32 %sub112, i32 %neg198
1216 %conv114 = trunc i32 %14 to i8
1217 %vecins115 = insertelement <16 x i8> %vecins107, i8 %conv114, i32 14
1218 %vecext116 = extractelement <16 x i8> %a, i32 15
1219 %conv117 = zext i8 %vecext116 to i32
1220 %vecext118 = extractelement <16 x i8> %b, i32 15
1221 %conv119 = zext i8 %vecext118 to i32
1222 %sub120 = sub nsw i32 %conv117, %conv119
1223 %ispos199 = icmp sgt i32 %sub120, -1
1224 %neg200 = sub nsw i32 0, %sub120
1225 %15 = select i1 %ispos199, i32 %sub120, i32 %neg200
1226 %conv122 = trunc i32 %15 to i8
1227 %vecins123 = insertelement <16 x i8> %vecins115, i8 %conv122, i32 15
1228 ret <16 x i8> %vecins123
1229 }
1231 define <4 x i32> @sub_absv_vec_32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr {
1232 ; CHECK-PWR9-LABEL: sub_absv_vec_32:
1233 ; CHECK-PWR9: # %bb.0: # %entry
1234 ; CHECK-PWR9-NEXT: xvnegsp v3, v3
1235 ; CHECK-PWR9-NEXT: xvnegsp v2, v2
1236 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1237 ; CHECK-PWR9-NEXT: blr
1238 ;
1239 ; CHECK-PWR8-LABEL: sub_absv_vec_32:
1240 ; CHECK-PWR8: # %bb.0: # %entry
1241 ; CHECK-PWR8-NEXT: vsubuwm v2, v2, v3
1242 ; CHECK-PWR8-NEXT: xxlxor v3, v3, v3
1243 ; CHECK-PWR8-NEXT: vsubuwm v3, v3, v2
1244 ; CHECK-PWR8-NEXT: vmaxsw v2, v2, v3
1245 ; CHECK-PWR8-NEXT: blr
1246 ;
1247 ; CHECK-PWR7-LABEL: sub_absv_vec_32:
1248 ; CHECK-PWR7: # %bb.0: # %entry
1249 ; CHECK-PWR7-NEXT: xxlxor v4, v4, v4
1250 ; CHECK-PWR7-NEXT: vsubuwm v2, v2, v3
1251 ; CHECK-PWR7-NEXT: vsubuwm v3, v4, v2
1252 ; CHECK-PWR7-NEXT: vmaxsw v2, v2, v3
1253 ; CHECK-PWR7-NEXT: blr
1254 entry:
1255 %sub = sub nsw <4 x i32> %a, %b
1256 %sub.i = sub <4 x i32> zeroinitializer, %sub
1257 %0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %sub, <4 x i32> %sub.i)
1258 ret <4 x i32> %0
1259 }
1261 define <8 x i16> @sub_absv_vec_16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr {
1262 ; CHECK-PWR9-LABEL: sub_absv_vec_16:
1263 ; CHECK-PWR9: # %bb.0: # %entry
1264 ; CHECK-PWR9-NEXT: vsubuhm v2, v2, v3
1265 ; CHECK-PWR9-NEXT: xxlxor v3, v3, v3
1266 ; CHECK-PWR9-NEXT: vsubuhm v3, v3, v2
1267 ; CHECK-PWR9-NEXT: vmaxsh v2, v2, v3
1268 ; CHECK-PWR9-NEXT: blr
1269 ;
1270 ; CHECK-PWR8-LABEL: sub_absv_vec_16:
1271 ; CHECK-PWR8: # %bb.0: # %entry
1272 ; CHECK-PWR8-NEXT: vsubuhm v2, v2, v3
1273 ; CHECK-PWR8-NEXT: xxlxor v3, v3, v3
1274 ; CHECK-PWR8-NEXT: vsubuhm v3, v3, v2
1275 ; CHECK-PWR8-NEXT: vmaxsh v2, v2, v3
1276 ; CHECK-PWR8-NEXT: blr
1277 ;
1278 ; CHECK-PWR7-LABEL: sub_absv_vec_16:
1279 ; CHECK-PWR7: # %bb.0: # %entry
1280 ; CHECK-PWR7-NEXT: xxlxor v4, v4, v4
1281 ; CHECK-PWR7-NEXT: vsubuhm v2, v2, v3
1282 ; CHECK-PWR7-NEXT: vsubuhm v3, v4, v2
1283 ; CHECK-PWR7-NEXT: vmaxsh v2, v2, v3
1284 ; CHECK-PWR7-NEXT: blr
1285 entry:
1286 %sub = sub nsw <8 x i16> %a, %b
1287 %sub.i = sub <8 x i16> zeroinitializer, %sub
1288 %0 = tail call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %sub, <8 x i16> %sub.i)
1289 ret <8 x i16> %0
1290 }
1292 define <16 x i8> @sub_absv_vec_8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr {
1293 ; CHECK-PWR9-LABEL: sub_absv_vec_8:
1294 ; CHECK-PWR9: # %bb.0: # %entry
1295 ; CHECK-PWR9-NEXT: vsububm v2, v2, v3
1296 ; CHECK-PWR9-NEXT: xxlxor v3, v3, v3
1297 ; CHECK-PWR9-NEXT: vsububm v3, v3, v2
1298 ; CHECK-PWR9-NEXT: vmaxsb v2, v2, v3
1299 ; CHECK-PWR9-NEXT: blr
1300 ;
1301 ; CHECK-PWR8-LABEL: sub_absv_vec_8:
1302 ; CHECK-PWR8: # %bb.0: # %entry
1303 ; CHECK-PWR8-NEXT: vsububm v2, v2, v3
1304 ; CHECK-PWR8-NEXT: xxlxor v3, v3, v3
1305 ; CHECK-PWR8-NEXT: vsububm v3, v3, v2
1306 ; CHECK-PWR8-NEXT: vmaxsb v2, v2, v3
1307 ; CHECK-PWR8-NEXT: blr
1308 ;
1309 ; CHECK-PWR7-LABEL: sub_absv_vec_8:
1310 ; CHECK-PWR7: # %bb.0: # %entry
1311 ; CHECK-PWR7-NEXT: xxlxor v4, v4, v4
1312 ; CHECK-PWR7-NEXT: vsububm v2, v2, v3
1313 ; CHECK-PWR7-NEXT: vsububm v3, v4, v2
1314 ; CHECK-PWR7-NEXT: vmaxsb v2, v2, v3
1315 ; CHECK-PWR7-NEXT: blr
1316 entry:
1317 %sub = sub nsw <16 x i8> %a, %b
1318 %sub.i = sub <16 x i8> zeroinitializer, %sub
1319 %0 = tail call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %sub, <16 x i8> %sub.i)
1320 ret <16 x i8> %0
1321 }
1323 define <4 x i32> @zext_sub_absd32(<4 x i16>, <4 x i16>) local_unnamed_addr {
1324 ; CHECK-PWR9-LE-LABEL: zext_sub_absd32:
1325 ; CHECK-PWR9-LE: # %bb.0:
1326 ; CHECK-PWR9-LE-NEXT: xxlxor v4, v4, v4
1327 ; CHECK-PWR9-LE-NEXT: vmrglh v2, v4, v2
1328 ; CHECK-PWR9-LE-NEXT: vmrglh v3, v4, v3
1329 ; CHECK-PWR9-LE-NEXT: vabsduw v2, v2, v3
1330 ; CHECK-PWR9-LE-NEXT: blr
1331 ;
1332 ; CHECK-PWR9-BE-LABEL: zext_sub_absd32:
1333 ; CHECK-PWR9-BE: # %bb.0:
1334 ; CHECK-PWR9-BE-NEXT: xxlxor v4, v4, v4
1335 ; CHECK-PWR9-BE-NEXT: vmrghh v2, v4, v2
1336 ; CHECK-PWR9-BE-NEXT: vmrghh v3, v4, v3
1337 ; CHECK-PWR9-BE-NEXT: vabsduw v2, v2, v3
1338 ; CHECK-PWR9-BE-NEXT: blr
1339 ;
1340 ; CHECK-PWR8-LABEL: zext_sub_absd32:
1341 ; CHECK-PWR8: # %bb.0:
1342 ; CHECK-PWR8-NEXT: xxlxor v4, v4, v4
1343 ; CHECK-PWR8-NEXT: vmrglh v2, v4, v2
1344 ; CHECK-PWR8-NEXT: vmrglh v3, v4, v3
1345 ; CHECK-PWR8-NEXT: vsubuwm v2, v2, v3
1346 ; CHECK-PWR8-NEXT: vsubuwm v3, v4, v2
1347 ; CHECK-PWR8-NEXT: vmaxsw v2, v2, v3
1348 ; CHECK-PWR8-NEXT: blr
1349 ;
1350 ; CHECK-PWR7-LABEL: zext_sub_absd32:
1351 ; CHECK-PWR7: # %bb.0:
1352 ; CHECK-PWR7-NEXT: addis r3, r2, .LCPI13_0@toc@ha
1353 ; CHECK-PWR7-NEXT: xxlxor v5, v5, v5
1354 ; CHECK-PWR7-NEXT: addi r3, r3, .LCPI13_0@toc@l
1355 ; CHECK-PWR7-NEXT: lxvw4x v4, 0, r3
1356 ; CHECK-PWR7-NEXT: vperm v2, v5, v2, v4
1357 ; CHECK-PWR7-NEXT: vperm v3, v5, v3, v4
1358 ; CHECK-PWR7-NEXT: vsubuwm v2, v2, v3
1359 ; CHECK-PWR7-NEXT: vsubuwm v3, v5, v2
1360 ; CHECK-PWR7-NEXT: vmaxsw v2, v2, v3
1361 ; CHECK-PWR7-NEXT: blr
1362 %3 = zext <4 x i16> %0 to <4 x i32>
1363 %4 = zext <4 x i16> %1 to <4 x i32>
1364 %5 = sub <4 x i32> %3, %4
1365 %6 = sub <4 x i32> zeroinitializer, %5
1366 %7 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> %6)
1367 ret <4 x i32> %7
1368 }
1370 define <8 x i16> @zext_sub_absd16(<8 x i8>, <8 x i8>) local_unnamed_addr {
1371 ; CHECK-PWR9-LE-LABEL: zext_sub_absd16:
1372 ; CHECK-PWR9-LE: # %bb.0:
1373 ; CHECK-PWR9-LE-NEXT: xxlxor v4, v4, v4
1374 ; CHECK-PWR9-LE-NEXT: vmrglb v2, v4, v2
1375 ; CHECK-PWR9-LE-NEXT: vmrglb v3, v4, v3
1376 ; CHECK-PWR9-LE-NEXT: vabsduh v2, v2, v3
1377 ; CHECK-PWR9-LE-NEXT: blr
1378 ;
1379 ; CHECK-PWR9-BE-LABEL: zext_sub_absd16:
1380 ; CHECK-PWR9-BE: # %bb.0:
1381 ; CHECK-PWR9-BE-NEXT: xxlxor v4, v4, v4
1382 ; CHECK-PWR9-BE-NEXT: vmrghb v2, v4, v2
1383 ; CHECK-PWR9-BE-NEXT: vmrghb v3, v4, v3
1384 ; CHECK-PWR9-BE-NEXT: vabsduh v2, v2, v3
1385 ; CHECK-PWR9-BE-NEXT: blr
1386 ;
1387 ; CHECK-PWR8-LABEL: zext_sub_absd16:
1388 ; CHECK-PWR8: # %bb.0:
1389 ; CHECK-PWR8-NEXT: xxlxor v4, v4, v4
1390 ; CHECK-PWR8-NEXT: vmrglb v2, v4, v2
1391 ; CHECK-PWR8-NEXT: vmrglb v3, v4, v3
1392 ; CHECK-PWR8-NEXT: vsubuhm v2, v2, v3
1393 ; CHECK-PWR8-NEXT: vsubuhm v3, v4, v2
1394 ; CHECK-PWR8-NEXT: vmaxsh v2, v2, v3
1395 ; CHECK-PWR8-NEXT: blr
1396 ;
1397 ; CHECK-PWR7-LABEL: zext_sub_absd16:
1398 ; CHECK-PWR7: # %bb.0:
1399 ; CHECK-PWR7-NEXT: addis r3, r2, .LCPI14_0@toc@ha
1400 ; CHECK-PWR7-NEXT: xxlxor v5, v5, v5
1401 ; CHECK-PWR7-NEXT: addi r3, r3, .LCPI14_0@toc@l
1402 ; CHECK-PWR7-NEXT: lxvw4x v4, 0, r3
1403 ; CHECK-PWR7-NEXT: vperm v2, v5, v2, v4
1404 ; CHECK-PWR7-NEXT: vperm v3, v5, v3, v4
1405 ; CHECK-PWR7-NEXT: vsubuhm v2, v2, v3
1406 ; CHECK-PWR7-NEXT: vsubuhm v3, v5, v2
1407 ; CHECK-PWR7-NEXT: vmaxsh v2, v2, v3
1408 ; CHECK-PWR7-NEXT: blr
1409 %3 = zext <8 x i8> %0 to <8 x i16>
1410 %4 = zext <8 x i8> %1 to <8 x i16>
1411 %5 = sub <8 x i16> %3, %4
1412 %6 = sub <8 x i16> zeroinitializer, %5
1413 %7 = tail call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %5, <8 x i16> %6)
1414 ret <8 x i16> %7
1415 }
1417 define <16 x i8> @zext_sub_absd8(<16 x i4>, <16 x i4>) local_unnamed_addr {
1418 ; CHECK-PWR9-LABEL: zext_sub_absd8:
1419 ; CHECK-PWR9: # %bb.0:
1420 ; CHECK-PWR9-NEXT: xxspltib vs0, 15
1421 ; CHECK-PWR9-NEXT: xxland v2, v2, vs0
1422 ; CHECK-PWR9-NEXT: xxland v3, v3, vs0
1423 ; CHECK-PWR9-NEXT: vabsdub v2, v2, v3
1424 ; CHECK-PWR9-NEXT: blr
1425 ;
1426 ; CHECK-PWR78-LABEL: zext_sub_absd8:
1427 ; CHECK-PWR78: # %bb.0:
1428 ; CHECK-PWR78-NEXT: vspltisb v4, 15
1429 ; CHECK-PWR78-NEXT: xxland v2, v2, v4
1430 ; CHECK-PWR78-NEXT: xxland v3, v3, v4
1431 ; CHECK-PWR78-NEXT: vsububm v2, v2, v3
1432 ; CHECK-PWR78-NEXT: xxlxor v3, v3, v3
1433 ; CHECK-PWR78-NEXT: vsububm v3, v3, v2
1434 ; CHECK-PWR78-NEXT: vmaxsb v2, v2, v3
1435 ; CHECK-PWR78-NEXT: blr
1436 %3 = zext <16 x i4> %0 to <16 x i8>
1437 %4 = zext <16 x i4> %1 to <16 x i8>
1438 %5 = sub <16 x i8> %3, %4
1439 %6 = sub <16 x i8> zeroinitializer, %5
1440 %7 = tail call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %5, <16 x i8> %6)
1441 ret <16 x i8> %7
1442 }
1444 define <4 x i32> @sext_sub_absd32(<4 x i16>, <4 x i16>) local_unnamed_addr {
1445 ; CHECK-PWR9-LE-LABEL: sext_sub_absd32:
1446 ; CHECK-PWR9-LE: # %bb.0:
1447 ; CHECK-PWR9-LE-NEXT: vmrglh v2, v2, v2
1448 ; CHECK-PWR9-LE-NEXT: vmrglh v3, v3, v3
1449 ; CHECK-PWR9-LE-NEXT: vextsh2w v2, v2
1450 ; CHECK-PWR9-LE-NEXT: vextsh2w v3, v3
1451 ; CHECK-PWR9-LE-NEXT: xvnegsp v3, v3
1452 ; CHECK-PWR9-LE-NEXT: xvnegsp v2, v2
1453 ; CHECK-PWR9-LE-NEXT: vabsduw v2, v2, v3
1454 ; CHECK-PWR9-LE-NEXT: blr
1455 ;
1456 ; CHECK-PWR9-BE-LABEL: sext_sub_absd32:
1457 ; CHECK-PWR9-BE: # %bb.0:
1458 ; CHECK-PWR9-BE-NEXT: vmrghh v2, v2, v2
1459 ; CHECK-PWR9-BE-NEXT: vmrghh v3, v3, v3
1460 ; CHECK-PWR9-BE-NEXT: vextsh2w v2, v2
1461 ; CHECK-PWR9-BE-NEXT: vextsh2w v3, v3
1462 ; CHECK-PWR9-BE-NEXT: xvnegsp v3, v3
1463 ; CHECK-PWR9-BE-NEXT: xvnegsp v2, v2
1464 ; CHECK-PWR9-BE-NEXT: vabsduw v2, v2, v3
1465 ; CHECK-PWR9-BE-NEXT: blr
1466 ;
1467 ; CHECK-PWR8-LABEL: sext_sub_absd32:
1468 ; CHECK-PWR8: # %bb.0:
1469 ; CHECK-PWR8-NEXT: vspltisw v4, 8
1470 ; CHECK-PWR8-NEXT: vmrglh v2, v2, v2
1471 ; CHECK-PWR8-NEXT: vadduwm v4, v4, v4
1472 ; CHECK-PWR8-NEXT: vmrglh v3, v3, v3
1473 ; CHECK-PWR8-NEXT: vslw v2, v2, v4
1474 ; CHECK-PWR8-NEXT: vslw v3, v3, v4
1475 ; CHECK-PWR8-NEXT: vsraw v2, v2, v4
1476 ; CHECK-PWR8-NEXT: vsraw v3, v3, v4
1477 ; CHECK-PWR8-NEXT: vsubuwm v2, v2, v3
1478 ; CHECK-PWR8-NEXT: xxlxor v3, v3, v3
1479 ; CHECK-PWR8-NEXT: vsubuwm v3, v3, v2
1480 ; CHECK-PWR8-NEXT: vmaxsw v2, v2, v3
1481 ; CHECK-PWR8-NEXT: blr
1482 ;
1483 ; CHECK-PWR7-LABEL: sext_sub_absd32:
1484 ; CHECK-PWR7: # %bb.0:
1485 ; CHECK-PWR7-NEXT: vmrghh v2, v2, v2
1486 ; CHECK-PWR7-NEXT: vmrghh v3, v3, v3
1487 ; CHECK-PWR7-NEXT: vspltisw v4, 8
1488 ; CHECK-PWR7-NEXT: vadduwm v4, v4, v4
1489 ; CHECK-PWR7-NEXT: vslw v2, v2, v4
1490 ; CHECK-PWR7-NEXT: vslw v3, v3, v4
1491 ; CHECK-PWR7-NEXT: vsraw v2, v2, v4
1492 ; CHECK-PWR7-NEXT: vsraw v3, v3, v4
1493 ; CHECK-PWR7-NEXT: vsubuwm v2, v2, v3
1494 ; CHECK-PWR7-NEXT: xxlxor v3, v3, v3
1495 ; CHECK-PWR7-NEXT: vsubuwm v3, v3, v2
1496 ; CHECK-PWR7-NEXT: vmaxsw v2, v2, v3
1497 ; CHECK-PWR7-NEXT: blr
1498 %3 = sext <4 x i16> %0 to <4 x i32>
1499 %4 = sext <4 x i16> %1 to <4 x i32>
1500 %5 = sub <4 x i32> %3, %4
1501 %6 = sub <4 x i32> zeroinitializer, %5
1502 %7 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> %6)
1503 ret <4 x i32> %7
1504 }
1506 define <8 x i16> @sext_sub_absd16(<8 x i8>, <8 x i8>) local_unnamed_addr {
1507 ; CHECK-PWR9-LE-LABEL: sext_sub_absd16:
1508 ; CHECK-PWR9-LE: # %bb.0:
1509 ; CHECK-PWR9-LE-NEXT: vmrglb v2, v2, v2
1510 ; CHECK-PWR9-LE-NEXT: vspltish v4, 8
1511 ; CHECK-PWR9-LE-NEXT: vmrglb v3, v3, v3
1512 ; CHECK-PWR9-LE-NEXT: vslh v2, v2, v4
1513 ; CHECK-PWR9-LE-NEXT: vslh v3, v3, v4
1514 ; CHECK-PWR9-LE-NEXT: vsrah v2, v2, v4
1515 ; CHECK-PWR9-LE-NEXT: vsrah v3, v3, v4
1516 ; CHECK-PWR9-LE-NEXT: vsubuhm v2, v2, v3
1517 ; CHECK-PWR9-LE-NEXT: xxlxor v3, v3, v3
1518 ; CHECK-PWR9-LE-NEXT: vsubuhm v3, v3, v2
1519 ; CHECK-PWR9-LE-NEXT: vmaxsh v2, v2, v3
1520 ; CHECK-PWR9-LE-NEXT: blr
1521 ;
1522 ; CHECK-PWR9-BE-LABEL: sext_sub_absd16:
1523 ; CHECK-PWR9-BE: # %bb.0:
1524 ; CHECK-PWR9-BE-NEXT: vmrghb v2, v2, v2
1525 ; CHECK-PWR9-BE-NEXT: vspltish v4, 8
1526 ; CHECK-PWR9-BE-NEXT: vmrghb v3, v3, v3
1527 ; CHECK-PWR9-BE-NEXT: vslh v2, v2, v4
1528 ; CHECK-PWR9-BE-NEXT: vslh v3, v3, v4
1529 ; CHECK-PWR9-BE-NEXT: vsrah v2, v2, v4
1530 ; CHECK-PWR9-BE-NEXT: vsrah v3, v3, v4
1531 ; CHECK-PWR9-BE-NEXT: vsubuhm v2, v2, v3
1532 ; CHECK-PWR9-BE-NEXT: xxlxor v3, v3, v3
1533 ; CHECK-PWR9-BE-NEXT: vsubuhm v3, v3, v2
1534 ; CHECK-PWR9-BE-NEXT: vmaxsh v2, v2, v3
1535 ; CHECK-PWR9-BE-NEXT: blr
1536 ;
1537 ; CHECK-PWR8-LABEL: sext_sub_absd16:
1538 ; CHECK-PWR8: # %bb.0:
1539 ; CHECK-PWR8-NEXT: vmrglb v2, v2, v2
1540 ; CHECK-PWR8-NEXT: vspltish v4, 8
1541 ; CHECK-PWR8-NEXT: vslh v2, v2, v4
1542 ; CHECK-PWR8-NEXT: vmrglb v3, v3, v3
1543 ; CHECK-PWR8-NEXT: vslh v3, v3, v4
1544 ; CHECK-PWR8-NEXT: vsrah v2, v2, v4
1545 ; CHECK-PWR8-NEXT: vsrah v3, v3, v4
1546 ; CHECK-PWR8-NEXT: vsubuhm v2, v2, v3
1547 ; CHECK-PWR8-NEXT: xxlxor v3, v3, v3
1548 ; CHECK-PWR8-NEXT: vsubuhm v3, v3, v2
1549 ; CHECK-PWR8-NEXT: vmaxsh v2, v2, v3
1550 ; CHECK-PWR8-NEXT: blr
1551 ;
1552 ; CHECK-PWR7-LABEL: sext_sub_absd16:
1553 ; CHECK-PWR7: # %bb.0:
1554 ; CHECK-PWR7-NEXT: vmrghb v2, v2, v2
1555 ; CHECK-PWR7-NEXT: vmrghb v3, v3, v3
1556 ; CHECK-PWR7-NEXT: vspltish v4, 8
1557 ; CHECK-PWR7-NEXT: vslh v2, v2, v4
1558 ; CHECK-PWR7-NEXT: vslh v3, v3, v4
1559 ; CHECK-PWR7-NEXT: vsrah v2, v2, v4
1560 ; CHECK-PWR7-NEXT: vsrah v3, v3, v4
1561 ; CHECK-PWR7-NEXT: vsubuhm v2, v2, v3
1562 ; CHECK-PWR7-NEXT: xxlxor v3, v3, v3
1563 ; CHECK-PWR7-NEXT: vsubuhm v3, v3, v2
1564 ; CHECK-PWR7-NEXT: vmaxsh v2, v2, v3
1565 ; CHECK-PWR7-NEXT: blr
1566 %3 = sext <8 x i8> %0 to <8 x i16>
1567 %4 = sext <8 x i8> %1 to <8 x i16>
1568 %5 = sub <8 x i16> %3, %4
1569 %6 = sub <8 x i16> zeroinitializer, %5
1570 %7 = tail call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %5, <8 x i16> %6)
1571 ret <8 x i16> %7
1572 }
1574 define <16 x i8> @sext_sub_absd8(<16 x i4>, <16 x i4>) local_unnamed_addr {
1575 ; CHECK-PWR9-LABEL: sext_sub_absd8:
1576 ; CHECK-PWR9: # %bb.0:
1577 ; CHECK-PWR9-NEXT: xxspltib v4, 4
1578 ; CHECK-PWR9-NEXT: vslb v2, v2, v4
1579 ; CHECK-PWR9-NEXT: vslb v3, v3, v4
1580 ; CHECK-PWR9-NEXT: vsrab v2, v2, v4
1581 ; CHECK-PWR9-NEXT: vsrab v3, v3, v4
1582 ; CHECK-PWR9-NEXT: vsububm v2, v2, v3
1583 ; CHECK-PWR9-NEXT: xxlxor v3, v3, v3
1584 ; CHECK-PWR9-NEXT: vsububm v3, v3, v2
1585 ; CHECK-PWR9-NEXT: vmaxsb v2, v2, v3
1586 ; CHECK-PWR9-NEXT: blr
1587 ;
1588 ; CHECK-PWR78-LABEL: sext_sub_absd8:
1589 ; CHECK-PWR78: # %bb.0:
1590 ; CHECK-PWR78-NEXT: vspltisb v4, 4
1591 ; CHECK-PWR78-NEXT: vslb v2, v2, v4
1592 ; CHECK-PWR78-NEXT: vslb v3, v3, v4
1593 ; CHECK-PWR78-NEXT: vsrab v2, v2, v4
1594 ; CHECK-PWR78-NEXT: vsrab v3, v3, v4
1595 ; CHECK-PWR78-NEXT: vsububm v2, v2, v3
1596 ; CHECK-PWR78-NEXT: xxlxor v3, v3, v3
1597 ; CHECK-PWR78-NEXT: vsububm v3, v3, v2
1598 ; CHECK-PWR78-NEXT: vmaxsb v2, v2, v3
1599 ; CHECK-PWR78-NEXT: blr
1600 %3 = sext <16 x i4> %0 to <16 x i8>
1601 %4 = sext <16 x i4> %1 to <16 x i8>
1602 %5 = sub <16 x i8> %3, %4
1603 %6 = sub <16 x i8> zeroinitializer, %5
1604 %7 = tail call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %5, <16 x i8> %6)
1605 ret <16 x i8> %7
1606 }
1608 ; To verify vabsdu* exploitation for ucmp + sub + select sequence
1610 define <4 x i32> @absd_int32_ugt(<4 x i32>, <4 x i32>) {
1611 ; CHECK-PWR9-LABEL: absd_int32_ugt:
1612 ; CHECK-PWR9: # %bb.0:
1613 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1614 ; CHECK-PWR9-NEXT: blr
1615 ;
1616 ; CHECK-PWR78-LABEL: absd_int32_ugt:
1617 ; CHECK-PWR78: # %bb.0:
1618 ; CHECK-PWR78-NEXT: vcmpgtuw v4, v2, v3
1619 ; CHECK-PWR78-NEXT: vsubuwm v5, v2, v3
1620 ; CHECK-PWR78-NEXT: vsubuwm v2, v3, v2
1621 ; CHECK-PWR78-NEXT: xxsel v2, v2, v5, v4
1622 ; CHECK-PWR78-NEXT: blr
1623 %3 = icmp ugt <4 x i32> %0, %1
1624 %4 = sub <4 x i32> %0, %1
1625 %5 = sub <4 x i32> %1, %0
1626 %6 = select <4 x i1> %3, <4 x i32> %4, <4 x i32> %5
1627 ret <4 x i32> %6
1628 }
1630 define <4 x i32> @absd_int32_uge(<4 x i32>, <4 x i32>) {
1631 ; CHECK-PWR9-LABEL: absd_int32_uge:
1632 ; CHECK-PWR9: # %bb.0:
1633 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1634 ; CHECK-PWR9-NEXT: blr
1635 ;
1636 ; CHECK-PWR78-LABEL: absd_int32_uge:
1637 ; CHECK-PWR78: # %bb.0:
1638 ; CHECK-PWR78-NEXT: vcmpgtuw v4, v3, v2
1639 ; CHECK-PWR78-NEXT: xxlnor vs0, v4, v4
1640 ; CHECK-PWR78-NEXT: vsubuwm v4, v2, v3
1641 ; CHECK-PWR78-NEXT: vsubuwm v2, v3, v2
1642 ; CHECK-PWR78-NEXT: xxsel v2, v2, v4, vs0
1643 ; CHECK-PWR78-NEXT: blr
1644 %3 = icmp uge <4 x i32> %0, %1
1645 %4 = sub <4 x i32> %0, %1
1646 %5 = sub <4 x i32> %1, %0
1647 %6 = select <4 x i1> %3, <4 x i32> %4, <4 x i32> %5
1648 ret <4 x i32> %6
1649 }
1651 define <4 x i32> @absd_int32_ult(<4 x i32>, <4 x i32>) {
1652 ; CHECK-PWR9-LABEL: absd_int32_ult:
1653 ; CHECK-PWR9: # %bb.0:
1654 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1655 ; CHECK-PWR9-NEXT: blr
1656 ;
1657 ; CHECK-PWR78-LABEL: absd_int32_ult:
1658 ; CHECK-PWR78: # %bb.0:
1659 ; CHECK-PWR78-NEXT: vcmpgtuw v4, v3, v2
1660 ; CHECK-PWR78-NEXT: vsubuwm v5, v2, v3
1661 ; CHECK-PWR78-NEXT: vsubuwm v2, v3, v2
1662 ; CHECK-PWR78-NEXT: xxsel v2, v5, v2, v4
1663 ; CHECK-PWR78-NEXT: blr
1664 %3 = icmp ult <4 x i32> %0, %1
1665 %4 = sub <4 x i32> %0, %1
1666 %5 = sub <4 x i32> %1, %0
1667 %6 = select <4 x i1> %3, <4 x i32> %5, <4 x i32> %4
1668 ret <4 x i32> %6
1669 }
1671 define <4 x i32> @absd_int32_ule(<4 x i32>, <4 x i32>) {
1672 ; CHECK-PWR9-LABEL: absd_int32_ule:
1673 ; CHECK-PWR9: # %bb.0:
1674 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1675 ; CHECK-PWR9-NEXT: blr
1676 ;
1677 ; CHECK-PWR78-LABEL: absd_int32_ule:
1678 ; CHECK-PWR78: # %bb.0:
1679 ; CHECK-PWR78-NEXT: vcmpgtuw v4, v2, v3
1680 ; CHECK-PWR78-NEXT: xxlnor vs0, v4, v4
1681 ; CHECK-PWR78-NEXT: vsubuwm v4, v2, v3
1682 ; CHECK-PWR78-NEXT: vsubuwm v2, v3, v2
1683 ; CHECK-PWR78-NEXT: xxsel v2, v4, v2, vs0
1684 ; CHECK-PWR78-NEXT: blr
1685 %3 = icmp ule <4 x i32> %0, %1
1686 %4 = sub <4 x i32> %0, %1
1687 %5 = sub <4 x i32> %1, %0
1688 %6 = select <4 x i1> %3, <4 x i32> %5, <4 x i32> %4
1689 ret <4 x i32> %6
1690 }
1692 define <8 x i16> @absd_int16_ugt(<8 x i16>, <8 x i16>) {
1693 ; CHECK-PWR9-LABEL: absd_int16_ugt:
1694 ; CHECK-PWR9: # %bb.0:
1695 ; CHECK-PWR9-NEXT: vabsduh v2, v2, v3
1696 ; CHECK-PWR9-NEXT: blr
1697 ;
1698 ; CHECK-PWR78-LABEL: absd_int16_ugt:
1699 ; CHECK-PWR78: # %bb.0:
1700 ; CHECK-PWR78-NEXT: vcmpgtuh v4, v2, v3
1701 ; CHECK-PWR78-NEXT: vsubuhm v5, v2, v3
1702 ; CHECK-PWR78-NEXT: vsubuhm v2, v3, v2
1703 ; CHECK-PWR78-NEXT: xxsel v2, v2, v5, v4
1704 ; CHECK-PWR78-NEXT: blr
1705 %3 = icmp ugt <8 x i16> %0, %1
1706 %4 = sub <8 x i16> %0, %1
1707 %5 = sub <8 x i16> %1, %0
1708 %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5
1709 ret <8 x i16> %6
1710 }
1712 define <8 x i16> @absd_int16_uge(<8 x i16>, <8 x i16>) {
1713 ; CHECK-PWR9-LABEL: absd_int16_uge:
1714 ; CHECK-PWR9: # %bb.0:
1715 ; CHECK-PWR9-NEXT: vabsduh v2, v2, v3
1716 ; CHECK-PWR9-NEXT: blr
1717 ;
1718 ; CHECK-PWR78-LABEL: absd_int16_uge:
1719 ; CHECK-PWR78: # %bb.0:
1720 ; CHECK-PWR78-NEXT: vcmpgtuh v4, v3, v2
1721 ; CHECK-PWR78-NEXT: vsubuhm v5, v2, v3
1722 ; CHECK-PWR78-NEXT: vsubuhm v2, v3, v2
1723 ; CHECK-PWR78-NEXT: xxlnor v4, v4, v4
1724 ; CHECK-PWR78-NEXT: xxsel v2, v2, v5, v4
1725 ; CHECK-PWR78-NEXT: blr
1726 %3 = icmp uge <8 x i16> %0, %1
1727 %4 = sub <8 x i16> %0, %1
1728 %5 = sub <8 x i16> %1, %0
1729 %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5
1730 ret <8 x i16> %6
1731 }
1733 define <8 x i16> @absd_int16_ult(<8 x i16>, <8 x i16>) {
1734 ; CHECK-PWR9-LABEL: absd_int16_ult:
1735 ; CHECK-PWR9: # %bb.0:
1736 ; CHECK-PWR9-NEXT: vabsduh v2, v2, v3
1737 ; CHECK-PWR9-NEXT: blr
1738 ;
1739 ; CHECK-PWR78-LABEL: absd_int16_ult:
1740 ; CHECK-PWR78: # %bb.0:
1741 ; CHECK-PWR78-NEXT: vcmpgtuh v4, v3, v2
1742 ; CHECK-PWR78-NEXT: vsubuhm v5, v2, v3
1743 ; CHECK-PWR78-NEXT: vsubuhm v2, v3, v2
1744 ; CHECK-PWR78-NEXT: xxsel v2, v5, v2, v4
1745 ; CHECK-PWR78-NEXT: blr
1746 %3 = icmp ult <8 x i16> %0, %1
1747 %4 = sub <8 x i16> %0, %1
1748 %5 = sub <8 x i16> %1, %0
1749 %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4
1750 ret <8 x i16> %6
1751 }
1753 define <8 x i16> @absd_int16_ule(<8 x i16>, <8 x i16>) {
1754 ; CHECK-PWR9-LABEL: absd_int16_ule:
1755 ; CHECK-PWR9: # %bb.0:
1756 ; CHECK-PWR9-NEXT: vabsduh v2, v2, v3
1757 ; CHECK-PWR9-NEXT: blr
1758 ;
1759 ; CHECK-PWR78-LABEL: absd_int16_ule:
1760 ; CHECK-PWR78: # %bb.0:
1761 ; CHECK-PWR78-NEXT: vcmpgtuh v4, v2, v3
1762 ; CHECK-PWR78-NEXT: vsubuhm v5, v2, v3
1763 ; CHECK-PWR78-NEXT: vsubuhm v2, v3, v2
1764 ; CHECK-PWR78-NEXT: xxlnor v4, v4, v4
1765 ; CHECK-PWR78-NEXT: xxsel v2, v5, v2, v4
1766 ; CHECK-PWR78-NEXT: blr
1767 %3 = icmp ule <8 x i16> %0, %1
1768 %4 = sub <8 x i16> %0, %1
1769 %5 = sub <8 x i16> %1, %0
1770 %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4
1771 ret <8 x i16> %6
1772 }
1774 define <16 x i8> @absd_int8_ugt(<16 x i8>, <16 x i8>) {
1775 ; CHECK-PWR9-LABEL: absd_int8_ugt:
1776 ; CHECK-PWR9: # %bb.0:
1777 ; CHECK-PWR9-NEXT: vabsdub v2, v2, v3
1778 ; CHECK-PWR9-NEXT: blr
1779 ;
1780 ; CHECK-PWR78-LABEL: absd_int8_ugt:
1781 ; CHECK-PWR78: # %bb.0:
1782 ; CHECK-PWR78-NEXT: vcmpgtub v4, v2, v3
1783 ; CHECK-PWR78-NEXT: vsububm v5, v2, v3
1784 ; CHECK-PWR78-NEXT: vsububm v2, v3, v2
1785 ; CHECK-PWR78-NEXT: xxsel v2, v2, v5, v4
1786 ; CHECK-PWR78-NEXT: blr
1787 %3 = icmp ugt <16 x i8> %0, %1
1788 %4 = sub <16 x i8> %0, %1
1789 %5 = sub <16 x i8> %1, %0
1790 %6 = select <16 x i1> %3, <16 x i8> %4, <16 x i8> %5
1791 ret <16 x i8> %6
1792 }
1794 define <16 x i8> @absd_int8_uge(<16 x i8>, <16 x i8>) {
1795 ; CHECK-PWR9-LABEL: absd_int8_uge:
1796 ; CHECK-PWR9: # %bb.0:
1797 ; CHECK-PWR9-NEXT: vabsdub v2, v2, v3
1798 ; CHECK-PWR9-NEXT: blr
1799 ;
1800 ; CHECK-PWR78-LABEL: absd_int8_uge:
1801 ; CHECK-PWR78: # %bb.0:
1802 ; CHECK-PWR78-NEXT: vcmpgtub v4, v3, v2
1803 ; CHECK-PWR78-NEXT: vsububm v5, v2, v3
1804 ; CHECK-PWR78-NEXT: vsububm v2, v3, v2
1805 ; CHECK-PWR78-NEXT: xxlnor v4, v4, v4
1806 ; CHECK-PWR78-NEXT: xxsel v2, v2, v5, v4
1807 ; CHECK-PWR78-NEXT: blr
1808 %3 = icmp uge <16 x i8> %0, %1
1809 %4 = sub <16 x i8> %0, %1
1810 %5 = sub <16 x i8> %1, %0
1811 %6 = select <16 x i1> %3, <16 x i8> %4, <16 x i8> %5
1812 ret <16 x i8> %6
1813 }
1815 define <16 x i8> @absd_int8_ult(<16 x i8>, <16 x i8>) {
1816 ; CHECK-PWR9-LABEL: absd_int8_ult:
1817 ; CHECK-PWR9: # %bb.0:
1818 ; CHECK-PWR9-NEXT: vabsdub v2, v2, v3
1819 ; CHECK-PWR9-NEXT: blr
1820 ;
1821 ; CHECK-PWR78-LABEL: absd_int8_ult:
1822 ; CHECK-PWR78: # %bb.0:
1823 ; CHECK-PWR78-NEXT: vcmpgtub v4, v3, v2
1824 ; CHECK-PWR78-NEXT: vsububm v5, v2, v3
1825 ; CHECK-PWR78-NEXT: vsububm v2, v3, v2
1826 ; CHECK-PWR78-NEXT: xxsel v2, v5, v2, v4
1827 ; CHECK-PWR78-NEXT: blr
1828 %3 = icmp ult <16 x i8> %0, %1
1829 %4 = sub <16 x i8> %0, %1
1830 %5 = sub <16 x i8> %1, %0
1831 %6 = select <16 x i1> %3, <16 x i8> %5, <16 x i8> %4
1832 ret <16 x i8> %6
1833 }
1835 define <16 x i8> @absd_int8_ule(<16 x i8>, <16 x i8>) {
1836 ; CHECK-PWR9-LABEL: absd_int8_ule:
1837 ; CHECK-PWR9: # %bb.0:
1838 ; CHECK-PWR9-NEXT: vabsdub v2, v2, v3
1839 ; CHECK-PWR9-NEXT: blr
1840 ;
1841 ; CHECK-PWR78-LABEL: absd_int8_ule:
1842 ; CHECK-PWR78: # %bb.0:
1843 ; CHECK-PWR78-NEXT: vcmpgtub v4, v2, v3
1844 ; CHECK-PWR78-NEXT: vsububm v5, v2, v3
1845 ; CHECK-PWR78-NEXT: vsububm v2, v3, v2
1846 ; CHECK-PWR78-NEXT: xxlnor v4, v4, v4
1847 ; CHECK-PWR78-NEXT: xxsel v2, v5, v2, v4
1848 ; CHECK-PWR78-NEXT: blr
1849 %3 = icmp ule <16 x i8> %0, %1
1850 %4 = sub <16 x i8> %0, %1
1851 %5 = sub <16 x i8> %1, %0
1852 %6 = select <16 x i1> %3, <16 x i8> %5, <16 x i8> %4
1853 ret <16 x i8> %6
1854 }
1856 ; Tests for ABDS icmp + sub + select sequence
1858 define <4 x i32> @absd_int32_sgt(<4 x i32>, <4 x i32>) {
1859 ; CHECK-PWR9-LABEL: absd_int32_sgt:
1860 ; CHECK-PWR9: # %bb.0:
1861 ; CHECK-PWR9-NEXT: xvnegsp v3, v3
1862 ; CHECK-PWR9-NEXT: xvnegsp v2, v2
1863 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1864 ; CHECK-PWR9-NEXT: blr
1865 ;
1866 ; CHECK-PWR78-LABEL: absd_int32_sgt:
1867 ; CHECK-PWR78: # %bb.0:
1868 ; CHECK-PWR78-NEXT: vcmpgtsw v4, v2, v3
1869 ; CHECK-PWR78-NEXT: vsubuwm v5, v2, v3
1870 ; CHECK-PWR78-NEXT: vsubuwm v2, v3, v2
1871 ; CHECK-PWR78-NEXT: xxsel v2, v2, v5, v4
1872 ; CHECK-PWR78-NEXT: blr
1873 %3 = icmp sgt <4 x i32> %0, %1
1874 %4 = sub <4 x i32> %0, %1
1875 %5 = sub <4 x i32> %1, %0
1876 %6 = select <4 x i1> %3, <4 x i32> %4, <4 x i32> %5
1877 ret <4 x i32> %6
1878 }
1880 define <4 x i32> @absd_int32_sge(<4 x i32>, <4 x i32>) {
1881 ; CHECK-PWR9-LABEL: absd_int32_sge:
1882 ; CHECK-PWR9: # %bb.0:
1883 ; CHECK-PWR9-NEXT: xvnegsp v3, v3
1884 ; CHECK-PWR9-NEXT: xvnegsp v2, v2
1885 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1886 ; CHECK-PWR9-NEXT: blr
1887 ;
1888 ; CHECK-PWR78-LABEL: absd_int32_sge:
1889 ; CHECK-PWR78: # %bb.0:
1890 ; CHECK-PWR78-NEXT: vcmpgtsw v4, v3, v2
1891 ; CHECK-PWR78-NEXT: xxlnor vs0, v4, v4
1892 ; CHECK-PWR78-NEXT: vsubuwm v4, v2, v3
1893 ; CHECK-PWR78-NEXT: vsubuwm v2, v3, v2
1894 ; CHECK-PWR78-NEXT: xxsel v2, v2, v4, vs0
1895 ; CHECK-PWR78-NEXT: blr
1896 %3 = icmp sge <4 x i32> %0, %1
1897 %4 = sub <4 x i32> %0, %1
1898 %5 = sub <4 x i32> %1, %0
1899 %6 = select <4 x i1> %3, <4 x i32> %4, <4 x i32> %5
1900 ret <4 x i32> %6
1901 }
1903 define <4 x i32> @absd_int32_slt(<4 x i32>, <4 x i32>) {
1904 ; CHECK-PWR9-LABEL: absd_int32_slt:
1905 ; CHECK-PWR9: # %bb.0:
1906 ; CHECK-PWR9-NEXT: xvnegsp v3, v3
1907 ; CHECK-PWR9-NEXT: xvnegsp v2, v2
1908 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1909 ; CHECK-PWR9-NEXT: blr
1910 ;
1911 ; CHECK-PWR78-LABEL: absd_int32_slt:
1912 ; CHECK-PWR78: # %bb.0:
1913 ; CHECK-PWR78-NEXT: vcmpgtsw v4, v3, v2
1914 ; CHECK-PWR78-NEXT: vsubuwm v5, v2, v3
1915 ; CHECK-PWR78-NEXT: vsubuwm v2, v3, v2
1916 ; CHECK-PWR78-NEXT: xxsel v2, v5, v2, v4
1917 ; CHECK-PWR78-NEXT: blr
1918 %3 = icmp slt <4 x i32> %0, %1
1919 %4 = sub <4 x i32> %0, %1
1920 %5 = sub <4 x i32> %1, %0
1921 %6 = select <4 x i1> %3, <4 x i32> %5, <4 x i32> %4
1922 ret <4 x i32> %6
1923 }
1925 define <4 x i32> @absd_int32_sle(<4 x i32>, <4 x i32>) {
1926 ; CHECK-PWR9-LABEL: absd_int32_sle:
1927 ; CHECK-PWR9: # %bb.0:
1928 ; CHECK-PWR9-NEXT: xvnegsp v3, v3
1929 ; CHECK-PWR9-NEXT: xvnegsp v2, v2
1930 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1931 ; CHECK-PWR9-NEXT: blr
1932 ;
1933 ; CHECK-PWR78-LABEL: absd_int32_sle:
1934 ; CHECK-PWR78: # %bb.0:
1935 ; CHECK-PWR78-NEXT: vcmpgtsw v4, v2, v3
1936 ; CHECK-PWR78-NEXT: xxlnor vs0, v4, v4
1937 ; CHECK-PWR78-NEXT: vsubuwm v4, v2, v3
1938 ; CHECK-PWR78-NEXT: vsubuwm v2, v3, v2
1939 ; CHECK-PWR78-NEXT: xxsel v2, v4, v2, vs0
1940 ; CHECK-PWR78-NEXT: blr
1941 %3 = icmp sle <4 x i32> %0, %1
1942 %4 = sub <4 x i32> %0, %1
1943 %5 = sub <4 x i32> %1, %0
1944 %6 = select <4 x i1> %3, <4 x i32> %5, <4 x i32> %4
1945 ret <4 x i32> %6
1946 }
1948 define <8 x i16> @absd_int16_sgt(<8 x i16>, <8 x i16>) {
1949 ; CHECK-LABEL: absd_int16_sgt:
1950 ; CHECK: # %bb.0:
1951 ; CHECK-NEXT: vcmpgtsh v4, v2, v3
1952 ; CHECK-NEXT: vsubuhm v5, v2, v3
1953 ; CHECK-NEXT: vsubuhm v2, v3, v2
1954 ; CHECK-NEXT: xxsel v2, v2, v5, v4
1955 ; CHECK-NEXT: blr
1956 %3 = icmp sgt <8 x i16> %0, %1
1957 %4 = sub <8 x i16> %0, %1
1958 %5 = sub <8 x i16> %1, %0
1959 %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5
1960 ret <8 x i16> %6
1961 }
1963 define <8 x i16> @absd_int16_sge(<8 x i16>, <8 x i16>) {
1964 ; CHECK-LABEL: absd_int16_sge:
1965 ; CHECK: # %bb.0:
1966 ; CHECK-NEXT: vcmpgtsh v4, v3, v2
1967 ; CHECK-NEXT: vsubuhm v5, v2, v3
1968 ; CHECK-NEXT: vsubuhm v2, v3, v2
1969 ; CHECK-NEXT: xxlnor v4, v4, v4
1970 ; CHECK-NEXT: xxsel v2, v2, v5, v4
1971 ; CHECK-NEXT: blr
1972 %3 = icmp sge <8 x i16> %0, %1
1973 %4 = sub <8 x i16> %0, %1
1974 %5 = sub <8 x i16> %1, %0
1975 %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5
1976 ret <8 x i16> %6
1977 }
1979 define <8 x i16> @absd_int16_slt(<8 x i16>, <8 x i16>) {
1980 ; CHECK-LABEL: absd_int16_slt:
1981 ; CHECK: # %bb.0:
1982 ; CHECK-NEXT: vcmpgtsh v4, v3, v2
1983 ; CHECK-NEXT: vsubuhm v5, v2, v3
1984 ; CHECK-NEXT: vsubuhm v2, v3, v2
1985 ; CHECK-NEXT: xxsel v2, v5, v2, v4
1986 ; CHECK-NEXT: blr
1987 %3 = icmp slt <8 x i16> %0, %1
1988 %4 = sub <8 x i16> %0, %1
1989 %5 = sub <8 x i16> %1, %0
1990 %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4
1991 ret <8 x i16> %6
1992 }
1994 define <8 x i16> @absd_int16_sle(<8 x i16>, <8 x i16>) {
1995 ; CHECK-LABEL: absd_int16_sle:
1996 ; CHECK: # %bb.0:
1997 ; CHECK-NEXT: vcmpgtsh v4, v2, v3
1998 ; CHECK-NEXT: vsubuhm v5, v2, v3
1999 ; CHECK-NEXT: vsubuhm v2, v3, v2
2000 ; CHECK-NEXT: xxlnor v4, v4, v4
2001 ; CHECK-NEXT: xxsel v2, v5, v2, v4
2002 ; CHECK-NEXT: blr
2003 %3 = icmp sle <8 x i16> %0, %1
2004 %4 = sub <8 x i16> %0, %1
2005 %5 = sub <8 x i16> %1, %0
2006 %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4
2007 ret <8 x i16> %6
2008 }
2010 define <16 x i8> @absd_int8_sgt(<16 x i8>, <16 x i8>) {
2011 ; CHECK-LABEL: absd_int8_sgt:
2012 ; CHECK: # %bb.0:
2013 ; CHECK-NEXT: vcmpgtsb v4, v2, v3
2014 ; CHECK-NEXT: vsububm v5, v2, v3
2015 ; CHECK-NEXT: vsububm v2, v3, v2
2016 ; CHECK-NEXT: xxsel v2, v2, v5, v4
2017 ; CHECK-NEXT: blr
2018 %3 = icmp sgt <16 x i8> %0, %1
2019 %4 = sub <16 x i8> %0, %1
2020 %5 = sub <16 x i8> %1, %0
2021 %6 = select <16 x i1> %3, <16 x i8> %4, <16 x i8> %5
2022 ret <16 x i8> %6
2023 }
2025 define <16 x i8> @absd_int8_sge(<16 x i8>, <16 x i8>) {
2026 ; CHECK-LABEL: absd_int8_sge:
2027 ; CHECK: # %bb.0:
2028 ; CHECK-NEXT: vcmpgtsb v4, v3, v2
2029 ; CHECK-NEXT: vsububm v5, v2, v3
2030 ; CHECK-NEXT: vsububm v2, v3, v2
2031 ; CHECK-NEXT: xxlnor v4, v4, v4
2032 ; CHECK-NEXT: xxsel v2, v2, v5, v4
2033 ; CHECK-NEXT: blr
2034 %3 = icmp sge <16 x i8> %0, %1
2035 %4 = sub <16 x i8> %0, %1
2036 %5 = sub <16 x i8> %1, %0
2037 %6 = select <16 x i1> %3, <16 x i8> %4, <16 x i8> %5
2038 ret <16 x i8> %6
2039 }
2041 define <16 x i8> @absd_int8_slt(<16 x i8>, <16 x i8>) {
2042 ; CHECK-LABEL: absd_int8_slt:
2043 ; CHECK: # %bb.0:
2044 ; CHECK-NEXT: vcmpgtsb v4, v3, v2
2045 ; CHECK-NEXT: vsububm v5, v2, v3
2046 ; CHECK-NEXT: vsububm v2, v3, v2
2047 ; CHECK-NEXT: xxsel v2, v5, v2, v4
2048 ; CHECK-NEXT: blr
2049 %3 = icmp slt <16 x i8> %0, %1
2050 %4 = sub <16 x i8> %0, %1
2051 %5 = sub <16 x i8> %1, %0
2052 %6 = select <16 x i1> %3, <16 x i8> %5, <16 x i8> %4
2053 ret <16 x i8> %6
2054 }
2056 define <16 x i8> @absd_int8_sle(<16 x i8>, <16 x i8>) {
2057 ; CHECK-LABEL: absd_int8_sle:
2058 ; CHECK: # %bb.0:
2059 ; CHECK-NEXT: vcmpgtsb v4, v2, v3
2060 ; CHECK-NEXT: vsububm v5, v2, v3
2061 ; CHECK-NEXT: vsububm v2, v3, v2
2062 ; CHECK-NEXT: xxlnor v4, v4, v4
2063 ; CHECK-NEXT: xxsel v2, v5, v2, v4
2064 ; CHECK-NEXT: blr
2065 %3 = icmp sle <16 x i8> %0, %1
2066 %4 = sub <16 x i8> %0, %1
2067 %5 = sub <16 x i8> %1, %0
2068 %6 = select <16 x i1> %3, <16 x i8> %5, <16 x i8> %4
2069 ret <16 x i8> %6
2070 }
2072 ; some cases we are unable to optimize
2073 ; check whether goes beyond the scope
2074 define <4 x i32> @absd_int32_ugt_opp(<4 x i32>, <4 x i32>) {
2075 ; CHECK-LABEL: absd_int32_ugt_opp:
2076 ; CHECK: # %bb.0:
2077 ; CHECK-NEXT: vcmpgtuw v4, v2, v3
2078 ; CHECK-NEXT: vsubuwm v5, v2, v3
2079 ; CHECK-NEXT: vsubuwm v2, v3, v2
2080 ; CHECK-NEXT: xxsel v2, v5, v2, v4
2081 ; CHECK-NEXT: blr
2082 %3 = icmp ugt <4 x i32> %0, %1
2083 %4 = sub <4 x i32> %0, %1
2084 %5 = sub <4 x i32> %1, %0
2085 %6 = select <4 x i1> %3, <4 x i32> %5, <4 x i32> %4
2086 ret <4 x i32> %6
2087 }
2089 define <2 x i64> @absd_int64_ugt(<2 x i64>, <2 x i64>) {
2090 ; CHECK-PWR9-LABEL: absd_int64_ugt:
2091 ; CHECK-PWR9: # %bb.0:
2092 ; CHECK-PWR9-NEXT: vcmpgtud v4, v2, v3
2093 ; CHECK-PWR9-NEXT: vsubudm v5, v2, v3
2094 ; CHECK-PWR9-NEXT: vsubudm v2, v3, v2
2095 ; CHECK-PWR9-NEXT: xxsel v2, v2, v5, v4
2096 ; CHECK-PWR9-NEXT: blr
2097 ;
2098 ; CHECK-PWR8-LABEL: absd_int64_ugt:
2099 ; CHECK-PWR8: # %bb.0:
2100 ; CHECK-PWR8-NEXT: vcmpgtud v4, v2, v3
2101 ; CHECK-PWR8-NEXT: vsubudm v5, v2, v3
2102 ; CHECK-PWR8-NEXT: vsubudm v2, v3, v2
2103 ; CHECK-PWR8-NEXT: xxsel v2, v2, v5, v4
2104 ; CHECK-PWR8-NEXT: blr
2105 ;
2106 ; CHECK-PWR7-LABEL: absd_int64_ugt:
2107 ; CHECK-PWR7: # %bb.0:
2108 ; CHECK-PWR7-NEXT: addi r3, r1, -64
2109 ; CHECK-PWR7-NEXT: addi r4, r1, -80
2110 ; CHECK-PWR7-NEXT: li r5, 0
2111 ; CHECK-PWR7-NEXT: li r6, -1
2112 ; CHECK-PWR7-NEXT: stxvd2x v3, 0, r3
2113 ; CHECK-PWR7-NEXT: stxvd2x v2, 0, r4
2114 ; CHECK-PWR7-NEXT: ld r3, -56(r1)
2115 ; CHECK-PWR7-NEXT: ld r4, -72(r1)
2116 ; CHECK-PWR7-NEXT: ld r8, -80(r1)
2117 ; CHECK-PWR7-NEXT: cmpld r4, r3
2118 ; CHECK-PWR7-NEXT: sub r9, r4, r3
2119 ; CHECK-PWR7-NEXT: iselgt r7, r6, r5
2120 ; CHECK-PWR7-NEXT: sub r3, r3, r4
2121 ; CHECK-PWR7-NEXT: std r7, -8(r1)
2122 ; CHECK-PWR7-NEXT: ld r7, -64(r1)
2123 ; CHECK-PWR7-NEXT: cmpld r8, r7
2124 ; CHECK-PWR7-NEXT: iselgt r4, r6, r5
2125 ; CHECK-PWR7-NEXT: addi r5, r1, -16
2126 ; CHECK-PWR7-NEXT: std r4, -16(r1)
2127 ; CHECK-PWR7-NEXT: sub r4, r8, r7
2128 ; CHECK-PWR7-NEXT: lxvd2x v2, 0, r5
2129 ; CHECK-PWR7-NEXT: std r9, -40(r1)
2130 ; CHECK-PWR7-NEXT: addi r5, r1, -48
2131 ; CHECK-PWR7-NEXT: std r4, -48(r1)
2132 ; CHECK-PWR7-NEXT: sub r4, r7, r8
2133 ; CHECK-PWR7-NEXT: lxvd2x v3, 0, r5
2134 ; CHECK-PWR7-NEXT: std r3, -24(r1)
2135 ; CHECK-PWR7-NEXT: addi r3, r1, -32
2136 ; CHECK-PWR7-NEXT: std r4, -32(r1)
2137 ; CHECK-PWR7-NEXT: lxvd2x v4, 0, r3
2138 ; CHECK-PWR7-NEXT: xxsel v2, v4, v3, v2
2139 ; CHECK-PWR7-NEXT: blr
2140 %3 = icmp ugt <2 x i64> %0, %1
2141 %4 = sub <2 x i64> %0, %1
2142 %5 = sub <2 x i64> %1, %0
2143 %6 = select <2 x i1> %3, <2 x i64> %4, <2 x i64> %5
2144 ret <2 x i64> %6
2145 }
2147 declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>)
2149 declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>)
2151 declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>)