llvm/lib/CodeGen/TargetInstrInfo.cpp

   1 //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements the TargetInstrInfo class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "llvm/CodeGen/TargetInstrInfo.h"
  14 #include "llvm/ADT/StringExtras.h"
  15 #include "llvm/CodeGen/MachineFrameInfo.h"
  16 #include "llvm/CodeGen/MachineInstrBuilder.h"
  17 #include "llvm/CodeGen/MachineMemOperand.h"
  18 #include "llvm/CodeGen/MachineRegisterInfo.h"
  19 #include "llvm/CodeGen/MachineScheduler.h"
  20 #include "llvm/CodeGen/PseudoSourceValue.h"
  21 #include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
  22 #include "llvm/CodeGen/StackMaps.h"
  23 #include "llvm/CodeGen/TargetFrameLowering.h"
  24 #include "llvm/CodeGen/TargetLowering.h"
  25 #include "llvm/CodeGen/TargetRegisterInfo.h"
  26 #include "llvm/CodeGen/TargetSchedule.h"
  27 #include "llvm/IR/DataLayout.h"
  28 #include "llvm/IR/DebugInfoMetadata.h"
  29 #include "llvm/MC/MCAsmInfo.h"
  30 #include "llvm/MC/MCInstrItineraries.h"
  31 #include "llvm/Support/CommandLine.h"
  32 #include "llvm/Support/ErrorHandling.h"
  33 #include "llvm/Support/raw_ostream.h"
  34 #include "llvm/Target/TargetMachine.h"
  35 #include <cctype>
  36
  37 using namespace llvm;
  38
  39 static cl::opt<bool> DisableHazardRecognizer(
  40   "disable-sched-hazard", cl::Hidden, cl::init(false),
  41   cl::desc("Disable hazard detection during preRA scheduling"));
  42
  43 TargetInstrInfo::~TargetInstrInfo() {
  44 }
  45
  46 const TargetRegisterClass*
  47 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
  48                              const TargetRegisterInfo *TRI,
  49                              const MachineFunction &MF) const {
  50   if (OpNum >= MCID.getNumOperands())
  51     return nullptr;
  52
  53   short RegClass = MCID.OpInfo[OpNum].RegClass;
  54   if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
  55     return TRI->getPointerRegClass(MF, RegClass);
  56
  57   // Instructions like INSERT_SUBREG do not have fixed register classes.
  58   if (RegClass < 0)
  59     return nullptr;
  60
  61   // Otherwise just look it up normally.
  62   return TRI->getRegClass(RegClass);
  63 }
  64
  65 /// insertNoop - Insert a noop into the instruction stream at the specified
  66 /// point.
  67 void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB,
  68                                  MachineBasicBlock::iterator MI) const {
  69   llvm_unreachable("Target didn't implement insertNoop!");
  70 }
  71
  72 /// insertNoops - Insert noops into the instruction stream at the specified
  73 /// point.
  74 void TargetInstrInfo::insertNoops(MachineBasicBlock &MBB,
  75                                   MachineBasicBlock::iterator MI,
  76                                   unsigned Quantity) const {
  77   for (unsigned i = 0; i < Quantity; ++i)
  78     insertNoop(MBB, MI);
  79 }
  80
  81 static bool isAsmComment(const char *Str, const MCAsmInfo &MAI) {
  82   return strncmp(Str, MAI.getCommentString().data(),
  83                  MAI.getCommentString().size()) == 0;
  84 }
  85
  86 /// Measure the specified inline asm to determine an approximation of its
  87 /// length.
  88 /// Comments (which run till the next SeparatorString or newline) do not
  89 /// count as an instruction.
  90 /// Any other non-whitespace text is considered an instruction, with
  91 /// multiple instructions separated by SeparatorString or newlines.
  92 /// Variable-length instructions are not handled here; this function
  93 /// may be overloaded in the target code to do that.
  94 /// We implement a special case of the .space directive which takes only a
  95 /// single integer argument in base 10 that is the size in bytes. This is a
  96 /// restricted form of the GAS directive in that we only interpret
  97 /// simple--i.e. not a logical or arithmetic expression--size values without
  98 /// the optional fill value. This is primarily used for creating arbitrary
  99 /// sized inline asm blocks for testing purposes.
 100 unsigned TargetInstrInfo::getInlineAsmLength(
 101   const char *Str,
 102   const MCAsmInfo &MAI, const TargetSubtargetInfo *STI) const {
 103   // Count the number of instructions in the asm.
 104   bool AtInsnStart = true;
 105   unsigned Length = 0;
 106   const unsigned MaxInstLength = MAI.getMaxInstLength(STI);
 107   for (; *Str; ++Str) {
 108     if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
 109                                 strlen(MAI.getSeparatorString())) == 0) {
 110       AtInsnStart = true;
 111     } else if (isAsmComment(Str, MAI)) {
 112       // Stop counting as an instruction after a comment until the next
 113       // separator.
 114       AtInsnStart = false;
 115     }
 116
 117     if (AtInsnStart && !isSpace(static_cast<unsigned char>(*Str))) {
 118       unsigned AddLength = MaxInstLength;
 119       if (strncmp(Str, ".space", 6) == 0) {
 120         char *EStr;
 121         int SpaceSize;
 122         SpaceSize = strtol(Str + 6, &EStr, 10);
 123         SpaceSize = SpaceSize < 0 ? 0 : SpaceSize;
 124         while (*EStr != '\n' && isSpace(static_cast<unsigned char>(*EStr)))
 125           ++EStr;
 126         if (*EStr == '\0' || *EStr == '\n' ||
 127             isAsmComment(EStr, MAI)) // Successfully parsed .space argument
 128           AddLength = SpaceSize;
 129       }
 130       Length += AddLength;
 131       AtInsnStart = false;
 132     }
 133   }
 134
 135   return Length;
 136 }
 137
 138 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
 139 /// after it, replacing it with an unconditional branch to NewDest.
 140 void
 141 TargetInstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
 142                                          MachineBasicBlock *NewDest) const {
 143   MachineBasicBlock *MBB = Tail->getParent();
 144
 145   // Remove all the old successors of MBB from the CFG.
 146   while (!MBB->succ_empty())
 147     MBB->removeSuccessor(MBB->succ_begin());
 148
 149   // Save off the debug loc before erasing the instruction.
 150   DebugLoc DL = Tail->getDebugLoc();
 151
 152   // Update call site info and remove all the dead instructions
 153   // from the end of MBB.
 154   while (Tail != MBB->end()) {
 155     auto MI = Tail++;
 156     if (MI->shouldUpdateCallSiteInfo())
 157       MBB->getParent()->eraseCallSiteInfo(&*MI);
 158     MBB->erase(MI);
 159   }
 160
 161   // If MBB isn't immediately before MBB, insert a branch to it.
 162   if (++MachineFunction::iterator(MBB) != MachineFunction::iterator(NewDest))
 163     insertBranch(*MBB, NewDest, nullptr, SmallVector<MachineOperand, 0>(), DL);
 164   MBB->addSuccessor(NewDest);
 165 }
 166
 167 MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr &MI,
 168                                                       bool NewMI, unsigned Idx1,
 169                                                       unsigned Idx2) const {
 170   const MCInstrDesc &MCID = MI.getDesc();
 171   bool HasDef = MCID.getNumDefs();
 172   if (HasDef && !MI.getOperand(0).isReg())
 173     // No idea how to commute this instruction. Target should implement its own.
 174     return nullptr;
 175
 176   unsigned CommutableOpIdx1 = Idx1; (void)CommutableOpIdx1;
 177   unsigned CommutableOpIdx2 = Idx2; (void)CommutableOpIdx2;
 178   assert(findCommutedOpIndices(MI, CommutableOpIdx1, CommutableOpIdx2) &&
 179          CommutableOpIdx1 == Idx1 && CommutableOpIdx2 == Idx2 &&
 180          "TargetInstrInfo::CommuteInstructionImpl(): not commutable operands.");
 181   assert(MI.getOperand(Idx1).isReg() && MI.getOperand(Idx2).isReg() &&
 182          "This only knows how to commute register operands so far");
 183
 184   Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
 185   Register Reg1 = MI.getOperand(Idx1).getReg();
 186   Register Reg2 = MI.getOperand(Idx2).getReg();
 187   unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0;
 188   unsigned SubReg1 = MI.getOperand(Idx1).getSubReg();
 189   unsigned SubReg2 = MI.getOperand(Idx2).getSubReg();
 190   bool Reg1IsKill = MI.getOperand(Idx1).isKill();
 191   bool Reg2IsKill = MI.getOperand(Idx2).isKill();
 192   bool Reg1IsUndef = MI.getOperand(Idx1).isUndef();
 193   bool Reg2IsUndef = MI.getOperand(Idx2).isUndef();
 194   bool Reg1IsInternal = MI.getOperand(Idx1).isInternalRead();
 195   bool Reg2IsInternal = MI.getOperand(Idx2).isInternalRead();
 196   // Avoid calling isRenamable for virtual registers since we assert that
 197   // renamable property is only queried/set for physical registers.
 198   bool Reg1IsRenamable = Register::isPhysicalRegister(Reg1)
 199                              ? MI.getOperand(Idx1).isRenamable()
 200                              : false;
 201   bool Reg2IsRenamable = Register::isPhysicalRegister(Reg2)
 202                              ? MI.getOperand(Idx2).isRenamable()
 203                              : false;
 204   // If destination is tied to either of the commuted source register, then
 205   // it must be updated.
 206   if (HasDef && Reg0 == Reg1 &&
 207       MI.getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) {
 208     Reg2IsKill = false;
 209     Reg0 = Reg2;
 210     SubReg0 = SubReg2;
 211   } else if (HasDef && Reg0 == Reg2 &&
 212              MI.getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) {
 213     Reg1IsKill = false;
 214     Reg0 = Reg1;
 215     SubReg0 = SubReg1;
 216   }
 217
 218   MachineInstr *CommutedMI = nullptr;
 219   if (NewMI) {
 220     // Create a new instruction.
 221     MachineFunction &MF = *MI.getMF();
 222     CommutedMI = MF.CloneMachineInstr(&MI);
 223   } else {
 224     CommutedMI = &MI;
 225   }
 226
 227   if (HasDef) {
 228     CommutedMI->getOperand(0).setReg(Reg0);
 229     CommutedMI->getOperand(0).setSubReg(SubReg0);
 230   }
 231   CommutedMI->getOperand(Idx2).setReg(Reg1);
 232   CommutedMI->getOperand(Idx1).setReg(Reg2);
 233   CommutedMI->getOperand(Idx2).setSubReg(SubReg1);
 234   CommutedMI->getOperand(Idx1).setSubReg(SubReg2);
 235   CommutedMI->getOperand(Idx2).setIsKill(Reg1IsKill);
 236   CommutedMI->getOperand(Idx1).setIsKill(Reg2IsKill);
 237   CommutedMI->getOperand(Idx2).setIsUndef(Reg1IsUndef);
 238   CommutedMI->getOperand(Idx1).setIsUndef(Reg2IsUndef);
 239   CommutedMI->getOperand(Idx2).setIsInternalRead(Reg1IsInternal);
 240   CommutedMI->getOperand(Idx1).setIsInternalRead(Reg2IsInternal);
 241   // Avoid calling setIsRenamable for virtual registers since we assert that
 242   // renamable property is only queried/set for physical registers.
 243   if (Register::isPhysicalRegister(Reg1))
 244     CommutedMI->getOperand(Idx2).setIsRenamable(Reg1IsRenamable);
 245   if (Register::isPhysicalRegister(Reg2))
 246     CommutedMI->getOperand(Idx1).setIsRenamable(Reg2IsRenamable);
 247   return CommutedMI;
 248 }
 249
 250 MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr &MI, bool NewMI,
 251                                                   unsigned OpIdx1,
 252                                                   unsigned OpIdx2) const {
 253   // If OpIdx1 or OpIdx2 is not specified, then this method is free to choose
 254   // any commutable operand, which is done in findCommutedOpIndices() method
 255   // called below.
 256   if ((OpIdx1 == CommuteAnyOperandIndex || OpIdx2 == CommuteAnyOperandIndex) &&
 257       !findCommutedOpIndices(MI, OpIdx1, OpIdx2)) {
 258     assert(MI.isCommutable() &&
 259            "Precondition violation: MI must be commutable.");
 260     return nullptr;
 261   }
 262   return commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
 263 }
 264
 265 bool TargetInstrInfo::fixCommutedOpIndices(unsigned &ResultIdx1,
 266                                            unsigned &ResultIdx2,
 267                                            unsigned CommutableOpIdx1,
 268                                            unsigned CommutableOpIdx2) {
 269   if (ResultIdx1 == CommuteAnyOperandIndex &&
 270       ResultIdx2 == CommuteAnyOperandIndex) {
 271     ResultIdx1 = CommutableOpIdx1;
 272     ResultIdx2 = CommutableOpIdx2;
 273   } else if (ResultIdx1 == CommuteAnyOperandIndex) {
 274     if (ResultIdx2 == CommutableOpIdx1)
 275       ResultIdx1 = CommutableOpIdx2;
 276     else if (ResultIdx2 == CommutableOpIdx2)
 277       ResultIdx1 = CommutableOpIdx1;
 278     else
 279       return false;
 280   } else if (ResultIdx2 == CommuteAnyOperandIndex) {
 281     if (ResultIdx1 == CommutableOpIdx1)
 282       ResultIdx2 = CommutableOpIdx2;
 283     else if (ResultIdx1 == CommutableOpIdx2)
 284       ResultIdx2 = CommutableOpIdx1;
 285     else
 286       return false;
 287   } else
 288     // Check that the result operand indices match the given commutable
 289     // operand indices.
 290     return (ResultIdx1 == CommutableOpIdx1 && ResultIdx2 == CommutableOpIdx2) ||
 291            (ResultIdx1 == CommutableOpIdx2 && ResultIdx2 == CommutableOpIdx1);
 292
 293   return true;
 294 }
 295
 296 bool TargetInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
 297                                             unsigned &SrcOpIdx1,
 298                                             unsigned &SrcOpIdx2) const {
 299   assert(!MI.isBundle() &&
 300          "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
 301
 302   const MCInstrDesc &MCID = MI.getDesc();
 303   if (!MCID.isCommutable())
 304     return false;
 305
 306   // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
 307   // is not true, then the target must implement this.
 308   unsigned CommutableOpIdx1 = MCID.getNumDefs();
 309   unsigned CommutableOpIdx2 = CommutableOpIdx1 + 1;
 310   if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
 311                             CommutableOpIdx1, CommutableOpIdx2))
 312     return false;
 313
 314   if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
 315     // No idea.
 316     return false;
 317   return true;
 318 }
 319
 320 bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
 321   if (!MI.isTerminator()) return false;
 322
 323   // Conditional branch is a special case.
 324   if (MI.isBranch() && !MI.isBarrier())
 325     return true;
 326   if (!MI.isPredicable())
 327     return true;
 328   return !isPredicated(MI);
 329 }
 330
 331 bool TargetInstrInfo::PredicateInstruction(
 332     MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
 333   bool MadeChange = false;
 334
 335   assert(!MI.isBundle() &&
 336          "TargetInstrInfo::PredicateInstruction() can't handle bundles");
 337
 338   const MCInstrDesc &MCID = MI.getDesc();
 339   if (!MI.isPredicable())
 340     return false;
 341
 342   for (unsigned j = 0, i = 0, e = MI.getNumOperands(); i != e; ++i) {
 343     if (MCID.OpInfo[i].isPredicate()) {
 344       MachineOperand &MO = MI.getOperand(i);
 345       if (MO.isReg()) {
 346         MO.setReg(Pred[j].getReg());
 347         MadeChange = true;
 348       } else if (MO.isImm()) {
 349         MO.setImm(Pred[j].getImm());
 350         MadeChange = true;
 351       } else if (MO.isMBB()) {
 352         MO.setMBB(Pred[j].getMBB());
 353         MadeChange = true;
 354       }
 355       ++j;
 356     }
 357   }
 358   return MadeChange;
 359 }
 360
 361 bool TargetInstrInfo::hasLoadFromStackSlot(
 362     const MachineInstr &MI,
 363     SmallVectorImpl<const MachineMemOperand *> &Accesses) const {
 364   size_t StartSize = Accesses.size();
 365   for (MachineInstr::mmo_iterator o = MI.memoperands_begin(),
 366                                   oe = MI.memoperands_end();
 367        o != oe; ++o) {
 368     if ((*o)->isLoad() &&
 369         dyn_cast_or_null<FixedStackPseudoSourceValue>((*o)->getPseudoValue()))
 370       Accesses.push_back(*o);
 371   }
 372   return Accesses.size() != StartSize;
 373 }
 374
 375 bool TargetInstrInfo::hasStoreToStackSlot(
 376     const MachineInstr &MI,
 377     SmallVectorImpl<const MachineMemOperand *> &Accesses) const {
 378   size_t StartSize = Accesses.size();
 379   for (MachineInstr::mmo_iterator o = MI.memoperands_begin(),
 380                                   oe = MI.memoperands_end();
 381        o != oe; ++o) {
 382     if ((*o)->isStore() &&
 383         dyn_cast_or_null<FixedStackPseudoSourceValue>((*o)->getPseudoValue()))
 384       Accesses.push_back(*o);
 385   }
 386   return Accesses.size() != StartSize;
 387 }
 388
 389 bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC,
 390                                         unsigned SubIdx, unsigned &Size,
 391                                         unsigned &Offset,
 392                                         const MachineFunction &MF) const {
 393   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
 394   if (!SubIdx) {
 395     Size = TRI->getSpillSize(*RC);
 396     Offset = 0;
 397     return true;
 398   }
 399   unsigned BitSize = TRI->getSubRegIdxSize(SubIdx);
 400   // Convert bit size to byte size.
 401   if (BitSize % 8)
 402     return false;
 403
 404   int BitOffset = TRI->getSubRegIdxOffset(SubIdx);
 405   if (BitOffset < 0 || BitOffset % 8)
 406     return false;
 407
 408   Size = BitSize / 8;
 409   Offset = (unsigned)BitOffset / 8;
 410
 411   assert(TRI->getSpillSize(*RC) >= (Offset + Size) && "bad subregister range");
 412
 413   if (!MF.getDataLayout().isLittleEndian()) {
 414     Offset = TRI->getSpillSize(*RC) - (Offset + Size);
 415   }
 416   return true;
 417 }
 418
 419 void TargetInstrInfo::reMaterialize(MachineBasicBlock &MBB,
 420                                     MachineBasicBlock::iterator I,
 421                                     Register DestReg, unsigned SubIdx,
 422                                     const MachineInstr &Orig,
 423                                     const TargetRegisterInfo &TRI) const {
 424   MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
 425   MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
 426   MBB.insert(I, MI);
 427 }
 428
 429 bool TargetInstrInfo::produceSameValue(const MachineInstr &MI0,
 430                                        const MachineInstr &MI1,
 431                                        const MachineRegisterInfo *MRI) const {
 432   return MI0.isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
 433 }
 434
 435 MachineInstr &TargetInstrInfo::duplicate(MachineBasicBlock &MBB,
 436     MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const {
 437   assert(!Orig.isNotDuplicable() && "Instruction cannot be duplicated");
 438   MachineFunction &MF = *MBB.getParent();
 439   return MF.CloneMachineInstrBundle(MBB, InsertBefore, Orig);
 440 }
 441
 442 // If the COPY instruction in MI can be folded to a stack operation, return
 443 // the register class to use.
 444 static const TargetRegisterClass *canFoldCopy(const MachineInstr &MI,
 445                                               unsigned FoldIdx) {
 446   assert(MI.isCopy() && "MI must be a COPY instruction");
 447   if (MI.getNumOperands() != 2)
 448     return nullptr;
 449   assert(FoldIdx<2 && "FoldIdx refers no nonexistent operand");
 450
 451   const MachineOperand &FoldOp = MI.getOperand(FoldIdx);
 452   const MachineOperand &LiveOp = MI.getOperand(1 - FoldIdx);
 453
 454   if (FoldOp.getSubReg() || LiveOp.getSubReg())
 455     return nullptr;
 456
 457   Register FoldReg = FoldOp.getReg();
 458   Register LiveReg = LiveOp.getReg();
 459
 460   assert(Register::isVirtualRegister(FoldReg) && "Cannot fold physregs");
 461
 462   const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
 463   const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
 464
 465   if (Register::isPhysicalRegister(LiveOp.getReg()))
 466     return RC->contains(LiveOp.getReg()) ? RC : nullptr;
 467
 468   if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
 469     return RC;
 470
 471   // FIXME: Allow folding when register classes are memory compatible.
 472   return nullptr;
 473 }
 474
 475 MCInst TargetInstrInfo::getNop() const { llvm_unreachable("Not implemented"); }
 476
 477 std::pair<unsigned, unsigned>
 478 TargetInstrInfo::getPatchpointUnfoldableRange(const MachineInstr &MI) const {
 479   switch (MI.getOpcode()) {
 480   case TargetOpcode::STACKMAP:
 481     // StackMapLiveValues are foldable
 482     return std::make_pair(0, StackMapOpers(&MI).getVarIdx());
 483   case TargetOpcode::PATCHPOINT:
 484     // For PatchPoint, the call args are not foldable (even if reported in the
 485     // stackmap e.g. via anyregcc).
 486     return std::make_pair(0, PatchPointOpers(&MI).getVarIdx());
 487   case TargetOpcode::STATEPOINT:
 488     // For statepoints, fold deopt and gc arguments, but not call arguments.
 489     return std::make_pair(MI.getNumDefs(), StatepointOpers(&MI).getVarIdx());
 490   default:
 491     llvm_unreachable("unexpected stackmap opcode");
 492   }
 493 }
 494
 495 static MachineInstr *foldPatchpoint(MachineFunction &MF, MachineInstr &MI,
 496                                     ArrayRef<unsigned> Ops, int FrameIndex,
 497                                     const TargetInstrInfo &TII) {
 498   unsigned StartIdx = 0;
 499   unsigned NumDefs = 0;
 500   // getPatchpointUnfoldableRange throws guarantee if MI is not a patchpoint.
 501   std::tie(NumDefs, StartIdx) = TII.getPatchpointUnfoldableRange(MI);
 502
 503   unsigned DefToFoldIdx = MI.getNumOperands();
 504
 505   // Return false if any operands requested for folding are not foldable (not
 506   // part of the stackmap's live values).
 507   for (unsigned Op : Ops) {
 508     if (Op < NumDefs) {
 509       assert(DefToFoldIdx == MI.getNumOperands() && "Folding multiple defs");
 510       DefToFoldIdx = Op;
 511     } else if (Op < StartIdx) {
 512       return nullptr;
 513     }
 514     if (MI.getOperand(Op).isTied())
 515       return nullptr;
 516   }
 517
 518   MachineInstr *NewMI =
 519       MF.CreateMachineInstr(TII.get(MI.getOpcode()), MI.getDebugLoc(), true);
 520   MachineInstrBuilder MIB(MF, NewMI);
 521
 522   // No need to fold return, the meta data, and function arguments
 523   for (unsigned i = 0; i < StartIdx; ++i)
 524     if (i != DefToFoldIdx)
 525       MIB.add(MI.getOperand(i));
 526
 527   for (unsigned i = StartIdx, e = MI.getNumOperands(); i < e; ++i) {
 528     MachineOperand &MO = MI.getOperand(i);
 529     unsigned TiedTo = e;
 530     (void)MI.isRegTiedToDefOperand(i, &TiedTo);
 531
 532     if (is_contained(Ops, i)) {
 533       assert(TiedTo == e && "Cannot fold tied operands");
 534       unsigned SpillSize;
 535       unsigned SpillOffset;
 536       // Compute the spill slot size and offset.
 537       const TargetRegisterClass *RC =
 538         MF.getRegInfo().getRegClass(MO.getReg());
 539       bool Valid =
 540           TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF);
 541       if (!Valid)
 542         report_fatal_error("cannot spill patchpoint subregister operand");
 543       MIB.addImm(StackMaps::IndirectMemRefOp);
 544       MIB.addImm(SpillSize);
 545       MIB.addFrameIndex(FrameIndex);
 546       MIB.addImm(SpillOffset);
 547     } else {
 548       MIB.add(MO);
 549       if (TiedTo < e) {
 550         assert(TiedTo < NumDefs && "Bad tied operand");
 551         if (TiedTo > DefToFoldIdx)
 552           --TiedTo;
 553         NewMI->tieOperands(TiedTo, NewMI->getNumOperands() - 1);
 554       }
 555     }
 556   }
 557   return NewMI;
 558 }
 559
 560 MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,
 561                                                  ArrayRef<unsigned> Ops, int FI,
 562                                                  LiveIntervals *LIS,
 563                                                  VirtRegMap *VRM) const {
 564   auto Flags = MachineMemOperand::MONone;
 565   for (unsigned OpIdx : Ops)
 566     Flags |= MI.getOperand(OpIdx).isDef() ? MachineMemOperand::MOStore
 567                                           : MachineMemOperand::MOLoad;
 568
 569   MachineBasicBlock *MBB = MI.getParent();
 570   assert(MBB && "foldMemoryOperand needs an inserted instruction");
 571   MachineFunction &MF = *MBB->getParent();
 572
 573   // If we're not folding a load into a subreg, the size of the load is the
 574   // size of the spill slot. But if we are, we need to figure out what the
 575   // actual load size is.
 576   int64_t MemSize = 0;
 577   const MachineFrameInfo &MFI = MF.getFrameInfo();
 578   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
 579
 580   if (Flags & MachineMemOperand::MOStore) {
 581     MemSize = MFI.getObjectSize(FI);
 582   } else {
 583     for (unsigned OpIdx : Ops) {
 584       int64_t OpSize = MFI.getObjectSize(FI);
 585
 586       if (auto SubReg = MI.getOperand(OpIdx).getSubReg()) {
 587         unsigned SubRegSize = TRI->getSubRegIdxSize(SubReg);
 588         if (SubRegSize > 0 && !(SubRegSize % 8))
 589           OpSize = SubRegSize / 8;
 590       }
 591
 592       MemSize = std::max(MemSize, OpSize);
 593     }
 594   }
 595
 596   assert(MemSize && "Did not expect a zero-sized stack slot");
 597
 598   MachineInstr *NewMI = nullptr;
 599
 600   if (MI.getOpcode() == TargetOpcode::STACKMAP ||
 601       MI.getOpcode() == TargetOpcode::PATCHPOINT ||
 602       MI.getOpcode() == TargetOpcode::STATEPOINT) {
 603     // Fold stackmap/patchpoint.
 604     NewMI = foldPatchpoint(MF, MI, Ops, FI, *this);
 605     if (NewMI)
 606       MBB->insert(MI, NewMI);
 607   } else {
 608     // Ask the target to do the actual folding.
 609     NewMI = foldMemoryOperandImpl(MF, MI, Ops, MI, FI, LIS, VRM);
 610   }
 611
 612   if (NewMI) {
 613     NewMI->setMemRefs(MF, MI.memoperands());
 614     // Add a memory operand, foldMemoryOperandImpl doesn't do that.
 615     assert((!(Flags & MachineMemOperand::MOStore) ||
 616             NewMI->mayStore()) &&
 617            "Folded a def to a non-store!");
 618     assert((!(Flags & MachineMemOperand::MOLoad) ||
 619             NewMI->mayLoad()) &&
 620            "Folded a use to a non-load!");
 621     assert(MFI.getObjectOffset(FI) != -1);
 622     MachineMemOperand *MMO =
 623         MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI),
 624                                 Flags, MemSize, MFI.getObjectAlign(FI));
 625     NewMI->addMemOperand(MF, MMO);
 626
 627     // The pass "x86 speculative load hardening" always attaches symbols to
 628     // call instructions. We need copy it form old instruction.
 629     NewMI->cloneInstrSymbols(MF, MI);
 630
 631     return NewMI;
 632   }
 633
 634   // Straight COPY may fold as load/store.
 635   if (!MI.isCopy() || Ops.size() != 1)
 636     return nullptr;
 637
 638   const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]);
 639   if (!RC)
 640     return nullptr;
 641
 642   const MachineOperand &MO = MI.getOperand(1 - Ops[0]);
 643   MachineBasicBlock::iterator Pos = MI;
 644
 645   if (Flags == MachineMemOperand::MOStore)
 646     storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI);
 647   else
 648     loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI);
 649   return &*--Pos;
 650 }
 651
 652 MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,
 653                                                  ArrayRef<unsigned> Ops,
 654                                                  MachineInstr &LoadMI,
 655                                                  LiveIntervals *LIS) const {
 656   assert(LoadMI.canFoldAsLoad() && "LoadMI isn't foldable!");
 657 #ifndef NDEBUG
 658   for (unsigned OpIdx : Ops)
 659     assert(MI.getOperand(OpIdx).isUse() && "Folding load into def!");
 660 #endif
 661
 662   MachineBasicBlock &MBB = *MI.getParent();
 663   MachineFunction &MF = *MBB.getParent();
 664
 665   // Ask the target to do the actual folding.
 666   MachineInstr *NewMI = nullptr;
 667   int FrameIndex = 0;
 668
 669   if ((MI.getOpcode() == TargetOpcode::STACKMAP ||
 670        MI.getOpcode() == TargetOpcode::PATCHPOINT ||
 671        MI.getOpcode() == TargetOpcode::STATEPOINT) &&
 672       isLoadFromStackSlot(LoadMI, FrameIndex)) {
 673     // Fold stackmap/patchpoint.
 674     NewMI = foldPatchpoint(MF, MI, Ops, FrameIndex, *this);
 675     if (NewMI)
 676       NewMI = &*MBB.insert(MI, NewMI);
 677   } else {
 678     // Ask the target to do the actual folding.
 679     NewMI = foldMemoryOperandImpl(MF, MI, Ops, MI, LoadMI, LIS);
 680   }
 681
 682   if (!NewMI)
 683     return nullptr;
 684
 685   // Copy the memoperands from the load to the folded instruction.
 686   if (MI.memoperands_empty()) {
 687     NewMI->setMemRefs(MF, LoadMI.memoperands());
 688   } else {
 689     // Handle the rare case of folding multiple loads.
 690     NewMI->setMemRefs(MF, MI.memoperands());
 691     for (MachineInstr::mmo_iterator I = LoadMI.memoperands_begin(),
 692                                     E = LoadMI.memoperands_end();
 693          I != E; ++I) {
 694       NewMI->addMemOperand(MF, *I);
 695     }
 696   }
 697   return NewMI;
 698 }
 699
 700 bool TargetInstrInfo::hasReassociableOperands(
 701     const MachineInstr &Inst, const MachineBasicBlock *MBB) const {
 702   const MachineOperand &Op1 = Inst.getOperand(1);
 703   const MachineOperand &Op2 = Inst.getOperand(2);
 704   const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
 705
 706   // We need virtual register definitions for the operands that we will
 707   // reassociate.
 708   MachineInstr *MI1 = nullptr;
 709   MachineInstr *MI2 = nullptr;
 710   if (Op1.isReg() && Register::isVirtualRegister(Op1.getReg()))
 711     MI1 = MRI.getUniqueVRegDef(Op1.getReg());
 712   if (Op2.isReg() && Register::isVirtualRegister(Op2.getReg()))
 713     MI2 = MRI.getUniqueVRegDef(Op2.getReg());
 714
 715   // And they need to be in the trace (otherwise, they won't have a depth).
 716   return MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB;
 717 }
 718
 719 bool TargetInstrInfo::hasReassociableSibling(const MachineInstr &Inst,
 720                                              bool &Commuted) const {
 721   const MachineBasicBlock *MBB = Inst.getParent();
 722   const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
 723   MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg());
 724   MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg());
 725   unsigned AssocOpcode = Inst.getOpcode();
 726
 727   // If only one operand has the same opcode and it's the second source operand,
 728   // the operands must be commuted.
 729   Commuted = MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode;
 730   if (Commuted)
 731     std::swap(MI1, MI2);
 732
 733   // 1. The previous instruction must be the same type as Inst.
 734   // 2. The previous instruction must also be associative/commutative (this can
 735   //    be different even for instructions with the same opcode if traits like
 736   //    fast-math-flags are included).
 737   // 3. The previous instruction must have virtual register definitions for its
 738   //    operands in the same basic block as Inst.
 739   // 4. The previous instruction's result must only be used by Inst.
 740   return MI1->getOpcode() == AssocOpcode && isAssociativeAndCommutative(*MI1) &&
 741          hasReassociableOperands(*MI1, MBB) &&
 742          MRI.hasOneNonDBGUse(MI1->getOperand(0).getReg());
 743 }
 744
 745 // 1. The operation must be associative and commutative.
 746 // 2. The instruction must have virtual register definitions for its
 747 //    operands in the same basic block.
 748 // 3. The instruction must have a reassociable sibling.
 749 bool TargetInstrInfo::isReassociationCandidate(const MachineInstr &Inst,
 750                                                bool &Commuted) const {
 751   return isAssociativeAndCommutative(Inst) &&
 752          hasReassociableOperands(Inst, Inst.getParent()) &&
 753          hasReassociableSibling(Inst, Commuted);
 754 }
 755
 756 // The concept of the reassociation pass is that these operations can benefit
 757 // from this kind of transformation:
 758 //
 759 // A = ? op ?
 760 // B = A op X (Prev)
 761 // C = B op Y (Root)
 762 // -->
 763 // A = ? op ?
 764 // B = X op Y
 765 // C = A op B
 766 //
 767 // breaking the dependency between A and B, allowing them to be executed in
 768 // parallel (or back-to-back in a pipeline) instead of depending on each other.
 769
 770 // FIXME: This has the potential to be expensive (compile time) while not
 771 // improving the code at all. Some ways to limit the overhead:
 772 // 1. Track successful transforms; bail out if hit rate gets too low.
 773 // 2. Only enable at -O3 or some other non-default optimization level.
 774 // 3. Pre-screen pattern candidates here: if an operand of the previous
 775 //    instruction is known to not increase the critical path, then don't match
 776 //    that pattern.
 777 bool TargetInstrInfo::getMachineCombinerPatterns(
 778     MachineInstr &Root, SmallVectorImpl<MachineCombinerPattern> &Patterns,
 779     bool DoRegPressureReduce) const {
 780   bool Commute;
 781   if (isReassociationCandidate(Root, Commute)) {
 782     // We found a sequence of instructions that may be suitable for a
 783     // reassociation of operands to increase ILP. Specify each commutation
 784     // possibility for the Prev instruction in the sequence and let the
 785     // machine combiner decide if changing the operands is worthwhile.
 786     if (Commute) {
 787       Patterns.push_back(MachineCombinerPattern::REASSOC_AX_YB);
 788       Patterns.push_back(MachineCombinerPattern::REASSOC_XA_YB);
 789     } else {
 790       Patterns.push_back(MachineCombinerPattern::REASSOC_AX_BY);
 791       Patterns.push_back(MachineCombinerPattern::REASSOC_XA_BY);
 792     }
 793     return true;
 794   }
 795
 796   return false;
 797 }
 798
 799 /// Return true when a code sequence can improve loop throughput.
 800 bool
 801 TargetInstrInfo::isThroughputPattern(MachineCombinerPattern Pattern) const {
 802   return false;
 803 }
 804
 805 /// Attempt the reassociation transformation to reduce critical path length.
 806 /// See the above comments before getMachineCombinerPatterns().
 807 void TargetInstrInfo::reassociateOps(
 808     MachineInstr &Root, MachineInstr &Prev,
 809     MachineCombinerPattern Pattern,
 810     SmallVectorImpl<MachineInstr *> &InsInstrs,
 811     SmallVectorImpl<MachineInstr *> &DelInstrs,
 812     DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
 813   MachineFunction *MF = Root.getMF();
 814   MachineRegisterInfo &MRI = MF->getRegInfo();
 815   const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
 816   const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
 817   const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI);
 818
 819   // This array encodes the operand index for each parameter because the
 820   // operands may be commuted. Each row corresponds to a pattern value,
 821   // and each column specifies the index of A, B, X, Y.
 822   unsigned OpIdx[4][4] = {
 823     { 1, 1, 2, 2 },
 824     { 1, 2, 2, 1 },
 825     { 2, 1, 1, 2 },
 826     { 2, 2, 1, 1 }
 827   };
 828
 829   int Row;
 830   switch (Pattern) {
 831   case MachineCombinerPattern::REASSOC_AX_BY: Row = 0; break;
 832   case MachineCombinerPattern::REASSOC_AX_YB: Row = 1; break;
 833   case MachineCombinerPattern::REASSOC_XA_BY: Row = 2; break;
 834   case MachineCombinerPattern::REASSOC_XA_YB: Row = 3; break;
 835   default: llvm_unreachable("unexpected MachineCombinerPattern");
 836   }
 837
 838   MachineOperand &OpA = Prev.getOperand(OpIdx[Row][0]);
 839   MachineOperand &OpB = Root.getOperand(OpIdx[Row][1]);
 840   MachineOperand &OpX = Prev.getOperand(OpIdx[Row][2]);
 841   MachineOperand &OpY = Root.getOperand(OpIdx[Row][3]);
 842   MachineOperand &OpC = Root.getOperand(0);
 843
 844   Register RegA = OpA.getReg();
 845   Register RegB = OpB.getReg();
 846   Register RegX = OpX.getReg();
 847   Register RegY = OpY.getReg();
 848   Register RegC = OpC.getReg();
 849
 850   if (Register::isVirtualRegister(RegA))
 851     MRI.constrainRegClass(RegA, RC);
 852   if (Register::isVirtualRegister(RegB))
 853     MRI.constrainRegClass(RegB, RC);
 854   if (Register::isVirtualRegister(RegX))
 855     MRI.constrainRegClass(RegX, RC);
 856   if (Register::isVirtualRegister(RegY))
 857     MRI.constrainRegClass(RegY, RC);
 858   if (Register::isVirtualRegister(RegC))
 859     MRI.constrainRegClass(RegC, RC);
 860
 861   // Create a new virtual register for the result of (X op Y) instead of
 862   // recycling RegB because the MachineCombiner's computation of the critical
 863   // path requires a new register definition rather than an existing one.
 864   Register NewVR = MRI.createVirtualRegister(RC);
 865   InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
 866
 867   unsigned Opcode = Root.getOpcode();
 868   bool KillA = OpA.isKill();
 869   bool KillX = OpX.isKill();
 870   bool KillY = OpY.isKill();
 871
 872   // Create new instructions for insertion.
 873   MachineInstrBuilder MIB1 =
 874       BuildMI(*MF, Prev.getDebugLoc(), TII->get(Opcode), NewVR)
 875           .addReg(RegX, getKillRegState(KillX))
 876           .addReg(RegY, getKillRegState(KillY));
 877   MachineInstrBuilder MIB2 =
 878       BuildMI(*MF, Root.getDebugLoc(), TII->get(Opcode), RegC)
 879           .addReg(RegA, getKillRegState(KillA))
 880           .addReg(NewVR, getKillRegState(true));
 881
 882   setSpecialOperandAttr(Root, Prev, *MIB1, *MIB2);
 883
 884   // Record new instructions for insertion and old instructions for deletion.
 885   InsInstrs.push_back(MIB1);
 886   InsInstrs.push_back(MIB2);
 887   DelInstrs.push_back(&Prev);
 888   DelInstrs.push_back(&Root);
 889 }
 890
 891 void TargetInstrInfo::genAlternativeCodeSequence(
 892     MachineInstr &Root, MachineCombinerPattern Pattern,
 893     SmallVectorImpl<MachineInstr *> &InsInstrs,
 894     SmallVectorImpl<MachineInstr *> &DelInstrs,
 895     DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const {
 896   MachineRegisterInfo &MRI = Root.getMF()->getRegInfo();
 897
 898   // Select the previous instruction in the sequence based on the input pattern.
 899   MachineInstr *Prev = nullptr;
 900   switch (Pattern) {
 901   case MachineCombinerPattern::REASSOC_AX_BY:
 902   case MachineCombinerPattern::REASSOC_XA_BY:
 903     Prev = MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
 904     break;
 905   case MachineCombinerPattern::REASSOC_AX_YB:
 906   case MachineCombinerPattern::REASSOC_XA_YB:
 907     Prev = MRI.getUniqueVRegDef(Root.getOperand(2).getReg());
 908     break;
 909   default:
 910     break;
 911   }
 912
 913   assert(Prev && "Unknown pattern for machine combiner");
 914
 915   reassociateOps(Root, *Prev, Pattern, InsInstrs, DelInstrs, InstIdxForVirtReg);
 916 }
 917
 918 bool TargetInstrInfo::isReallyTriviallyReMaterializableGeneric(
 919     const MachineInstr &MI, AAResults *AA) const {
 920   const MachineFunction &MF = *MI.getMF();
 921   const MachineRegisterInfo &MRI = MF.getRegInfo();
 922
 923   // Remat clients assume operand 0 is the defined register.
 924   if (!MI.getNumOperands() || !MI.getOperand(0).isReg())
 925     return false;
 926   Register DefReg = MI.getOperand(0).getReg();
 927
 928   // A sub-register definition can only be rematerialized if the instruction
 929   // doesn't read the other parts of the register.  Otherwise it is really a
 930   // read-modify-write operation on the full virtual register which cannot be
 931   // moved safely.
 932   if (Register::isVirtualRegister(DefReg) && MI.getOperand(0).getSubReg() &&
 933       MI.readsVirtualRegister(DefReg))
 934     return false;
 935
 936   // A load from a fixed stack slot can be rematerialized. This may be
 937   // redundant with subsequent checks, but it's target-independent,
 938   // simple, and a common case.
 939   int FrameIdx = 0;
 940   if (isLoadFromStackSlot(MI, FrameIdx) &&
 941       MF.getFrameInfo().isImmutableObjectIndex(FrameIdx))
 942     return true;
 943
 944   // Avoid instructions obviously unsafe for remat.
 945   if (MI.isNotDuplicable() || MI.mayStore() || MI.mayRaiseFPException() ||
 946       MI.hasUnmodeledSideEffects())
 947     return false;
 948
 949   // Don't remat inline asm. We have no idea how expensive it is
 950   // even if it's side effect free.
 951   if (MI.isInlineAsm())
 952     return false;
 953
 954   // Avoid instructions which load from potentially varying memory.
 955   if (MI.mayLoad() && !MI.isDereferenceableInvariantLoad(AA))
 956     return false;
 957
 958   // If any of the registers accessed are non-constant, conservatively assume
 959   // the instruction is not rematerializable.
 960   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
 961     const MachineOperand &MO = MI.getOperand(i);
 962     if (!MO.isReg()) continue;
 963     Register Reg = MO.getReg();
 964     if (Reg == 0)
 965       continue;
 966
 967     // Check for a well-behaved physical register.
 968     if (Register::isPhysicalRegister(Reg)) {
 969       if (MO.isUse()) {
 970         // If the physreg has no defs anywhere, it's just an ambient register
 971         // and we can freely move its uses. Alternatively, if it's allocatable,
 972         // it could get allocated to something with a def during allocation.
 973         if (!MRI.isConstantPhysReg(Reg))
 974           return false;
 975       } else {
 976         // A physreg def. We can't remat it.
 977         return false;
 978       }
 979       continue;
 980     }
 981
 982     // Only allow one virtual-register def.  There may be multiple defs of the
 983     // same virtual register, though.
 984     if (MO.isDef() && Reg != DefReg)
 985       return false;
 986
 987     // Don't allow any virtual-register uses. Rematting an instruction with
 988     // virtual register uses would length the live ranges of the uses, which
 989     // is not necessarily a good idea, certainly not "trivial".
 990     if (MO.isUse())
 991       return false;
 992   }
 993
 994   // Everything checked out.
 995   return true;
 996 }
 997
 998 int TargetInstrInfo::getSPAdjust(const MachineInstr &MI) const {
 999   const MachineFunction *MF = MI.getMF();
1000   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
1001   bool StackGrowsDown =
1002     TFI->getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown;
1003
1004   unsigned FrameSetupOpcode = getCallFrameSetupOpcode();
1005   unsigned FrameDestroyOpcode = getCallFrameDestroyOpcode();
1006
1007   if (!isFrameInstr(MI))
1008     return 0;
1009
1010   int SPAdj = TFI->alignSPAdjust(getFrameSize(MI));
1011
1012   if ((!StackGrowsDown && MI.getOpcode() == FrameSetupOpcode) ||
1013       (StackGrowsDown && MI.getOpcode() == FrameDestroyOpcode))
1014     SPAdj = -SPAdj;
1015
1016   return SPAdj;
1017 }
1018
1019 /// isSchedulingBoundary - Test if the given instruction should be
1020 /// considered a scheduling boundary. This primarily includes labels
1021 /// and terminators.
1022 bool TargetInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
1023                                            const MachineBasicBlock *MBB,
1024                                            const MachineFunction &MF) const {
1025   // Terminators and labels can't be scheduled around.
1026   if (MI.isTerminator() || MI.isPosition())
1027     return true;
1028
1029   // INLINEASM_BR can jump to another block
1030   if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)
1031     return true;
1032
1033   // Don't attempt to schedule around any instruction that defines
1034   // a stack-oriented pointer, as it's unlikely to be profitable. This
1035   // saves compile time, because it doesn't require every single
1036   // stack slot reference to depend on the instruction that does the
1037   // modification.
1038   const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
1039   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1040   return MI.modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI);
1041 }
1042
1043 // Provide a global flag for disabling the PreRA hazard recognizer that targets
1044 // may choose to honor.
1045 bool TargetInstrInfo::usePreRAHazardRecognizer() const {
1046   return !DisableHazardRecognizer;
1047 }
1048
1049 // Default implementation of CreateTargetRAHazardRecognizer.
1050 ScheduleHazardRecognizer *TargetInstrInfo::
1051 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
1052                              const ScheduleDAG *DAG) const {
1053   // Dummy hazard recognizer allows all instructions to issue.
1054   return new ScheduleHazardRecognizer();
1055 }
1056
1057 // Default implementation of CreateTargetMIHazardRecognizer.
1058 ScheduleHazardRecognizer *TargetInstrInfo::CreateTargetMIHazardRecognizer(
1059     const InstrItineraryData *II, const ScheduleDAGMI *DAG) const {
1060   return new ScoreboardHazardRecognizer(II, DAG, "machine-scheduler");
1061 }
1062
1063 // Default implementation of CreateTargetPostRAHazardRecognizer.
1064 ScheduleHazardRecognizer *TargetInstrInfo::
1065 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
1066                                    const ScheduleDAG *DAG) const {
1067   return new ScoreboardHazardRecognizer(II, DAG, "post-RA-sched");
1068 }
1069
1070 // Default implementation of getMemOperandWithOffset.
1071 bool TargetInstrInfo::getMemOperandWithOffset(
1072     const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset,
1073     bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const {
1074   SmallVector<const MachineOperand *, 4> BaseOps;
1075   unsigned Width;
1076   if (!getMemOperandsWithOffsetWidth(MI, BaseOps, Offset, OffsetIsScalable,
1077                                      Width, TRI) ||
1078       BaseOps.size() != 1)
1079     return false;
1080   BaseOp = BaseOps.front();
1081   return true;
1082 }
1083
1084 //===----------------------------------------------------------------------===//
1085 //  SelectionDAG latency interface.
1086 //===----------------------------------------------------------------------===//
1087
1088 int
1089 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
1090                                    SDNode *DefNode, unsigned DefIdx,
1091                                    SDNode *UseNode, unsigned UseIdx) const {
1092   if (!ItinData || ItinData->isEmpty())
1093     return -1;
1094
1095   if (!DefNode->isMachineOpcode())
1096     return -1;
1097
1098   unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass();
1099   if (!UseNode->isMachineOpcode())
1100     return ItinData->getOperandCycle(DefClass, DefIdx);
1101   unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass();
1102   return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
1103 }
1104
1105 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
1106                                      SDNode *N) const {
1107   if (!ItinData || ItinData->isEmpty())
1108     return 1;
1109
1110   if (!N->isMachineOpcode())
1111     return 1;
1112
1113   return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
1114 }
1115
1116 //===----------------------------------------------------------------------===//
1117 //  MachineInstr latency interface.
1118 //===----------------------------------------------------------------------===//
1119
1120 unsigned TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
1121                                          const MachineInstr &MI) const {
1122   if (!ItinData || ItinData->isEmpty())
1123     return 1;
1124
1125   unsigned Class = MI.getDesc().getSchedClass();
1126   int UOps = ItinData->Itineraries[Class].NumMicroOps;
1127   if (UOps >= 0)
1128     return UOps;
1129
1130   // The # of u-ops is dynamically determined. The specific target should
1131   // override this function to return the right number.
1132   return 1;
1133 }
1134
1135 /// Return the default expected latency for a def based on it's opcode.
1136 unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel &SchedModel,
1137                                             const MachineInstr &DefMI) const {
1138   if (DefMI.isTransient())
1139     return 0;
1140   if (DefMI.mayLoad())
1141     return SchedModel.LoadLatency;
1142   if (isHighLatencyDef(DefMI.getOpcode()))
1143     return SchedModel.HighLatency;
1144   return 1;
1145 }
1146
1147 unsigned TargetInstrInfo::getPredicationCost(const MachineInstr &) const {
1148   return 0;
1149 }
1150
1151 unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
1152                                           const MachineInstr &MI,
1153                                           unsigned *PredCost) const {
1154   // Default to one cycle for no itinerary. However, an "empty" itinerary may
1155   // still have a MinLatency property, which getStageLatency checks.
1156   if (!ItinData)
1157     return MI.mayLoad() ? 2 : 1;
1158
1159   return ItinData->getStageLatency(MI.getDesc().getSchedClass());
1160 }
1161
1162 bool TargetInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
1163                                        const MachineInstr &DefMI,
1164                                        unsigned DefIdx) const {
1165   const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
1166   if (!ItinData || ItinData->isEmpty())
1167     return false;
1168
1169   unsigned DefClass = DefMI.getDesc().getSchedClass();
1170   int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
1171   return (DefCycle != -1 && DefCycle <= 1);
1172 }
1173
1174 Optional<ParamLoadedValue>
1175 TargetInstrInfo::describeLoadedValue(const MachineInstr &MI,
1176                                      Register Reg) const {
1177   const MachineFunction *MF = MI.getMF();
1178   const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
1179   DIExpression *Expr = DIExpression::get(MF->getFunction().getContext(), {});
1180   int64_t Offset;
1181   bool OffsetIsScalable;
1182
1183   // To simplify the sub-register handling, verify that we only need to
1184   // consider physical registers.
1185   assert(MF->getProperties().hasProperty(
1186       MachineFunctionProperties::Property::NoVRegs));
1187
1188   if (auto DestSrc = isCopyInstr(MI)) {
1189     Register DestReg = DestSrc->Destination->getReg();
1190
1191     // If the copy destination is the forwarding reg, describe the forwarding
1192     // reg using the copy source as the backup location. Example:
1193     //
1194     //   x0 = MOV x7
1195     //   call callee(x0)      ; x0 described as x7
1196     if (Reg == DestReg)
1197       return ParamLoadedValue(*DestSrc->Source, Expr);
1198
1199     // Cases where super- or sub-registers needs to be described should
1200     // be handled by the target's hook implementation.
1201     assert(!TRI->isSuperOrSubRegisterEq(Reg, DestReg) &&
1202            "TargetInstrInfo::describeLoadedValue can't describe super- or "
1203            "sub-regs for copy instructions");
1204     return None;
1205   } else if (auto RegImm = isAddImmediate(MI, Reg)) {
1206     Register SrcReg = RegImm->Reg;
1207     Offset = RegImm->Imm;
1208     Expr = DIExpression::prepend(Expr, DIExpression::ApplyOffset, Offset);
1209     return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
1210   } else if (MI.hasOneMemOperand()) {
1211     // Only describe memory which provably does not escape the function. As
1212     // described in llvm.org/PR43343, escaped memory may be clobbered by the
1213     // callee (or by another thread).
1214     const auto &TII = MF->getSubtarget().getInstrInfo();
1215     const MachineFrameInfo &MFI = MF->getFrameInfo();
1216     const MachineMemOperand *MMO = MI.memoperands()[0];
1217     const PseudoSourceValue *PSV = MMO->getPseudoValue();
1218
1219     // If the address points to "special" memory (e.g. a spill slot), it's
1220     // sufficient to check that it isn't aliased by any high-level IR value.
1221     if (!PSV || PSV->mayAlias(&MFI))
1222       return None;
1223
1224     const MachineOperand *BaseOp;
1225     if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable,
1226                                       TRI))
1227       return None;
1228
1229     // FIXME: Scalable offsets are not yet handled in the offset code below.
1230     if (OffsetIsScalable)
1231       return None;
1232
1233     // TODO: Can currently only handle mem instructions with a single define.
1234     // An example from the x86 target:
1235     //    ...
1236     //    DIV64m $rsp, 1, $noreg, 24, $noreg, implicit-def dead $rax, implicit-def $rdx
1237     //    ...
1238     //
1239     if (MI.getNumExplicitDefs() != 1)
1240       return None;
1241
1242     // TODO: In what way do we need to take Reg into consideration here?
1243
1244     SmallVector<uint64_t, 8> Ops;
1245     DIExpression::appendOffset(Ops, Offset);
1246     Ops.push_back(dwarf::DW_OP_deref_size);
1247     Ops.push_back(MMO->getSize());
1248     Expr = DIExpression::prependOpcodes(Expr, Ops);
1249     return ParamLoadedValue(*BaseOp, Expr);
1250   }
1251
1252   return None;
1253 }
1254
1255 /// Both DefMI and UseMI must be valid.  By default, call directly to the
1256 /// itinerary. This may be overriden by the target.
1257 int TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
1258                                        const MachineInstr &DefMI,
1259                                        unsigned DefIdx,
1260                                        const MachineInstr &UseMI,
1261                                        unsigned UseIdx) const {
1262   unsigned DefClass = DefMI.getDesc().getSchedClass();
1263   unsigned UseClass = UseMI.getDesc().getSchedClass();
1264   return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
1265 }
1266
1267 bool TargetInstrInfo::getRegSequenceInputs(
1268     const MachineInstr &MI, unsigned DefIdx,
1269     SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
1270   assert((MI.isRegSequence() ||
1271           MI.isRegSequenceLike()) && "Instruction do not have the proper type");
1272
1273   if (!MI.isRegSequence())
1274     return getRegSequenceLikeInputs(MI, DefIdx, InputRegs);
1275
1276   // We are looking at:
1277   // Def = REG_SEQUENCE v0, sub0, v1, sub1, ...
1278   assert(DefIdx == 0 && "REG_SEQUENCE only has one def");
1279   for (unsigned OpIdx = 1, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx;
1280        OpIdx += 2) {
1281     const MachineOperand &MOReg = MI.getOperand(OpIdx);
1282     if (MOReg.isUndef())
1283       continue;
1284     const MachineOperand &MOSubIdx = MI.getOperand(OpIdx + 1);
1285     assert(MOSubIdx.isImm() &&
1286            "One of the subindex of the reg_sequence is not an immediate");
1287     // Record Reg:SubReg, SubIdx.
1288     InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(),
1289                                             (unsigned)MOSubIdx.getImm()));
1290   }
1291   return true;
1292 }
1293
1294 bool TargetInstrInfo::getExtractSubregInputs(
1295     const MachineInstr &MI, unsigned DefIdx,
1296     RegSubRegPairAndIdx &InputReg) const {
1297   assert((MI.isExtractSubreg() ||
1298       MI.isExtractSubregLike()) && "Instruction do not have the proper type");
1299
1300   if (!MI.isExtractSubreg())
1301     return getExtractSubregLikeInputs(MI, DefIdx, InputReg);
1302
1303   // We are looking at:
1304   // Def = EXTRACT_SUBREG v0.sub1, sub0.
1305   assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def");
1306   const MachineOperand &MOReg = MI.getOperand(1);
1307   if (MOReg.isUndef())
1308     return false;
1309   const MachineOperand &MOSubIdx = MI.getOperand(2);
1310   assert(MOSubIdx.isImm() &&
1311          "The subindex of the extract_subreg is not an immediate");
1312
1313   InputReg.Reg = MOReg.getReg();
1314   InputReg.SubReg = MOReg.getSubReg();
1315   InputReg.SubIdx = (unsigned)MOSubIdx.getImm();
1316   return true;
1317 }
1318
1319 bool TargetInstrInfo::getInsertSubregInputs(
1320     const MachineInstr &MI, unsigned DefIdx,
1321     RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const {
1322   assert((MI.isInsertSubreg() ||
1323       MI.isInsertSubregLike()) && "Instruction do not have the proper type");
1324
1325   if (!MI.isInsertSubreg())
1326     return getInsertSubregLikeInputs(MI, DefIdx, BaseReg, InsertedReg);
1327
1328   // We are looking at:
1329   // Def = INSERT_SEQUENCE v0, v1, sub0.
1330   assert(DefIdx == 0 && "INSERT_SUBREG only has one def");
1331   const MachineOperand &MOBaseReg = MI.getOperand(1);
1332   const MachineOperand &MOInsertedReg = MI.getOperand(2);
1333   if (MOInsertedReg.isUndef())
1334     return false;
1335   const MachineOperand &MOSubIdx = MI.getOperand(3);
1336   assert(MOSubIdx.isImm() &&
1337          "One of the subindex of the reg_sequence is not an immediate");
1338   BaseReg.Reg = MOBaseReg.getReg();
1339   BaseReg.SubReg = MOBaseReg.getSubReg();
1340
1341   InsertedReg.Reg = MOInsertedReg.getReg();
1342   InsertedReg.SubReg = MOInsertedReg.getSubReg();
1343   InsertedReg.SubIdx = (unsigned)MOSubIdx.getImm();
1344   return true;
1345 }
1346
1347 // Returns a MIRPrinter comment for this machine operand.
1348 std::string TargetInstrInfo::createMIROperandComment(
1349     const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx,
1350     const TargetRegisterInfo *TRI) const {
1351
1352   if (!MI.isInlineAsm())
1353     return "";
1354
1355   std::string Flags;
1356   raw_string_ostream OS(Flags);
1357
1358   if (OpIdx == InlineAsm::MIOp_ExtraInfo) {
1359     // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1360     unsigned ExtraInfo = Op.getImm();
1361     bool First = true;
1362     for (StringRef Info : InlineAsm::getExtraInfoNames(ExtraInfo)) {
1363       if (!First)
1364         OS << " ";
1365       First = false;
1366       OS << Info;
1367     }
1368
1369     return OS.str();
1370   }
1371
1372   int FlagIdx = MI.findInlineAsmFlagIdx(OpIdx);
1373   if (FlagIdx < 0 || (unsigned)FlagIdx != OpIdx)
1374     return "";
1375
1376   assert(Op.isImm() && "Expected flag operand to be an immediate");
1377   // Pretty print the inline asm operand descriptor.
1378   unsigned Flag = Op.getImm();
1379   unsigned Kind = InlineAsm::getKind(Flag);
1380   OS << InlineAsm::getKindName(Kind);
1381
1382   unsigned RCID = 0;
1383   if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
1384       InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1385     if (TRI) {
1386       OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1387     } else
1388       OS << ":RC" << RCID;
1389   }
1390
1391   if (InlineAsm::isMemKind(Flag)) {
1392     unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1393     OS << ":" << InlineAsm::getMemConstraintName(MCID);
1394   }
1395
1396   unsigned TiedTo = 0;
1397   if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1398     OS << " tiedto:$" << TiedTo;
1399
1400   return OS.str();
1401 }
1402
1403 TargetInstrInfo::PipelinerLoopInfo::~PipelinerLoopInfo() {}