llvm/test/MC/AMDGPU/gfx10_err_pos.s

   1 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+WavefrontSize32,-WavefrontSize64 %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
   2
   3 //==============================================================================
   4 // destination must be different than all sources
   5
   6 v_mqsad_pk_u16_u8 v[0:1], v[1:2], v9, v[4:5]
   7 // CHECK: error: destination must be different than all sources
   8 // CHECK-NEXT:{{^}}v_mqsad_pk_u16_u8 v[0:1], v[1:2], v9, v[4:5]
   9 // CHECK-NEXT:{{^}}                          ^
  10
  11 v_mqsad_pk_u16_u8 v[0:1], v[2:3], v0, v[4:5]
  12 // CHECK: error: destination must be different than all sources
  13 // CHECK-NEXT:{{^}}v_mqsad_pk_u16_u8 v[0:1], v[2:3], v0, v[4:5]
  14 // CHECK-NEXT:{{^}}                                  ^
  15
  16 v_mqsad_pk_u16_u8 v[0:1], v[2:3], v1, v[4:5]
  17 // CHECK: error: destination must be different than all sources
  18 // CHECK-NEXT:{{^}}v_mqsad_pk_u16_u8 v[0:1], v[2:3], v1, v[4:5]
  19 // CHECK-NEXT:{{^}}                                  ^
  20
  21 v_mqsad_pk_u16_u8 v[0:1], v[2:3], v9, v[0:1]
  22 // CHECK: error: destination must be different than all sources
  23 // CHECK-NEXT:{{^}}v_mqsad_pk_u16_u8 v[0:1], v[2:3], v9, v[0:1]
  24 // CHECK-NEXT:{{^}}                                      ^
  25
  26 //==============================================================================
  27 // dim modifier is required on this GPU
  28
  29 image_atomic_add v252, v2, s[8:15]
  30 // CHECK: error: dim modifier is required on this GPU
  31 // CHECK-NEXT:{{^}}image_atomic_add v252, v2, s[8:15]
  32 // CHECK-NEXT:{{^}}^
  33
  34 //==============================================================================
  35 // duplicate data format
  36
  37 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT_32,BUF_DATA_FORMAT_8]
  38 // CHECK: error: duplicate data format
  39 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT_32,BUF_DATA_FORMAT_8]
  40 // CHECK-NEXT:{{^}}                                                                                ^
  41
  42 //==============================================================================
  43 // duplicate numeric format
  44
  45 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_NUM_FORMAT_UINT,BUF_NUM_FORMAT_FLOAT]
  46 // CHECK: error: duplicate numeric format
  47 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_NUM_FORMAT_UINT,BUF_NUM_FORMAT_FLOAT]
  48 // CHECK-NEXT:{{^}}                                                                                 ^
  49
  50 //==============================================================================
  51 // expected ')' in parentheses expression
  52
  53 v_bfe_u32 v0, 1+(100, v1, v2
  54 // CHECK: error: expected ')' in parentheses expression
  55 // CHECK-NEXT:{{^}}v_bfe_u32 v0, 1+(100, v1, v2
  56 // CHECK-NEXT:{{^}}                    ^
  57
  58 //==============================================================================
  59 // expected a 12-bit signed offset
  60
  61 global_load_dword v1, v[3:4] off, offset:-4097
  62 // CHECK: error: expected a 12-bit signed offset
  63 // CHECK-NEXT:{{^}}global_load_dword v1, v[3:4] off, offset:-4097
  64 // CHECK-NEXT:{{^}}                                  ^
  65
  66 scratch_load_dword v0, v1, off offset:-2049 glc slc
  67 // CHECK: error: expected a 12-bit signed offset
  68 // CHECK-NEXT:{{^}}scratch_load_dword v0, v1, off offset:-2049 glc slc
  69 // CHECK-NEXT:{{^}}                               ^
  70
  71 //==============================================================================
  72 // expected a 16-bit signed jump offset
  73
  74 s_branch 0x10000
  75 // CHECK: error: expected a 16-bit signed jump offset
  76 // CHECK-NEXT:{{^}}s_branch 0x10000
  77 // CHECK-NEXT:{{^}}         ^
  78
  79 //==============================================================================
  80 // expected a 2-bit lane id
  81
  82 ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 4, 1, 2, 3)
  83 // CHECK: error: expected a 2-bit lane id
  84 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 4, 1, 2, 3)
  85 // CHECK-NEXT:{{^}}                                                ^
  86
  87 //==============================================================================
  88 // expected a 20-bit unsigned offset
  89
  90 s_atc_probe_buffer 0x1, s[8:11], -1
  91 // CHECK: error: expected a 20-bit unsigned offset
  92 // CHECK-NEXT:{{^}}s_atc_probe_buffer 0x1, s[8:11], -1
  93 // CHECK-NEXT:{{^}}                                 ^
  94
  95 s_atc_probe_buffer 0x1, s[8:11], 0xFFFFFFFFFFF00000
  96 // CHECK: error: expected a 20-bit unsigned offset
  97 // CHECK-NEXT:{{^}}s_atc_probe_buffer 0x1, s[8:11], 0xFFFFFFFFFFF00000
  98 // CHECK-NEXT:{{^}}                                 ^
  99
 100 s_buffer_atomic_swap s5, s[4:7], 0x1FFFFF
 101 // CHECK: error: expected a 20-bit unsigned offset
 102 // CHECK-NEXT:{{^}}s_buffer_atomic_swap s5, s[4:7], 0x1FFFFF
 103 // CHECK-NEXT:{{^}}                                 ^
 104
 105 //==============================================================================
 106 // expected a 21-bit signed offset
 107
 108 s_atc_probe 0x7, s[4:5], 0x1FFFFF
 109 // CHECK: error: expected a 21-bit signed offset
 110 // CHECK-NEXT:{{^}}s_atc_probe 0x7, s[4:5], 0x1FFFFF
 111 // CHECK-NEXT:{{^}}                         ^
 112
 113 s_atomic_swap s5, s[2:3], 0x1FFFFF
 114 // CHECK: error: expected a 21-bit signed offset
 115 // CHECK-NEXT:{{^}}s_atomic_swap s5, s[2:3], 0x1FFFFF
 116 // CHECK-NEXT:{{^}}                          ^
 117
 118 //==============================================================================
 119 // expected a 2-bit value
 120
 121 v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,4] row_mask:0x0 bank_mask:0x0
 122 // CHECK: error: expected a 2-bit value
 123 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,4] row_mask:0x0 bank_mask:0x0
 124 // CHECK-NEXT:{{^}}                                      ^
 125
 126 v_mov_b32_dpp v5, v1 quad_perm:[3,-1,1,3] row_mask:0x0 bank_mask:0x0
 127 // CHECK: error: expected a 2-bit value
 128 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:[3,-1,1,3] row_mask:0x0 bank_mask:0x0
 129 // CHECK-NEXT:{{^}}                                  ^
 130
 131 //==============================================================================
 132 // expected a 3-bit value
 133
 134 v_mov_b32_dpp v5, v1 dpp8:[-1,1,2,3,4,5,6,7]
 135 // CHECK: error: expected a 3-bit value
 136 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[-1,1,2,3,4,5,6,7]
 137 // CHECK-NEXT:{{^}}                           ^
 138
 139 v_mov_b32_dpp v5, v1 dpp8:[0,1,2,8,4,5,6,7]
 140 // CHECK: error: expected a 3-bit value
 141 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,8,4,5,6,7]
 142 // CHECK-NEXT:{{^}}                                 ^
 143
 144 //==============================================================================
 145 // expected a 5-character mask
 146
 147 ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "ppii")
 148 // CHECK: error: expected a 5-character mask
 149 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "ppii")
 150 // CHECK-NEXT:{{^}}                                                   ^
 151
 152 //==============================================================================
 153 // expected a closing parentheses
 154
 155 ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3
 156 // CHECK: error: expected a closing parentheses
 157 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3
 158 // CHECK-NEXT:{{^}}                                                          ^
 159
 160 ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3, 4)
 161 // CHECK: error: expected a closing parentheses
 162 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3, 4)
 163 // CHECK-NEXT:{{^}}                                                          ^
 164
 165 //==============================================================================
 166 // expected a closing parenthesis
 167
 168 s_sendmsg sendmsg(2, 2, 0, 0)
 169 // CHECK: error: expected a closing parenthesis
 170 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(2, 2, 0, 0)
 171 // CHECK-NEXT:{{^}}                         ^
 172
 173 s_waitcnt vmcnt(0
 174 // CHECK: error: expected a closing parenthesis
 175 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(0
 176 // CHECK-NEXT:{{^}}                 ^
 177
 178 //==============================================================================
 179 // expected a closing square bracket
 180
 181 s_mov_b32 s1, s[0 1
 182 // CHECK: error: expected a closing square bracket
 183 // CHECK-NEXT:{{^}}s_mov_b32 s1, s[0 1
 184 // CHECK-NEXT:{{^}}                  ^
 185
 186 s_mov_b32 s1, s[0 s0
 187 // CHECK: error: expected a closing square bracket
 188 // CHECK-NEXT:{{^}}s_mov_b32 s1, s[0 s0
 189 // CHECK-NEXT:{{^}}                  ^
 190
 191 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT_32,BUF_NUM_FORMAT_FLOAT,BUF_DATA_FORMAT_8]
 192 // CHECK: error: expected a closing square bracket
 193 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT_32,BUF_NUM_FORMAT_FLOAT,BUF_DATA_FORMAT_8]
 194 // CHECK-NEXT:{{^}}                                                                                                    ^
 195
 196 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_NUM_FORMAT_UINT
 197 // CHECK: error: expected a closing square bracket
 198 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_NUM_FORMAT_UINT
 199 // CHECK-NEXT:{{^}}                                                                                ^
 200
 201 v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1 1
 202 // CHECK: error: expected a closing square bracket
 203 // CHECK-NEXT:{{^}}v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1 1
 204 // CHECK-NEXT:{{^}}                                          ^
 205
 206 v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1,
 207 // CHECK: error: expected a closing square bracket
 208 // CHECK-NEXT:{{^}}v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1,
 209 // CHECK-NEXT:{{^}}                                         ^
 210
 211 v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1[
 212 // CHECK: error: expected a closing square bracket
 213 // CHECK-NEXT:{{^}}v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1[
 214 // CHECK-NEXT:{{^}}                                         ^
 215
 216 v_pk_add_u16 v1, v2, v3 op_sel:[0,0,0,0,0]
 217 // CHECK: error: expected a closing square bracket
 218 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[0,0,0,0,0]
 219 // CHECK-NEXT:{{^}}                                       ^
 220
 221 v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7)
 222 // CHECK: error: expected a closing square bracket
 223 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7)
 224 // CHECK-NEXT:{{^}}                                          ^
 225
 226 v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0) row_mask:0x0 bank_mask:0x0
 227 // CHECK: error: expected a closing square bracket
 228 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0) row_mask:0x0 bank_mask:0x0
 229 // CHECK-NEXT:{{^}}                                       ^
 230
 231 //==============================================================================
 232 // expected a colon
 233
 234 ds_swizzle_b32 v8, v2 offset
 235 // CHECK: error: expected a colon
 236 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset
 237 // CHECK-NEXT:{{^}}                            ^
 238
 239 ds_swizzle_b32 v8, v2 offset-
 240 // CHECK: error: expected a colon
 241 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset-
 242 // CHECK-NEXT:{{^}}                            ^
 243
 244 //==============================================================================
 245 // expected a comma
 246
 247 ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM
 248 // CHECK: error: expected a comma
 249 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM
 250 // CHECK-NEXT:{{^}}                                              ^
 251
 252 ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2)
 253 // CHECK: error: expected a comma
 254 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2)
 255 // CHECK-NEXT:{{^}}                                                       ^
 256
 257 s_setreg_b32  hwreg(1,2 3), s2
 258 // CHECK: error: expected a comma
 259 // CHECK-NEXT:{{^}}s_setreg_b32  hwreg(1,2 3), s2
 260 // CHECK-NEXT:{{^}}                        ^
 261
 262 v_pk_add_u16 v1, v2, v3 op_sel:[0 0]
 263 // CHECK: error: expected a comma
 264 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[0 0]
 265 // CHECK-NEXT:{{^}}                                  ^
 266
 267 v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6]
 268 // CHECK: error: expected a comma
 269 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6]
 270 // CHECK-NEXT:{{^}}                                        ^
 271
 272 v_mov_b32_dpp v5, v1 quad_perm:[3,2] row_mask:0x0 bank_mask:0x0
 273 // CHECK: error: expected a comma
 274 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:[3,2] row_mask:0x0 bank_mask:0x0
 275 // CHECK-NEXT:{{^}}                                   ^
 276
 277 //==============================================================================
 278 // expected a comma or a closing parenthesis
 279
 280 s_setreg_b32  hwreg(1 2,3), s2
 281 // CHECK: error: expected a comma or a closing parenthesis
 282 // CHECK-NEXT:{{^}}s_setreg_b32  hwreg(1 2,3), s2
 283 // CHECK-NEXT:{{^}}                      ^
 284
 285 //==============================================================================
 286 // expected a comma or a closing square bracket
 287
 288 s_mov_b64 s[10:11], [s0
 289 // CHECK: error: expected a comma or a closing square bracket
 290 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s0
 291 // CHECK-NEXT:{{^}}                       ^
 292
 293 s_mov_b64 s[10:11], [s0,s1
 294 // CHECK: error: expected a comma or a closing square bracket
 295 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s0,s1
 296 // CHECK-NEXT:{{^}}                          ^
 297
 298 image_load_mip v[253:255], [v255, v254 dmask:0xe dim:1D
 299 // CHECK: error: expected a comma or a closing square bracket
 300 // CHECK-NEXT:{{^}}image_load_mip v[253:255], [v255, v254 dmask:0xe dim:1D
 301 // CHECK-NEXT:{{^}}                                       ^
 302
 303 image_load_mip v[253:255], [v255, v254
 304 // CHECK: error: expected a comma or a closing square bracket
 305 // CHECK-NEXT:{{^}}image_load_mip v[253:255], [v255, v254
 306 // CHECK-NEXT:{{^}}                                      ^
 307
 308 //==============================================================================
 309 // expected a counter name
 310
 311 s_waitcnt vmcnt(0) & expcnt(0) & 1
 312 // CHECK: error: expected a counter name
 313 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) & 1
 314 // CHECK-NEXT:{{^}}                                 ^
 315
 316 s_waitcnt vmcnt(0) & expcnt(0) & lgkmcnt(0)&
 317 // CHECK: error: expected a counter name
 318 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) & lgkmcnt(0)&
 319 // CHECK-NEXT:{{^}}                                            ^
 320
 321 s_waitcnt vmcnt(0) & expcnt(0) 1
 322 // CHECK: error: expected a counter name
 323 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) 1
 324 // CHECK-NEXT:{{^}}                               ^
 325
 326 s_waitcnt vmcnt(0), expcnt(0), lgkmcnt(0),
 327 // CHECK: error: expected a counter name
 328 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(0), expcnt(0), lgkmcnt(0),
 329 // CHECK-NEXT:{{^}}                                          ^
 330
 331 //==============================================================================
 332 // expected a format string
 333
 334 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[]
 335 // CHECK: error: expected a format string
 336 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[]
 337 // CHECK-NEXT:{{^}}                                                             ^
 338
 339 //==============================================================================
 340 // expected a left parenthesis
 341
 342 s_waitcnt vmcnt(0) & expcnt(0) & x
 343 // CHECK: error: expected a left parenthesis
 344 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) & x
 345 // CHECK-NEXT:{{^}}                                  ^
 346
 347 //==============================================================================
 348 // expected a left square bracket
 349
 350 v_pk_add_u16 v1, v2, v3 op_sel:
 351 // CHECK: error: expected a left square bracket
 352 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:
 353 // CHECK-NEXT:{{^}}                               ^
 354
 355 //==============================================================================
 356 // expected a register
 357
 358 image_load v[0:3], [v4, v5, 6], s[8:15] dmask:0xf dim:3D unorm
 359 // CHECK: error: expected a register
 360 // CHECK-NEXT:{{^}}image_load v[0:3], [v4, v5, 6], s[8:15] dmask:0xf dim:3D unorm
 361 // CHECK-NEXT:{{^}}                            ^
 362
 363 image_load v[0:3], [v4, v5, v], s[8:15] dmask:0xf dim:3D unorm
 364 // CHECK: error: expected a register
 365 // CHECK-NEXT:{{^}}image_load v[0:3], [v4, v5, v], s[8:15] dmask:0xf dim:3D unorm
 366 // CHECK-NEXT:{{^}}                            ^
 367
 368 //==============================================================================
 369 // expected a register or a list of registers
 370
 371 s_mov_b32 s1, [s0, 1
 372 // CHECK: error: expected a register or a list of registers
 373 // CHECK-NEXT:{{^}}s_mov_b32 s1, [s0, 1
 374 // CHECK-NEXT:{{^}}                   ^
 375
 376 //==============================================================================
 377 // expected a single 32-bit register
 378
 379 s_mov_b64 s[10:11], [s0,s[2:3]]
 380 // CHECK: error: expected a single 32-bit register
 381 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s0,s[2:3]]
 382 // CHECK-NEXT:{{^}}                        ^
 383
 384 //==============================================================================
 385 // expected a string
 386
 387 ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, pppii)
 388 // CHECK: error: expected a string
 389 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, pppii)
 390 // CHECK-NEXT:{{^}}                                                   ^
 391
 392 //==============================================================================
 393 // expected a swizzle mode
 394
 395 ds_swizzle_b32 v8, v2 offset:swizzle(XXX,1)
 396 // CHECK: error: expected a swizzle mode
 397 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(XXX,1)
 398 // CHECK-NEXT:{{^}}                                     ^
 399
 400 //==============================================================================
 401 // expected absolute expression
 402
 403 s_waitcnt vmcnt(x)
 404 // CHECK: error: expected absolute expression
 405 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(x)
 406 // CHECK-NEXT:{{^}}                ^
 407
 408 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], format:[BUF_DATA_FORMAT_32]
 409 // CHECK: error: expected absolute expression
 410 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], format:[BUF_DATA_FORMAT_32]
 411 // CHECK-NEXT:{{^}}                                                         ^
 412
 413 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format: offset:52
 414 // CHECK: error: expected absolute expression
 415 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format: offset:52
 416 // CHECK-NEXT:{{^}}                                                             ^
 417
 418 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:BUF_NUM_FORMAT_UINT]
 419 // CHECK: error: expected absolute expression
 420 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:BUF_NUM_FORMAT_UINT]
 421 // CHECK-NEXT:{{^}}                                                            ^
 422
 423 v_mov_b32_dpp v5, v1 dpp8:[0,1,2,x,4,5,6,7]
 424 // CHECK: error: expected absolute expression
 425 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,x,4,5,6,7]
 426 // CHECK-NEXT:{{^}}                                 ^
 427
 428 v_mov_b32_dpp v5, v1 quad_perm:[3,x,1,0] row_mask:0x0 bank_mask:0x0
 429 // CHECK: error: expected absolute expression
 430 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:[3,x,1,0] row_mask:0x0 bank_mask:0x0
 431 // CHECK-NEXT:{{^}}                                  ^
 432
 433 v_mov_b32_dpp v5, v1 row_share:x row_mask:0x0 bank_mask:0x0
 434 // CHECK: error: expected absolute expression
 435 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 row_share:x row_mask:0x0 bank_mask:0x0
 436 // CHECK-NEXT:{{^}}                               ^
 437
 438 //==============================================================================
 439 // expected a message name or an absolute expression
 440
 441 s_sendmsg sendmsg(MSG_GSX, GS_OP_CUT, 0)
 442 // CHECK: error: expected a message name or an absolute expression
 443 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GSX, GS_OP_CUT, 0)
 444 // CHECK-NEXT:{{^}}                  ^
 445
 446 //==============================================================================
 447 // expected a register name or an absolute expression
 448
 449 s_setreg_b32  hwreg(HW_REG_WRONG), s2
 450 // CHECK: error: expected a register name or an absolute expression
 451 // CHECK-NEXT:{{^}}s_setreg_b32  hwreg(HW_REG_WRONG), s2
 452 // CHECK-NEXT:{{^}}                    ^
 453
 454 //==============================================================================
 455 // expected a sendmsg macro or an absolute expression
 456
 457 s_sendmsg undef
 458 // CHECK: error: expected a sendmsg macro or an absolute expression
 459 // CHECK-NEXT:{{^}}s_sendmsg undef
 460 // CHECK-NEXT:{{^}}          ^
 461
 462 //==============================================================================
 463 // expected a swizzle macro or an absolute expression
 464
 465 ds_swizzle_b32 v8, v2 offset:SWZ(QUAD_PERM, 0, 1, 2, 3)
 466 // CHECK: error: expected a swizzle macro or an absolute expression
 467 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:SWZ(QUAD_PERM, 0, 1, 2, 3)
 468 // CHECK-NEXT:{{^}}                             ^
 469
 470 //==============================================================================
 471 // expected a hwreg macro or an absolute expression
 472
 473 s_setreg_b32 undef, s2
 474 // CHECK: error: expected a hwreg macro or an absolute expression
 475 // CHECK-NEXT:{{^}}s_setreg_b32 undef, s2
 476 // CHECK-NEXT:{{^}}             ^
 477
 478 //==============================================================================
 479 // expected an 11-bit unsigned offset
 480
 481 flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc
 482 // CHECK: error: expected a 11-bit unsigned offset
 483 // CHECK-NEXT:{{^}}flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc
 484 // CHECK-NEXT:{{^}}                                       ^
 485
 486 //==============================================================================
 487 // expected an absolute expression
 488
 489 v_ceil_f32 v1, abs(u)
 490 // CHECK: error: expected an absolute expression
 491 // CHECK-NEXT:{{^}}v_ceil_f32 v1, abs(u)
 492 // CHECK-NEXT:{{^}}                   ^
 493
 494 v_ceil_f32 v1, neg(u)
 495 // CHECK: error: expected an absolute expression
 496 // CHECK-NEXT:{{^}}v_ceil_f32 v1, neg(u)
 497 // CHECK-NEXT:{{^}}                   ^
 498
 499 v_ceil_f32 v1, |u|
 500 // CHECK: error: expected an absolute expression
 501 // CHECK-NEXT:{{^}}v_ceil_f32 v1, |u|
 502 // CHECK-NEXT:{{^}}                ^
 503
 504 v_mov_b32_sdwa v1, sext(u)
 505 // CHECK: error: expected an absolute expression
 506 // CHECK-NEXT:{{^}}v_mov_b32_sdwa v1, sext(u)
 507 // CHECK-NEXT:{{^}}                        ^
 508
 509 //==============================================================================
 510 // expected an identifier
 511
 512 v_mov_b32_sdwa v5, v1 dst_sel:
 513 // CHECK: error: expected an identifier
 514 // CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:
 515 // CHECK-NEXT:{{^}}                              ^
 516
 517 v_mov_b32_sdwa v5, v1 dst_sel:0
 518 // CHECK: error: expected an identifier
 519 // CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:0
 520 // CHECK-NEXT:{{^}}                              ^
 521
 522 v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:[UNUSED_PAD]
 523 // CHECK: error: expected an identifier
 524 // CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:[UNUSED_PAD]
 525 // CHECK-NEXT:{{^}}                                               ^
 526
 527 //==============================================================================
 528 // expected an opening square bracket
 529
 530 v_mov_b32_dpp v5, v1 dpp8:(0,1,2,3,4,5,6,7)
 531 // CHECK: error: expected an opening square bracket
 532 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:(0,1,2,3,4,5,6,7)
 533 // CHECK-NEXT:{{^}}                          ^
 534
 535 v_mov_b32_dpp v5, v1 quad_perm:(3,2,1,0) row_mask:0x0 bank_mask:0x0
 536 // CHECK: error: expected an opening square bracket
 537 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:(3,2,1,0) row_mask:0x0 bank_mask:0x0
 538 // CHECK-NEXT:{{^}}                               ^
 539
 540 //==============================================================================
 541 // expected an operation name or an absolute expression
 542
 543 s_sendmsg sendmsg(MSG_GS, GS_OP_CUTX, 0)
 544 // CHECK: error: expected an operation name or an absolute expression
 545 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS, GS_OP_CUTX, 0)
 546 // CHECK-NEXT:{{^}}                          ^
 547
 548 //==============================================================================
 549 // failed parsing operand.
 550
 551 v_ceil_f16 v0, abs(neg(1))
 552 // CHECK: error: failed parsing operand.
 553 // CHECK-NEXT:{{^}}v_ceil_f16 v0, abs(neg(1))
 554 // CHECK-NEXT:{{^}}                   ^
 555
 556 //==============================================================================
 557 // first register index should not exceed second index
 558
 559 s_mov_b64 s[10:11], s[1:0]
 560 // CHECK: error: first register index should not exceed second index
 561 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], s[1:0]
 562 // CHECK-NEXT:{{^}}                      ^
 563
 564 //==============================================================================
 565 // group size must be a power of two
 566
 567 ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,3,1)
 568 // CHECK: error: group size must be a power of two
 569 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,3,1)
 570 // CHECK-NEXT:{{^}}                                               ^
 571
 572 ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,3)
 573 // CHECK: error: group size must be a power of two
 574 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,3)
 575 // CHECK-NEXT:{{^}}                                             ^
 576
 577 ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,3)
 578 // CHECK: error: group size must be a power of two
 579 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,3)
 580 // CHECK-NEXT:{{^}}                                          ^
 581
 582 //==============================================================================
 583 // group size must be in the interval [1,16]
 584
 585 ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,0)
 586 // CHECK: error: group size must be in the interval [1,16]
 587 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,0)
 588 // CHECK-NEXT:{{^}}                                          ^
 589
 590 //==============================================================================
 591 // group size must be in the interval [2,32]
 592
 593 ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,1,0)
 594 // CHECK: error: group size must be in the interval [2,32]
 595 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,1,0)
 596 // CHECK-NEXT:{{^}}                                               ^
 597
 598 //==============================================================================
 599 // image address size does not match dim and a16
 600
 601 image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D
 602 // CHECK: error: image address size does not match dim and a16
 603 // CHECK-NEXT:{{^}}image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D
 604 // CHECK-NEXT:{{^}}^
 605
 606 //==============================================================================
 607 // image data size does not match dmask and tfe
 608
 609 image_load v[0:1], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
 610 // CHECK: error: image data size does not match dmask and tfe
 611 // CHECK-NEXT:{{^}}image_load v[0:1], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
 612 // CHECK-NEXT:{{^}}^
 613
 614 //==============================================================================
 615 // instruction must use glc
 616
 617 flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:2047
 618 // CHECK: error: instruction must use glc
 619 // CHECK-NEXT:{{^}}flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:2047
 620 // CHECK-NEXT:{{^}}^
 621
 622 //==============================================================================
 623 // instruction not supported on this GPU
 624
 625 s_cbranch_join 1
 626 // CHECK: error: instruction not supported on this GPU
 627 // CHECK-NEXT:{{^}}s_cbranch_join 1
 628 // CHECK-NEXT:{{^}}^
 629
 630 //==============================================================================
 631 // invalid bit offset: only 5-bit values are legal
 632
 633 s_getreg_b32  s2, hwreg(3,32,32)
 634 // CHECK: error: invalid bit offset: only 5-bit values are legal
 635 // CHECK-NEXT:{{^}}s_getreg_b32  s2, hwreg(3,32,32)
 636 // CHECK-NEXT:{{^}}                          ^
 637
 638 //==============================================================================
 639 // invalid bitfield width: only values from 1 to 32 are legal
 640
 641 s_setreg_b32  hwreg(3,0,33), s2
 642 // CHECK: error: invalid bitfield width: only values from 1 to 32 are legal
 643 // CHECK-NEXT:{{^}}s_setreg_b32  hwreg(3,0,33), s2
 644 // CHECK-NEXT:{{^}}                        ^
 645
 646 //==============================================================================
 647 // invalid code of hardware register: only 6-bit values are legal
 648
 649 s_setreg_b32  hwreg(0x40), s2
 650 // CHECK: error: invalid code of hardware register: only 6-bit values are legal
 651 // CHECK-NEXT:{{^}}s_setreg_b32  hwreg(0x40), s2
 652 // CHECK-NEXT:{{^}}                    ^
 653
 654 //==============================================================================
 655 // invalid counter name x
 656
 657 s_waitcnt vmcnt(0) & expcnt(0) x(0)
 658 // CHECK: error: invalid counter name x
 659 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) x(0)
 660 // CHECK-NEXT:{{^}}                               ^
 661
 662 //==============================================================================
 663 // invalid dim value
 664
 665 image_load v[0:1], v0, s[0:7] dmask:0x9 dim:1 D
 666 // CHECK: error: invalid dim value
 667 // CHECK-NEXT:{{^}}image_load v[0:1], v0, s[0:7] dmask:0x9 dim:1 D
 668 // CHECK-NEXT:{{^}}                                            ^
 669
 670 image_atomic_xor v4, v32, s[96:103] dmask:0x1 dim:, glc
 671 // CHECK: error: invalid dim value
 672 // CHECK-NEXT:{{^}}image_atomic_xor v4, v32, s[96:103] dmask:0x1 dim:, glc
 673 // CHECK-NEXT:{{^}}                                                  ^
 674
 675 image_load v[0:1], v0, s[0:7] dmask:0x9 dim:7D
 676 // CHECK: error: invalid dim value
 677 // CHECK-NEXT:{{^}}image_load v[0:1], v0, s[0:7] dmask:0x9 dim:7D
 678 // CHECK-NEXT:{{^}}                                            ^
 679
 680 //==============================================================================
 681 // invalid dst_sel value
 682
 683 v_mov_b32_sdwa v5, v1 dst_sel:WORD
 684 // CHECK: error: invalid dst_sel value
 685 // CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:WORD
 686 // CHECK-NEXT:{{^}}                              ^
 687
 688 //==============================================================================
 689 // invalid dst_unused value
 690
 691 v_mov_b32_sdwa v5, v1 dst_unused:UNUSED
 692 // CHECK: error: invalid dst_unused value
 693 // CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_unused:UNUSED
 694 // CHECK-NEXT:{{^}}                                 ^
 695
 696 //==============================================================================
 697 // invalid exp target
 698
 699 exp invalid_target_10 v3, v2, v1, v0
 700 // CHECK: error: invalid exp target
 701 // CHECK-NEXT:{{^}}exp invalid_target_10 v3, v2, v1, v0
 702 // CHECK-NEXT:{{^}}    ^
 703
 704 exp pos00 v3, v2, v1, v0
 705 // CHECK: error: invalid exp target
 706 // CHECK-NEXT:{{^}}exp pos00 v3, v2, v1, v0
 707 // CHECK-NEXT:{{^}}    ^
 708
 709 //==============================================================================
 710 // invalid immediate: only 16-bit values are legal
 711
 712 s_setreg_b32  0x1f803, s2
 713 // CHECK: error: invalid immediate: only 16-bit values are legal
 714 // CHECK-NEXT:{{^}}s_setreg_b32  0x1f803, s2
 715 // CHECK-NEXT:{{^}}              ^
 716
 717 //==============================================================================
 718 // invalid instruction
 719
 720 v_dot_f32_f16 v0, v1, v2
 721 // CHECK: error: invalid instruction
 722 // CHECK-NEXT:{{^}}v_dot_f32_f16 v0, v1, v2
 723 // CHECK-NEXT:{{^}}^
 724
 725 //==============================================================================
 726 // invalid interpolation attribute
 727
 728 v_interp_p2_f32 v0, v1, att
 729 // CHECK: error: invalid interpolation attribute
 730 // CHECK-NEXT:{{^}}v_interp_p2_f32 v0, v1, att
 731 // CHECK-NEXT:{{^}}                        ^
 732
 733 //==============================================================================
 734 // invalid interpolation slot
 735
 736 v_interp_mov_f32 v8, p1, attr0.x
 737 // CHECK: error: invalid interpolation slot
 738 // CHECK-NEXT:{{^}}v_interp_mov_f32 v8, p1, attr0.x
 739 // CHECK-NEXT:{{^}}                     ^
 740
 741 //==============================================================================
 742 // invalid mask
 743
 744 ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "pppi2")
 745 // CHECK: error: invalid mask
 746 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "pppi2")
 747 // CHECK-NEXT:{{^}}                                                   ^
 748
 749 //==============================================================================
 750 // invalid message id
 751
 752 s_sendmsg sendmsg(-1)
 753 // CHECK: error: invalid message id
 754 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(-1)
 755 // CHECK-NEXT:{{^}}                  ^
 756
 757 //==============================================================================
 758 // invalid message stream id
 759
 760 s_sendmsg sendmsg(2, 2, 4)
 761 // CHECK: error: invalid message stream id
 762 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(2, 2, 4)
 763 // CHECK-NEXT:{{^}}                        ^
 764
 765 s_sendmsg sendmsg(MSG_GS, GS_OP_CUT, 4)
 766 // CHECK: error: invalid message stream id
 767 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS, GS_OP_CUT, 4)
 768 // CHECK-NEXT:{{^}}                                     ^
 769
 770 //==============================================================================
 771 // invalid mul value.
 772
 773 v_cvt_f64_i32 v[5:6], s1 mul:3
 774 // CHECK: error: invalid mul value.
 775 // CHECK-NEXT:{{^}}v_cvt_f64_i32 v[5:6], s1 mul:3
 776 // CHECK-NEXT:{{^}}                         ^
 777
 778 //==============================================================================
 779 // invalid or missing interpolation attribute channel
 780
 781 v_interp_p2_f32 v0, v1, attr0.q
 782 // CHECK: error: invalid or missing interpolation attribute channel
 783 // CHECK-NEXT:{{^}}v_interp_p2_f32 v0, v1, attr0.q
 784 // CHECK-NEXT:{{^}}                        ^
 785
 786 //==============================================================================
 787 // invalid or missing interpolation attribute number
 788
 789 v_interp_p2_f32 v7, v1, attr.x
 790 // CHECK: error: invalid or missing interpolation attribute number
 791 // CHECK-NEXT:{{^}}v_interp_p2_f32 v7, v1, attr.x
 792 // CHECK-NEXT:{{^}}                        ^
 793
 794 //==============================================================================
 795 // invalid op_sel operand
 796
 797 v_permlane16_b32 v5, v1, s2, s3 op_sel:[0, 0, 0, 1]
 798 // CHECK: error: invalid op_sel operand
 799 // CHECK-NEXT:{{^}}v_permlane16_b32 v5, v1, s2, s3 op_sel:[0, 0, 0, 1]
 800 // CHECK-NEXT:{{^}}                                ^
 801
 802 //==============================================================================
 803 // invalid op_sel value.
 804
 805 v_pk_add_u16 v1, v2, v3 op_sel:[-1,0]
 806 // CHECK: error: invalid op_sel value.
 807 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[-1,0]
 808 // CHECK-NEXT:{{^}}                                ^
 809
 810 //==============================================================================
 811 // invalid operand (violates constant bus restrictions)
 812
 813 v_ashrrev_i64 v[0:1], 0x100, s[0:1]
 814 // CHECK: error: invalid operand (violates constant bus restrictions)
 815 // CHECK-NEXT:{{^}}v_ashrrev_i64 v[0:1], 0x100, s[0:1]
 816 // CHECK-NEXT:{{^}}                             ^
 817
 818 v_ashrrev_i64 v[0:1], s3, s[0:1]
 819 // CHECK: error: invalid operand (violates constant bus restrictions)
 820 // CHECK-NEXT:{{^}}v_ashrrev_i64 v[0:1], s3, s[0:1]
 821 // CHECK-NEXT:{{^}}                          ^
 822
 823 v_bfe_u32 v0, s1, 0x3039, s2
 824 // CHECK: error: invalid operand (violates constant bus restrictions)
 825 // CHECK-NEXT:{{^}}v_bfe_u32 v0, s1, 0x3039, s2
 826 // CHECK-NEXT:{{^}}                          ^
 827
 828 v_bfe_u32 v0, s1, s2, s3
 829 // CHECK: error: invalid operand (violates constant bus restrictions)
 830 // CHECK-NEXT:{{^}}v_bfe_u32 v0, s1, s2, s3
 831 // CHECK-NEXT:{{^}}                      ^
 832
 833 v_div_fmas_f32 v5, s3, 0x123, v3
 834 // CHECK: error: invalid operand (violates constant bus restrictions)
 835 // CHECK-NEXT:{{^}}v_div_fmas_f32 v5, s3, 0x123, v3
 836 // CHECK-NEXT:{{^}}                       ^
 837
 838 v_div_fmas_f32 v5, s3, v3, 0x123
 839 // CHECK: error: invalid operand (violates constant bus restrictions)
 840 // CHECK-NEXT:{{^}}v_div_fmas_f32 v5, s3, v3, 0x123
 841 // CHECK-NEXT:{{^}}                           ^
 842
 843 v_div_fmas_f32 v5, 0x123, v3, s3
 844 // CHECK: error: invalid operand (violates constant bus restrictions)
 845 // CHECK-NEXT:{{^}}v_div_fmas_f32 v5, 0x123, v3, s3
 846 // CHECK-NEXT:{{^}}                              ^
 847
 848 v_div_fmas_f32 v5, s3, s4, v3
 849 // CHECK: error: invalid operand (violates constant bus restrictions)
 850 // CHECK-NEXT:{{^}}v_div_fmas_f32 v5, s3, s4, v3
 851 // CHECK-NEXT:{{^}}                       ^
 852
 853 //==============================================================================
 854 // invalid operand for instruction
 855
 856 buffer_load_dword v5, off, s[8:11], s3 tfe lds
 857 // CHECK: error: invalid operand for instruction
 858 // CHECK-NEXT:{{^}}buffer_load_dword v5, off, s[8:11], s3 tfe lds
 859 // CHECK-NEXT:{{^}}                                           ^
 860
 861 exp mrt0 0x12345678, v0, v0, v0
 862 // CHECK: error: invalid operand for instruction
 863 // CHECK-NEXT:{{^}}exp mrt0 0x12345678, v0, v0, v0
 864 // CHECK-NEXT:{{^}}         ^
 865
 866 v_cmp_eq_f32 s[0:1], private_base, s0
 867 // CHECK: error: invalid operand for instruction
 868 // CHECK-NEXT:{{^}}v_cmp_eq_f32 s[0:1], private_base, s0
 869 // CHECK-NEXT:{{^}}             ^
 870
 871 //==============================================================================
 872 // invalid operation id
 873
 874 s_sendmsg sendmsg(15, -1)
 875 // CHECK: error: invalid operation id
 876 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(15, -1)
 877 // CHECK-NEXT:{{^}}                      ^
 878
 879 //==============================================================================
 880 // invalid or unsupported register size
 881
 882 s_mov_b64 s[0:17], -1
 883 // CHECK: error: invalid or unsupported register size
 884 // CHECK-NEXT:{{^}}s_mov_b64 s[0:17], -1
 885 // CHECK-NEXT:{{^}}          ^
 886
 887 //==============================================================================
 888 // invalid register alignment
 889
 890 s_load_dwordx4 s[1:4], s[2:3], s4
 891 // CHECK: error: invalid register alignment
 892 // CHECK-NEXT:{{^}}s_load_dwordx4 s[1:4], s[2:3], s4
 893 // CHECK-NEXT:{{^}}               ^
 894
 895 //==============================================================================
 896 // invalid register index
 897
 898 s_mov_b32 s1, s[0:-1]
 899 // CHECK: error: invalid register index
 900 // CHECK-NEXT:{{^}}s_mov_b32 s1, s[0:-1]
 901 // CHECK-NEXT:{{^}}                  ^
 902
 903 v_add_f64 v[0:1], v[0:1], v[0xF00000001:0x2]
 904 // CHECK: error: invalid register index
 905 // CHECK-NEXT:{{^}}v_add_f64 v[0:1], v[0:1], v[0xF00000001:0x2]
 906 // CHECK-NEXT:{{^}}                            ^
 907
 908 //==============================================================================
 909 // invalid register name
 910
 911 s_mov_b64 s[10:11], [x0,s1]
 912 // CHECK: error: invalid register name
 913 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [x0,s1]
 914 // CHECK-NEXT:{{^}}                     ^
 915
 916 //==============================================================================
 917 // invalid row_share value
 918
 919 v_mov_b32_dpp v5, v1 row_share:16 row_mask:0x0 bank_mask:0x0
 920 // CHECK: error: invalid row_share value
 921 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 row_share:16 row_mask:0x0 bank_mask:0x0
 922 // CHECK-NEXT:{{^}}                               ^
 923
 924 v_mov_b32_dpp v5, v1 row_share:-1 row_mask:0x0 bank_mask:0x0
 925 // CHECK: error: invalid row_share value
 926 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 row_share:-1 row_mask:0x0 bank_mask:0x0
 927 // CHECK-NEXT:{{^}}                               ^
 928
 929 //==============================================================================
 930 // invalid syntax, expected 'neg' modifier
 931
 932 v_ceil_f32 v0, --1
 933 // CHECK: error: invalid syntax, expected 'neg' modifier
 934 // CHECK-NEXT:{{^}}v_ceil_f32 v0, --1
 935 // CHECK-NEXT:{{^}}               ^
 936
 937 //==============================================================================
 938 // lane id must be in the interval [0,group size - 1]
 939
 940 ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,2,-1)
 941 // CHECK: error: lane id must be in the interval [0,group size - 1]
 942 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,2,-1)
 943 // CHECK-NEXT:{{^}}                                                 ^
 944
 945 //==============================================================================
 946 // lds_direct cannot be used with this instruction
 947
 948 v_ashrrev_i16 v0, lds_direct, v0
 949 // CHECK: error: lds_direct cannot be used with this instruction
 950 // CHECK-NEXT:{{^}}v_ashrrev_i16 v0, lds_direct, v0
 951 // CHECK-NEXT:{{^}}                  ^
 952
 953 v_ashrrev_i16 v0, v1, lds_direct
 954 // CHECK: error: lds_direct cannot be used with this instruction
 955 // CHECK-NEXT:{{^}}v_ashrrev_i16 v0, v1, lds_direct
 956 // CHECK-NEXT:{{^}}                      ^
 957
 958 v_mov_b32_sdwa v1, src_lds_direct dst_sel:DWORD
 959 // CHECK: error: lds_direct cannot be used with this instruction
 960 // CHECK-NEXT:{{^}}v_mov_b32_sdwa v1, src_lds_direct dst_sel:DWORD
 961 // CHECK-NEXT:{{^}}                   ^
 962
 963 v_add_f32_sdwa v5, v1, lds_direct dst_sel:DWORD
 964 // CHECK: error: lds_direct cannot be used with this instruction
 965 // CHECK-NEXT:{{^}}v_add_f32_sdwa v5, v1, lds_direct dst_sel:DWORD
 966 // CHECK-NEXT:{{^}}                       ^
 967
 968 //==============================================================================
 969 // lds_direct may be used as src0 only
 970
 971 v_add_f32 v5, v1, lds_direct
 972 // CHECK: error: lds_direct may be used as src0 only
 973 // CHECK-NEXT:{{^}}v_add_f32 v5, v1, lds_direct
 974 // CHECK-NEXT:{{^}}                  ^
 975
 976 //==============================================================================
 977 // message does not support operations
 978
 979 s_sendmsg sendmsg(MSG_GS_ALLOC_REQ, 0)
 980 // CHECK: error: message does not support operations
 981 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS_ALLOC_REQ, 0)
 982 // CHECK-NEXT:{{^}}                                    ^
 983
 984 //==============================================================================
 985 // message operation does not support streams
 986
 987 s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP, 0)
 988 // CHECK: error: message operation does not support streams
 989 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP, 0)
 990 // CHECK-NEXT:{{^}}                                          ^
 991
 992 //==============================================================================
 993 // missing message operation
 994
 995 s_sendmsg sendmsg(MSG_SYSMSG)
 996 // CHECK: error: missing message operation
 997 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_SYSMSG)
 998 // CHECK-NEXT:{{^}}                  ^
 999
1000 //==============================================================================
1001 // missing register index
1002
1003 s_mov_b64 s[10:11], [s
1004 // CHECK: error: missing register index
1005 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s
1006 // CHECK-NEXT:{{^}}                      ^
1007
1008 s_mov_b64 s[10:11], [s,s1]
1009 // CHECK: error: missing register index
1010 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s,s1]
1011 // CHECK-NEXT:{{^}}                      ^
1012
1013 //==============================================================================
1014 // not a valid operand.
1015
1016 s_branch offset:1
1017 // CHECK: error: not a valid operand.
1018 // CHECK-NEXT:{{^}}s_branch offset:1
1019 // CHECK-NEXT:{{^}}         ^
1020
1021 v_mov_b32 v0, v0 row_bcast:0
1022 // CHECK: error: not a valid operand.
1023 // CHECK-NEXT:{{^}}v_mov_b32 v0, v0 row_bcast:0
1024 // CHECK-NEXT:{{^}}                 ^
1025
1026 //==============================================================================
1027 // only one literal operand is allowed
1028
1029 s_and_b32 s2, 0x12345678, 0x12345679
1030 // CHECK: error: only one literal operand is allowed
1031 // CHECK-NEXT:{{^}}s_and_b32 s2, 0x12345678, 0x12345679
1032 // CHECK-NEXT:{{^}}                          ^
1033
1034 v_add_f64 v[0:1], 1.23456, -abs(1.2345)
1035 // CHECK: error: only one literal operand is allowed
1036 // CHECK-NEXT:{{^}}v_add_f64 v[0:1], 1.23456, -abs(1.2345)
1037 // CHECK-NEXT:{{^}}                                ^
1038
1039 v_min3_i16 v5, 0x5678, 0x5678, 0x5679
1040 // CHECK: error: only one literal operand is allowed
1041 // CHECK-NEXT:{{^}}v_min3_i16 v5, 0x5678, 0x5678, 0x5679
1042 // CHECK-NEXT:{{^}}                               ^
1043
1044 v_pk_add_f16 v1, 25.0, 25.1
1045 // CHECK: error: only one literal operand is allowed
1046 // CHECK-NEXT:{{^}}v_pk_add_f16 v1, 25.0, 25.1
1047 // CHECK-NEXT:{{^}}                       ^
1048
1049 v_fma_mix_f32 v5, 0x7c, 0x7b, 1
1050 // CHECK: error: only one literal operand is allowed
1051 // CHECK-NEXT:{{^}}v_fma_mix_f32 v5, 0x7c, 0x7b, 1
1052 // CHECK-NEXT:{{^}}                        ^
1053
1054 v_pk_add_i16 v5, 0x7c, 0x4000
1055 // CHECK: error: only one literal operand is allowed
1056 // CHECK-NEXT:{{^}}v_pk_add_i16 v5, 0x7c, 0x4000
1057 // CHECK-NEXT:{{^}}                       ^
1058
1059 v_pk_add_i16 v5, 0x4400, 0x4000
1060 // CHECK: error: only one literal operand is allowed
1061 // CHECK-NEXT:{{^}}v_pk_add_i16 v5, 0x4400, 0x4000
1062 // CHECK-NEXT:{{^}}                         ^
1063
1064 v_bfe_u32 v0, v2, 123, undef
1065 // CHECK: error: only one literal operand is allowed
1066 // CHECK-NEXT:{{^}}v_bfe_u32 v0, v2, 123, undef
1067 // CHECK-NEXT:{{^}}                       ^
1068
1069 v_bfe_u32 v0, v2, undef, 123
1070 // CHECK: error: only one literal operand is allowed
1071 // CHECK-NEXT:{{^}}v_bfe_u32 v0, v2, undef, 123
1072 // CHECK-NEXT:{{^}}                         ^
1073
1074 //==============================================================================
1075 // out of bounds interpolation attribute number
1076
1077 v_interp_p1_f32 v0, v1, attr64.w
1078 // CHECK: error: out of bounds interpolation attribute number
1079 // CHECK-NEXT:{{^}}v_interp_p1_f32 v0, v1, attr64.w
1080 // CHECK-NEXT:{{^}}                        ^
1081
1082 //==============================================================================
1083 // out of range format
1084
1085 tbuffer_load_format_d16_x v0, off, s[0:3], format:-1, 0
1086 // CHECK: error: out of range format
1087 // CHECK-NEXT:{{^}}tbuffer_load_format_d16_x v0, off, s[0:3], format:-1, 0
1088 // CHECK-NEXT:{{^}}                                           ^
1089
1090 //==============================================================================
1091 // register does not fit in the list
1092
1093 s_mov_b64 s[10:11], [exec,exec_lo]
1094 // CHECK: error: register does not fit in the list
1095 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [exec,exec_lo]
1096 // CHECK-NEXT:{{^}}                          ^
1097
1098 s_mov_b64 s[10:11], [exec_lo,exec]
1099 // CHECK: error: register does not fit in the list
1100 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [exec_lo,exec]
1101 // CHECK-NEXT:{{^}}                             ^
1102
1103 //==============================================================================
1104 // register index is out of range
1105
1106 s_add_i32 s106, s0, s1
1107 // CHECK: error: register index is out of range
1108 // CHECK-NEXT:{{^}}s_add_i32 s106, s0, s1
1109 // CHECK-NEXT:{{^}}          ^
1110
1111 s_load_dwordx16 s[100:115], s[2:3], s4
1112 // CHECK: error: register index is out of range
1113 // CHECK-NEXT:{{^}}s_load_dwordx16 s[100:115], s[2:3], s4
1114 // CHECK-NEXT:{{^}}                ^
1115
1116 s_mov_b32 ttmp16, 0
1117 // CHECK: error: register index is out of range
1118 // CHECK-NEXT:{{^}}s_mov_b32 ttmp16, 0
1119 // CHECK-NEXT:{{^}}          ^
1120
1121 v_add_nc_i32 v256, v0, v1
1122 // CHECK: error: register index is out of range
1123 // CHECK-NEXT:{{^}}v_add_nc_i32 v256, v0, v1
1124 // CHECK-NEXT:{{^}}             ^
1125
1126 //==============================================================================
1127 // register not available on this GPU
1128
1129 s_and_b32     ttmp9, tma_hi, 0x0000ffff
1130 // CHECK: error: register not available on this GPU
1131 // CHECK-NEXT:{{^}}s_and_b32     ttmp9, tma_hi, 0x0000ffff
1132 // CHECK-NEXT:{{^}}                     ^
1133
1134 s_mov_b32 flat_scratch, -1
1135 // CHECK: error: register not available on this GPU
1136 // CHECK-NEXT:{{^}}s_mov_b32 flat_scratch, -1
1137 // CHECK-NEXT:{{^}}          ^
1138
1139 //==============================================================================
1140 // registers in a list must be of the same kind
1141
1142 s_mov_b64 s[10:11], [a0,v1]
1143 // CHECK: error: registers in a list must be of the same kind
1144 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [a0,v1]
1145 // CHECK-NEXT:{{^}}                        ^
1146
1147 //==============================================================================
1148 // registers in a list must have consecutive indices
1149
1150 s_mov_b64 s[10:11], [a0,a2]
1151 // CHECK: error: registers in a list must have consecutive indices
1152 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [a0,a2]
1153 // CHECK-NEXT:{{^}}                        ^
1154
1155 s_mov_b64 s[10:11], [s0,s0]
1156 // CHECK: error: registers in a list must have consecutive indices
1157 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s0,s0]
1158 // CHECK-NEXT:{{^}}                        ^
1159
1160 s_mov_b64 s[10:11], [s2,s1]
1161 // CHECK: error: registers in a list must have consecutive indices
1162 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s2,s1]
1163 // CHECK-NEXT:{{^}}                        ^
1164
1165 //==============================================================================
1166 // source operand must be a VGPR
1167
1168 v_movrels_b32_sdwa v0, 1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
1169 // CHECK: error: source operand must be a VGPR
1170 // CHECK-NEXT:{{^}}v_movrels_b32_sdwa v0, 1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
1171 // CHECK-NEXT:{{^}}                       ^
1172
1173 v_movrels_b32_sdwa v0, s0
1174 // CHECK: error: source operand must be a VGPR
1175 // CHECK-NEXT:{{^}}v_movrels_b32_sdwa v0, s0
1176 // CHECK-NEXT:{{^}}                       ^
1177
1178 v_movrels_b32_sdwa v0, shared_base
1179 // CHECK: error: source operand must be a VGPR
1180 // CHECK-NEXT:{{^}}v_movrels_b32_sdwa v0, shared_base
1181 // CHECK-NEXT:{{^}}                       ^
1182
1183 //==============================================================================
1184 // specified hardware register is not supported on this GPU
1185
1186 s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES)
1187 // CHECK: error: specified hardware register is not supported on this GPU
1188 // CHECK-NEXT:{{^}}s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES)
1189 // CHECK-NEXT:{{^}}                       ^
1190
1191 //==============================================================================
1192 // too few operands for instruction
1193
1194 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7]
1195 // CHECK: error: too few operands for instruction
1196 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7]
1197 // CHECK-NEXT:{{^}}^
1198
1199 v_add_f32_e64 v0, v1
1200 // CHECK: error: too few operands for instruction
1201 // CHECK-NEXT:{{^}}v_add_f32_e64 v0, v1
1202 // CHECK-NEXT:{{^}}^
1203
1204 //==============================================================================
1205 // too large value for expcnt
1206
1207 s_waitcnt expcnt(8)
1208 // CHECK: error: too large value for expcnt
1209 // CHECK-NEXT:{{^}}s_waitcnt expcnt(8)
1210 // CHECK-NEXT:{{^}}                 ^
1211
1212 //==============================================================================
1213 // too large value for lgkmcnt
1214
1215 s_waitcnt lgkmcnt(64)
1216 // CHECK: error: too large value for lgkmcnt
1217 // CHECK-NEXT:{{^}}s_waitcnt lgkmcnt(64)
1218 // CHECK-NEXT:{{^}}                  ^
1219
1220 //==============================================================================
1221 // too large value for vmcnt
1222
1223 s_waitcnt vmcnt(64)
1224 // CHECK: error: too large value for vmcnt
1225 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(64)
1226 // CHECK-NEXT:{{^}}                ^
1227
1228 //==============================================================================
1229 // unknown token in expression
1230
1231 ds_swizzle_b32 v8, v2 offset:
1232 // CHECK: error: unknown token in expression
1233 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:
1234 // CHECK-NEXT:{{^}}                             ^
1235
1236 s_sendmsg sendmsg(1 -)
1237 // CHECK: error: unknown token in expression
1238 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(1 -)
1239 // CHECK-NEXT:{{^}}                     ^
1240
1241 tbuffer_load_format_d16_x v0, off, s[0:3], format:1,, s0
1242 // CHECK: error: unknown token in expression
1243 // CHECK-NEXT:{{^}}tbuffer_load_format_d16_x v0, off, s[0:3], format:1,, s0
1244 // CHECK-NEXT:{{^}}                                                    ^
1245
1246 tbuffer_load_format_d16_x v0, off, s[0:3], format:1:, s0
1247 // CHECK: error: unknown token in expression
1248 // CHECK-NEXT:{{^}}tbuffer_load_format_d16_x v0, off, s[0:3], format:1:, s0
1249 // CHECK-NEXT:{{^}}                                                   ^
1250
1251 v_pk_add_u16 v1, v2, v3 op_sel:[
1252 // CHECK: error: unknown token in expression
1253 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[
1254 // CHECK-NEXT:{{^}}                                ^
1255
1256 v_pk_add_u16 v1, v2, v3 op_sel:[,0]
1257 // CHECK: error: unknown token in expression
1258 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[,0]
1259 // CHECK-NEXT:{{^}}                                ^
1260
1261 v_pk_add_u16 v1, v2, v3 op_sel:[,]
1262 // CHECK: error: unknown token in expression
1263 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[,]
1264 // CHECK-NEXT:{{^}}                                ^
1265
1266 v_pk_add_u16 v1, v2, v3 op_sel:[0,]
1267 // CHECK: error: unknown token in expression
1268 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[0,]
1269 // CHECK-NEXT:{{^}}                                  ^
1270
1271 v_pk_add_u16 v1, v2, v3 op_sel:[]
1272 // CHECK: error: unknown token in expression
1273 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[]
1274 // CHECK-NEXT:{{^}}                                ^
1275
1276 //==============================================================================
1277 // unsupported format
1278
1279 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT]
1280 // CHECK: error: unsupported format
1281 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT]
1282 // CHECK-NEXT:{{^}}                                                             ^
1283
1284 //==============================================================================
1285 // expected vertical bar
1286
1287 v_ceil_f32 v1, |1+1|
1288 // CHECK: error: expected vertical bar
1289 // CHECK-NEXT:{{^}}v_ceil_f32 v1, |1+1|
1290 // CHECK-NEXT:{{^}}                 ^
1291
1292 //==============================================================================
1293 // expected left paren after neg
1294
1295 v_ceil_f32 v1, neg-(v2)
1296 // CHECK: error: expected left paren after neg
1297 // CHECK-NEXT:{{^}}v_ceil_f32 v1, neg-(v2)
1298 // CHECK-NEXT:{{^}}                  ^
1299
1300 //==============================================================================
1301 // expected left paren after abs
1302
1303 v_ceil_f32 v1, abs-(v2)
1304 // CHECK: error: expected left paren after abs
1305 // CHECK-NEXT:{{^}}v_ceil_f32 v1, abs-(v2)
1306 // CHECK-NEXT:{{^}}                  ^
1307
1308 //==============================================================================
1309 // expected left paren after sext
1310
1311 v_cmpx_f_i32_sdwa sext[v1], v2 src0_sel:DWORD src1_sel:DWORD
1312 // CHECK: error: expected left paren after sext
1313 // CHECK-NEXT:{{^}}v_cmpx_f_i32_sdwa sext[v1], v2 src0_sel:DWORD src1_sel:DWORD
1314 // CHECK-NEXT:{{^}}                      ^
1315
1316 //==============================================================================
1317 // expected closing parentheses
1318
1319 v_ceil_f32 v1, abs(v2]
1320 // CHECK: error: expected closing parentheses
1321 // CHECK-NEXT:{{^}}v_ceil_f32 v1, abs(v2]
1322 // CHECK-NEXT:{{^}}                     ^
1323
1324 v_ceil_f32 v1, neg(v2]
1325 // CHECK: error: expected closing parentheses
1326 // CHECK-NEXT:{{^}}v_ceil_f32 v1, neg(v2]
1327 // CHECK-NEXT:{{^}}                     ^
1328
1329 v_cmpx_f_i32_sdwa sext(v1], v2 src0_sel:DWORD src1_sel:DWORD
1330 // CHECK: error: expected closing parentheses
1331 // CHECK-NEXT:{{^}}v_cmpx_f_i32_sdwa sext(v1], v2 src0_sel:DWORD src1_sel:DWORD
1332 // CHECK-NEXT:{{^}}                         ^
1333
1334 //==============================================================================
1335 // expected a left parentheses
1336
1337 ds_swizzle_b32 v8, v2 offset:swizzle[QUAD_PERM, 0, 1, 2, 3]
1338 // CHECK: error: expected a left parentheses
1339 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle[QUAD_PERM, 0, 1, 2, 3]
1340 // CHECK-NEXT:{{^}}                                    ^
1341
1342 //==============================================================================
1343 // expected an absolute expression or a label
1344
1345 s_branch 1+x
1346 // CHECK: error: expected an absolute expression or a label
1347 // CHECK-NEXT:{{^}}s_branch 1+x
1348 // CHECK-NEXT:{{^}}         ^
1349
1350 //==============================================================================
1351 // expected a 16-bit offset
1352
1353 ds_swizzle_b32 v8, v2 offset:0x10000
1354 // CHECK: error: expected a 16-bit offset
1355 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:0x10000
1356 // CHECK-NEXT:{{^}}                             ^