lib/CodeGen/PreAllocSplitting.cpp

   1 //===-- PreAllocSplitting.cpp - Pre-allocation Interval Spltting Pass. ----===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the machine instruction level pre-register allocation
  11 // live interval splitting pass. It finds live interval barriers, i.e.
  12 // instructions which will kill all physical registers in certain register
  13 // classes, and split all live intervals which cross the barrier.
  14 //
  15 //===----------------------------------------------------------------------===//
  16
  17 #define DEBUG_TYPE "pre-alloc-split"
  18 #include "VirtRegMap.h"
  19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
  20 #include "llvm/CodeGen/LiveStackAnalysis.h"
  21 #include "llvm/CodeGen/MachineDominators.h"
  22 #include "llvm/CodeGen/MachineFrameInfo.h"
  23 #include "llvm/CodeGen/MachineFunctionPass.h"
  24 #include "llvm/CodeGen/MachineLoopInfo.h"
  25 #include "llvm/CodeGen/MachineRegisterInfo.h"
  26 #include "llvm/CodeGen/Passes.h"
  27 #include "llvm/CodeGen/RegisterCoalescer.h"
  28 #include "llvm/Target/TargetInstrInfo.h"
  29 #include "llvm/Target/TargetMachine.h"
  30 #include "llvm/Target/TargetOptions.h"
  31 #include "llvm/Target/TargetRegisterInfo.h"
  32 #include "llvm/Support/CommandLine.h"
  33 #include "llvm/Support/Debug.h"
  34 #include "llvm/Support/ErrorHandling.h"
  35 #include "llvm/ADT/DenseMap.h"
  36 #include "llvm/ADT/DepthFirstIterator.h"
  37 #include "llvm/ADT/SmallPtrSet.h"
  38 #include "llvm/ADT/Statistic.h"
  39 using namespace llvm;
  40
  41 static cl::opt<int> PreSplitLimit("pre-split-limit", cl::init(-1), cl::Hidden);
  42 static cl::opt<int> DeadSplitLimit("dead-split-limit", cl::init(-1), cl::Hidden);
  43 static cl::opt<int> RestoreFoldLimit("restore-fold-limit", cl::init(-1), cl::Hidden);
  44
  45 STATISTIC(NumSplits, "Number of intervals split");
  46 STATISTIC(NumRemats, "Number of intervals split by rematerialization");
  47 STATISTIC(NumFolds, "Number of intervals split with spill folding");
  48 STATISTIC(NumRestoreFolds, "Number of intervals split with restore folding");
  49 STATISTIC(NumRenumbers, "Number of intervals renumbered into new registers");
  50 STATISTIC(NumDeadSpills, "Number of dead spills removed");
  51
  52 namespace {
  53   class VISIBILITY_HIDDEN PreAllocSplitting : public MachineFunctionPass {
  54     MachineFunction       *CurrMF;
  55     const TargetMachine   *TM;
  56     const TargetInstrInfo *TII;
  57     const TargetRegisterInfo* TRI;
  58     MachineFrameInfo      *MFI;
  59     MachineRegisterInfo   *MRI;
  60     LiveIntervals         *LIs;
  61     LiveStacks            *LSs;
  62     VirtRegMap            *VRM;
  63
  64     // Barrier - Current barrier being processed.
  65     MachineInstr          *Barrier;
  66
  67     // BarrierMBB - Basic block where the barrier resides in.
  68     MachineBasicBlock     *BarrierMBB;
  69
  70     // Barrier - Current barrier index.
  71     MachineInstrIndex     BarrierIdx;
  72
  73     // CurrLI - Current live interval being split.
  74     LiveInterval          *CurrLI;
  75
  76     // CurrSLI - Current stack slot live interval.
  77     LiveInterval          *CurrSLI;
  78
  79     // CurrSValNo - Current val# for the stack slot live interval.
  80     VNInfo                *CurrSValNo;
  81
  82     // IntervalSSMap - A map from live interval to spill slots.
  83     DenseMap<unsigned, int> IntervalSSMap;
  84
  85     // Def2SpillMap - A map from a def instruction index to spill index.
  86     DenseMap<MachineInstrIndex, MachineInstrIndex> Def2SpillMap;
  87
  88   public:
  89     static char ID;
  90     PreAllocSplitting() : MachineFunctionPass(&ID) {}
  91
  92     virtual bool runOnMachineFunction(MachineFunction &MF);
  93
  94     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
  95       AU.setPreservesCFG();
  96       AU.addRequired<LiveIntervals>();
  97       AU.addPreserved<LiveIntervals>();
  98       AU.addRequired<LiveStacks>();
  99       AU.addPreserved<LiveStacks>();
 100       AU.addPreserved<RegisterCoalescer>();
 101       if (StrongPHIElim)
 102         AU.addPreservedID(StrongPHIEliminationID);
 103       else
 104         AU.addPreservedID(PHIEliminationID);
 105       AU.addRequired<MachineDominatorTree>();
 106       AU.addRequired<MachineLoopInfo>();
 107       AU.addRequired<VirtRegMap>();
 108       AU.addPreserved<MachineDominatorTree>();
 109       AU.addPreserved<MachineLoopInfo>();
 110       AU.addPreserved<VirtRegMap>();
 111       MachineFunctionPass::getAnalysisUsage(AU);
 112     }
 113
 114     virtual void releaseMemory() {
 115       IntervalSSMap.clear();
 116       Def2SpillMap.clear();
 117     }
 118
 119     virtual const char *getPassName() const {
 120       return "Pre-Register Allocaton Live Interval Splitting";
 121     }
 122
 123     /// print - Implement the dump method.
 124     virtual void print(raw_ostream &O, const Module* M = 0) const {
 125       LIs->print(O, M);
 126     }
 127
 128
 129   private:
 130     MachineBasicBlock::iterator
 131       findNextEmptySlot(MachineBasicBlock*, MachineInstr*,
 132                         MachineInstrIndex&);
 133
 134     MachineBasicBlock::iterator
 135       findSpillPoint(MachineBasicBlock*, MachineInstr*, MachineInstr*,
 136                      SmallPtrSet<MachineInstr*, 4>&, MachineInstrIndex&);
 137
 138     MachineBasicBlock::iterator
 139       findRestorePoint(MachineBasicBlock*, MachineInstr*, MachineInstrIndex,
 140                      SmallPtrSet<MachineInstr*, 4>&, MachineInstrIndex&);
 141
 142     int CreateSpillStackSlot(unsigned, const TargetRegisterClass *);
 143
 144     bool IsAvailableInStack(MachineBasicBlock*, unsigned,
 145                             MachineInstrIndex, MachineInstrIndex,
 146                             MachineInstrIndex&, int&) const;
 147
 148     void UpdateSpillSlotInterval(VNInfo*, MachineInstrIndex, MachineInstrIndex);
 149
 150     bool SplitRegLiveInterval(LiveInterval*);
 151
 152     bool SplitRegLiveIntervals(const TargetRegisterClass **,
 153                                SmallPtrSet<LiveInterval*, 8>&);
 154
 155     bool createsNewJoin(LiveRange* LR, MachineBasicBlock* DefMBB,
 156                         MachineBasicBlock* BarrierMBB);
 157     bool Rematerialize(unsigned vreg, VNInfo* ValNo,
 158                        MachineInstr* DefMI,
 159                        MachineBasicBlock::iterator RestorePt,
 160                        MachineInstrIndex RestoreIdx,
 161                        SmallPtrSet<MachineInstr*, 4>& RefsInMBB);
 162     MachineInstr* FoldSpill(unsigned vreg, const TargetRegisterClass* RC,
 163                             MachineInstr* DefMI,
 164                             MachineInstr* Barrier,
 165                             MachineBasicBlock* MBB,
 166                             int& SS,
 167                             SmallPtrSet<MachineInstr*, 4>& RefsInMBB);
 168     MachineInstr* FoldRestore(unsigned vreg,
 169                               const TargetRegisterClass* RC,
 170                               MachineInstr* Barrier,
 171                               MachineBasicBlock* MBB,
 172                               int SS,
 173                               SmallPtrSet<MachineInstr*, 4>& RefsInMBB);
 174     void RenumberValno(VNInfo* VN);
 175     void ReconstructLiveInterval(LiveInterval* LI);
 176     bool removeDeadSpills(SmallPtrSet<LiveInterval*, 8>& split);
 177     unsigned getNumberOfNonSpills(SmallPtrSet<MachineInstr*, 4>& MIs,
 178                                unsigned Reg, int FrameIndex, bool& TwoAddr);
 179     VNInfo* PerformPHIConstruction(MachineBasicBlock::iterator Use,
 180                                    MachineBasicBlock* MBB, LiveInterval* LI,
 181                                    SmallPtrSet<MachineInstr*, 4>& Visited,
 182             DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Defs,
 183             DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Uses,
 184                                       DenseMap<MachineInstr*, VNInfo*>& NewVNs,
 185                                 DenseMap<MachineBasicBlock*, VNInfo*>& LiveOut,
 186                                 DenseMap<MachineBasicBlock*, VNInfo*>& Phis,
 187                                         bool IsTopLevel, bool IsIntraBlock);
 188     VNInfo* PerformPHIConstructionFallBack(MachineBasicBlock::iterator Use,
 189                                    MachineBasicBlock* MBB, LiveInterval* LI,
 190                                    SmallPtrSet<MachineInstr*, 4>& Visited,
 191             DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Defs,
 192             DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Uses,
 193                                       DenseMap<MachineInstr*, VNInfo*>& NewVNs,
 194                                 DenseMap<MachineBasicBlock*, VNInfo*>& LiveOut,
 195                                 DenseMap<MachineBasicBlock*, VNInfo*>& Phis,
 196                                         bool IsTopLevel, bool IsIntraBlock);
 197 };
 198 } // end anonymous namespace
 199
 200 char PreAllocSplitting::ID = 0;
 201
 202 static RegisterPass<PreAllocSplitting>
 203 X("pre-alloc-splitting", "Pre-Register Allocation Live Interval Splitting");
 204
 205 const PassInfo *const llvm::PreAllocSplittingID = &X;
 206
 207
 208 /// findNextEmptySlot - Find a gap after the given machine instruction in the
 209 /// instruction index map. If there isn't one, return end().
 210 MachineBasicBlock::iterator
 211 PreAllocSplitting::findNextEmptySlot(MachineBasicBlock *MBB, MachineInstr *MI,
 212                                      MachineInstrIndex &SpotIndex) {
 213   MachineBasicBlock::iterator MII = MI;
 214   if (++MII != MBB->end()) {
 215     MachineInstrIndex Index =
 216       LIs->findGapBeforeInstr(LIs->getInstructionIndex(MII));
 217     if (Index != MachineInstrIndex()) {
 218       SpotIndex = Index;
 219       return MII;
 220     }
 221   }
 222   return MBB->end();
 223 }
 224
 225 /// findSpillPoint - Find a gap as far away from the given MI that's suitable
 226 /// for spilling the current live interval. The index must be before any
 227 /// defs and uses of the live interval register in the mbb. Return begin() if
 228 /// none is found.
 229 MachineBasicBlock::iterator
 230 PreAllocSplitting::findSpillPoint(MachineBasicBlock *MBB, MachineInstr *MI,
 231                                   MachineInstr *DefMI,
 232                                   SmallPtrSet<MachineInstr*, 4> &RefsInMBB,
 233                                   MachineInstrIndex &SpillIndex) {
 234   MachineBasicBlock::iterator Pt = MBB->begin();
 235
 236   MachineBasicBlock::iterator MII = MI;
 237   MachineBasicBlock::iterator EndPt = DefMI
 238     ? MachineBasicBlock::iterator(DefMI) : MBB->begin();
 239
 240   while (MII != EndPt && !RefsInMBB.count(MII) &&
 241          MII->getOpcode() != TRI->getCallFrameSetupOpcode())
 242     --MII;
 243   if (MII == EndPt || RefsInMBB.count(MII)) return Pt;
 244
 245   while (MII != EndPt && !RefsInMBB.count(MII)) {
 246     MachineInstrIndex Index = LIs->getInstructionIndex(MII);
 247
 248     // We can't insert the spill between the barrier (a call), and its
 249     // corresponding call frame setup.
 250     if (MII->getOpcode() == TRI->getCallFrameDestroyOpcode()) {
 251       while (MII->getOpcode() != TRI->getCallFrameSetupOpcode()) {
 252         --MII;
 253         if (MII == EndPt) {
 254           return Pt;
 255         }
 256       }
 257       continue;
 258     } else if (LIs->hasGapBeforeInstr(Index)) {
 259       Pt = MII;
 260       SpillIndex = LIs->findGapBeforeInstr(Index, true);
 261     }
 262
 263     if (RefsInMBB.count(MII))
 264       return Pt;
 265
 266
 267     --MII;
 268   }
 269
 270   return Pt;
 271 }
 272
 273 /// findRestorePoint - Find a gap in the instruction index map that's suitable
 274 /// for restoring the current live interval value. The index must be before any
 275 /// uses of the live interval register in the mbb. Return end() if none is
 276 /// found.
 277 MachineBasicBlock::iterator
 278 PreAllocSplitting::findRestorePoint(MachineBasicBlock *MBB, MachineInstr *MI,
 279                                     MachineInstrIndex LastIdx,
 280                                     SmallPtrSet<MachineInstr*, 4> &RefsInMBB,
 281                                     MachineInstrIndex &RestoreIndex) {
 282   // FIXME: Allow spill to be inserted to the beginning of the mbb. Update mbb
 283   // begin index accordingly.
 284   MachineBasicBlock::iterator Pt = MBB->end();
 285   MachineBasicBlock::iterator EndPt = MBB->getFirstTerminator();
 286
 287   // We start at the call, so walk forward until we find the call frame teardown
 288   // since we can't insert restores before that.  Bail if we encounter a use
 289   // during this time.
 290   MachineBasicBlock::iterator MII = MI;
 291   if (MII == EndPt) return Pt;
 292
 293   while (MII != EndPt && !RefsInMBB.count(MII) &&
 294          MII->getOpcode() != TRI->getCallFrameDestroyOpcode())
 295     ++MII;
 296   if (MII == EndPt || RefsInMBB.count(MII)) return Pt;
 297   ++MII;
 298
 299   // FIXME: Limit the number of instructions to examine to reduce
 300   // compile time?
 301   while (MII != EndPt) {
 302     MachineInstrIndex Index = LIs->getInstructionIndex(MII);
 303     if (Index > LastIdx)
 304       break;
 305     MachineInstrIndex Gap = LIs->findGapBeforeInstr(Index);
 306
 307     // We can't insert a restore between the barrier (a call) and its
 308     // corresponding call frame teardown.
 309     if (MII->getOpcode() == TRI->getCallFrameSetupOpcode()) {
 310       do {
 311         if (MII == EndPt || RefsInMBB.count(MII)) return Pt;
 312         ++MII;
 313       } while (MII->getOpcode() != TRI->getCallFrameDestroyOpcode());
 314     } else if (Gap != MachineInstrIndex()) {
 315       Pt = MII;
 316       RestoreIndex = Gap;
 317     }
 318
 319     if (RefsInMBB.count(MII))
 320       return Pt;
 321
 322     ++MII;
 323   }
 324
 325   return Pt;
 326 }
 327
 328 /// CreateSpillStackSlot - Create a stack slot for the live interval being
 329 /// split. If the live interval was previously split, just reuse the same
 330 /// slot.
 331 int PreAllocSplitting::CreateSpillStackSlot(unsigned Reg,
 332                                             const TargetRegisterClass *RC) {
 333   int SS;
 334   DenseMap<unsigned, int>::iterator I = IntervalSSMap.find(Reg);
 335   if (I != IntervalSSMap.end()) {
 336     SS = I->second;
 337   } else {
 338     SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
 339     IntervalSSMap[Reg] = SS;
 340   }
 341
 342   // Create live interval for stack slot.
 343   CurrSLI = &LSs->getOrCreateInterval(SS, RC);
 344   if (CurrSLI->hasAtLeastOneValue())
 345     CurrSValNo = CurrSLI->getValNumInfo(0);
 346   else
 347     CurrSValNo = CurrSLI->getNextValue(MachineInstrIndex(), 0, false,
 348                                        LSs->getVNInfoAllocator());
 349   return SS;
 350 }
 351
 352 /// IsAvailableInStack - Return true if register is available in a split stack
 353 /// slot at the specified index.
 354 bool
 355 PreAllocSplitting::IsAvailableInStack(MachineBasicBlock *DefMBB,
 356                                     unsigned Reg, MachineInstrIndex DefIndex,
 357                                     MachineInstrIndex RestoreIndex,
 358                                     MachineInstrIndex &SpillIndex,
 359                                     int& SS) const {
 360   if (!DefMBB)
 361     return false;
 362
 363   DenseMap<unsigned, int>::iterator I = IntervalSSMap.find(Reg);
 364   if (I == IntervalSSMap.end())
 365     return false;
 366   DenseMap<MachineInstrIndex, MachineInstrIndex>::iterator
 367     II = Def2SpillMap.find(DefIndex);
 368   if (II == Def2SpillMap.end())
 369     return false;
 370
 371   // If last spill of def is in the same mbb as barrier mbb (where restore will
 372   // be), make sure it's not below the intended restore index.
 373   // FIXME: Undo the previous spill?
 374   assert(LIs->getMBBFromIndex(II->second) == DefMBB);
 375   if (DefMBB == BarrierMBB && II->second >= RestoreIndex)
 376     return false;
 377
 378   SS = I->second;
 379   SpillIndex = II->second;
 380   return true;
 381 }
 382
 383 /// UpdateSpillSlotInterval - Given the specified val# of the register live
 384 /// interval being split, and the spill and restore indicies, update the live
 385 /// interval of the spill stack slot.
 386 void
 387 PreAllocSplitting::UpdateSpillSlotInterval(VNInfo *ValNo, MachineInstrIndex SpillIndex,
 388                                            MachineInstrIndex RestoreIndex) {
 389   assert(LIs->getMBBFromIndex(RestoreIndex) == BarrierMBB &&
 390          "Expect restore in the barrier mbb");
 391
 392   MachineBasicBlock *MBB = LIs->getMBBFromIndex(SpillIndex);
 393   if (MBB == BarrierMBB) {
 394     // Intra-block spill + restore. We are done.
 395     LiveRange SLR(SpillIndex, RestoreIndex, CurrSValNo);
 396     CurrSLI->addRange(SLR);
 397     return;
 398   }
 399
 400   SmallPtrSet<MachineBasicBlock*, 4> Processed;
 401   MachineInstrIndex EndIdx = LIs->getMBBEndIdx(MBB);
 402   LiveRange SLR(SpillIndex, LIs->getNextSlot(EndIdx), CurrSValNo);
 403   CurrSLI->addRange(SLR);
 404   Processed.insert(MBB);
 405
 406   // Start from the spill mbb, figure out the extend of the spill slot's
 407   // live interval.
 408   SmallVector<MachineBasicBlock*, 4> WorkList;
 409   const LiveRange *LR = CurrLI->getLiveRangeContaining(SpillIndex);
 410   if (LR->end > EndIdx)
 411     // If live range extend beyond end of mbb, add successors to work list.
 412     for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
 413            SE = MBB->succ_end(); SI != SE; ++SI)
 414       WorkList.push_back(*SI);
 415
 416   while (!WorkList.empty()) {
 417     MachineBasicBlock *MBB = WorkList.back();
 418     WorkList.pop_back();
 419     if (Processed.count(MBB))
 420       continue;
 421     MachineInstrIndex Idx = LIs->getMBBStartIdx(MBB);
 422     LR = CurrLI->getLiveRangeContaining(Idx);
 423     if (LR && LR->valno == ValNo) {
 424       EndIdx = LIs->getMBBEndIdx(MBB);
 425       if (Idx <= RestoreIndex && RestoreIndex < EndIdx) {
 426         // Spill slot live interval stops at the restore.
 427         LiveRange SLR(Idx, RestoreIndex, CurrSValNo);
 428         CurrSLI->addRange(SLR);
 429       } else if (LR->end > EndIdx) {
 430         // Live range extends beyond end of mbb, process successors.
 431         LiveRange SLR(Idx, LIs->getNextIndex(EndIdx), CurrSValNo);
 432         CurrSLI->addRange(SLR);
 433         for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
 434                SE = MBB->succ_end(); SI != SE; ++SI)
 435           WorkList.push_back(*SI);
 436       } else {
 437         LiveRange SLR(Idx, LR->end, CurrSValNo);
 438         CurrSLI->addRange(SLR);
 439       }
 440       Processed.insert(MBB);
 441     }
 442   }
 443 }
 444
 445 /// PerformPHIConstruction - From properly set up use and def lists, use a PHI
 446 /// construction algorithm to compute the ranges and valnos for an interval.
 447 VNInfo*
 448 PreAllocSplitting::PerformPHIConstruction(MachineBasicBlock::iterator UseI,
 449                                        MachineBasicBlock* MBB, LiveInterval* LI,
 450                                        SmallPtrSet<MachineInstr*, 4>& Visited,
 451              DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Defs,
 452              DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Uses,
 453                                        DenseMap<MachineInstr*, VNInfo*>& NewVNs,
 454                                  DenseMap<MachineBasicBlock*, VNInfo*>& LiveOut,
 455                                  DenseMap<MachineBasicBlock*, VNInfo*>& Phis,
 456                                            bool IsTopLevel, bool IsIntraBlock) {
 457   // Return memoized result if it's available.
 458   if (IsTopLevel && Visited.count(UseI) && NewVNs.count(UseI))
 459     return NewVNs[UseI];
 460   else if (!IsTopLevel && IsIntraBlock && NewVNs.count(UseI))
 461     return NewVNs[UseI];
 462   else if (!IsIntraBlock && LiveOut.count(MBB))
 463     return LiveOut[MBB];
 464
 465   // Check if our block contains any uses or defs.
 466   bool ContainsDefs = Defs.count(MBB);
 467   bool ContainsUses = Uses.count(MBB);
 468
 469   VNInfo* RetVNI = 0;
 470
 471   // Enumerate the cases of use/def contaning blocks.
 472   if (!ContainsDefs && !ContainsUses) {
 473     return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs, Uses,
 474                                           NewVNs, LiveOut, Phis,
 475                                           IsTopLevel, IsIntraBlock);
 476   } else if (ContainsDefs && !ContainsUses) {
 477     SmallPtrSet<MachineInstr*, 2>& BlockDefs = Defs[MBB];
 478
 479     // Search for the def in this block.  If we don't find it before the
 480     // instruction we care about, go to the fallback case.  Note that that
 481     // should never happen: this cannot be intrablock, so use should
 482     // always be an end() iterator.
 483     assert(UseI == MBB->end() && "No use marked in intrablock");
 484
 485     MachineBasicBlock::iterator Walker = UseI;
 486     --Walker;
 487     while (Walker != MBB->begin()) {
 488       if (BlockDefs.count(Walker))
 489         break;
 490       --Walker;
 491     }
 492
 493     // Once we've found it, extend its VNInfo to our instruction.
 494     MachineInstrIndex DefIndex = LIs->getInstructionIndex(Walker);
 495     DefIndex = LIs->getDefIndex(DefIndex);
 496     MachineInstrIndex EndIndex = LIs->getMBBEndIdx(MBB);
 497
 498     RetVNI = NewVNs[Walker];
 499     LI->addRange(LiveRange(DefIndex, LIs->getNextSlot(EndIndex), RetVNI));
 500   } else if (!ContainsDefs && ContainsUses) {
 501     SmallPtrSet<MachineInstr*, 2>& BlockUses = Uses[MBB];
 502
 503     // Search for the use in this block that precedes the instruction we care
 504     // about, going to the fallback case if we don't find it.
 505     if (UseI == MBB->begin())
 506       return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs,
 507                                             Uses, NewVNs, LiveOut, Phis,
 508                                             IsTopLevel, IsIntraBlock);
 509
 510     MachineBasicBlock::iterator Walker = UseI;
 511     --Walker;
 512     bool found = false;
 513     while (Walker != MBB->begin()) {
 514       if (BlockUses.count(Walker)) {
 515         found = true;
 516         break;
 517       }
 518       --Walker;
 519     }
 520
 521     // Must check begin() too.
 522     if (!found) {
 523       if (BlockUses.count(Walker))
 524         found = true;
 525       else
 526         return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs,
 527                                               Uses, NewVNs, LiveOut, Phis,
 528                                               IsTopLevel, IsIntraBlock);
 529     }
 530
 531     MachineInstrIndex UseIndex = LIs->getInstructionIndex(Walker);
 532     UseIndex = LIs->getUseIndex(UseIndex);
 533     MachineInstrIndex EndIndex;
 534     if (IsIntraBlock) {
 535       EndIndex = LIs->getInstructionIndex(UseI);
 536       EndIndex = LIs->getUseIndex(EndIndex);
 537     } else
 538       EndIndex = LIs->getMBBEndIdx(MBB);
 539
 540     // Now, recursively phi construct the VNInfo for the use we found,
 541     // and then extend it to include the instruction we care about
 542     RetVNI = PerformPHIConstruction(Walker, MBB, LI, Visited, Defs, Uses,
 543                                     NewVNs, LiveOut, Phis, false, true);
 544
 545     LI->addRange(LiveRange(UseIndex, LIs->getNextSlot(EndIndex), RetVNI));
 546
 547     // FIXME: Need to set kills properly for inter-block stuff.
 548     if (RetVNI->isKill(UseIndex)) RetVNI->removeKill(UseIndex);
 549     if (IsIntraBlock)
 550       RetVNI->addKill(EndIndex);
 551   } else if (ContainsDefs && ContainsUses) {
 552     SmallPtrSet<MachineInstr*, 2>& BlockDefs = Defs[MBB];
 553     SmallPtrSet<MachineInstr*, 2>& BlockUses = Uses[MBB];
 554
 555     // This case is basically a merging of the two preceding case, with the
 556     // special note that checking for defs must take precedence over checking
 557     // for uses, because of two-address instructions.
 558
 559     if (UseI == MBB->begin())
 560       return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs, Uses,
 561                                             NewVNs, LiveOut, Phis,
 562                                             IsTopLevel, IsIntraBlock);
 563
 564     MachineBasicBlock::iterator Walker = UseI;
 565     --Walker;
 566     bool foundDef = false;
 567     bool foundUse = false;
 568     while (Walker != MBB->begin()) {
 569       if (BlockDefs.count(Walker)) {
 570         foundDef = true;
 571         break;
 572       } else if (BlockUses.count(Walker)) {
 573         foundUse = true;
 574         break;
 575       }
 576       --Walker;
 577     }
 578
 579     // Must check begin() too.
 580     if (!foundDef && !foundUse) {
 581       if (BlockDefs.count(Walker))
 582         foundDef = true;
 583       else if (BlockUses.count(Walker))
 584         foundUse = true;
 585       else
 586         return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs,
 587                                               Uses, NewVNs, LiveOut, Phis,
 588                                               IsTopLevel, IsIntraBlock);
 589     }
 590
 591     MachineInstrIndex StartIndex = LIs->getInstructionIndex(Walker);
 592     StartIndex = foundDef ? LIs->getDefIndex(StartIndex) :
 593                             LIs->getUseIndex(StartIndex);
 594     MachineInstrIndex EndIndex;
 595     if (IsIntraBlock) {
 596       EndIndex = LIs->getInstructionIndex(UseI);
 597       EndIndex = LIs->getUseIndex(EndIndex);
 598     } else
 599       EndIndex = LIs->getMBBEndIdx(MBB);
 600
 601     if (foundDef)
 602       RetVNI = NewVNs[Walker];
 603     else
 604       RetVNI = PerformPHIConstruction(Walker, MBB, LI, Visited, Defs, Uses,
 605                                       NewVNs, LiveOut, Phis, false, true);
 606
 607     LI->addRange(LiveRange(StartIndex, LIs->getNextSlot(EndIndex), RetVNI));
 608
 609     if (foundUse && RetVNI->isKill(StartIndex))
 610       RetVNI->removeKill(StartIndex);
 611     if (IsIntraBlock) {
 612       RetVNI->addKill(EndIndex);
 613     }
 614   }
 615
 616   // Memoize results so we don't have to recompute them.
 617   if (!IsIntraBlock) LiveOut[MBB] = RetVNI;
 618   else {
 619     if (!NewVNs.count(UseI))
 620       NewVNs[UseI] = RetVNI;
 621     Visited.insert(UseI);
 622   }
 623
 624   return RetVNI;
 625 }
 626
 627 /// PerformPHIConstructionFallBack - PerformPHIConstruction fall back path.
 628 ///
 629 VNInfo*
 630 PreAllocSplitting::PerformPHIConstructionFallBack(MachineBasicBlock::iterator UseI,
 631                                        MachineBasicBlock* MBB, LiveInterval* LI,
 632                                        SmallPtrSet<MachineInstr*, 4>& Visited,
 633              DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Defs,
 634              DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Uses,
 635                                        DenseMap<MachineInstr*, VNInfo*>& NewVNs,
 636                                  DenseMap<MachineBasicBlock*, VNInfo*>& LiveOut,
 637                                  DenseMap<MachineBasicBlock*, VNInfo*>& Phis,
 638                                            bool IsTopLevel, bool IsIntraBlock) {
 639   // NOTE: Because this is the fallback case from other cases, we do NOT
 640   // assume that we are not intrablock here.
 641   if (Phis.count(MBB)) return Phis[MBB];
 642
 643   MachineInstrIndex StartIndex = LIs->getMBBStartIdx(MBB);
 644   VNInfo *RetVNI = Phis[MBB] =
 645     LI->getNextValue(MachineInstrIndex(), /*FIXME*/ 0, false,
 646                      LIs->getVNInfoAllocator());
 647
 648   if (!IsIntraBlock) LiveOut[MBB] = RetVNI;
 649
 650   // If there are no uses or defs between our starting point and the
 651   // beginning of the block, then recursive perform phi construction
 652   // on our predecessors.
 653   DenseMap<MachineBasicBlock*, VNInfo*> IncomingVNs;
 654   for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
 655          PE = MBB->pred_end(); PI != PE; ++PI) {
 656     VNInfo* Incoming = PerformPHIConstruction((*PI)->end(), *PI, LI,
 657                                               Visited, Defs, Uses, NewVNs,
 658                                               LiveOut, Phis, false, false);
 659     if (Incoming != 0)
 660       IncomingVNs[*PI] = Incoming;
 661   }
 662
 663   if (MBB->pred_size() == 1 && !RetVNI->hasPHIKill()) {
 664     VNInfo* OldVN = RetVNI;
 665     VNInfo* NewVN = IncomingVNs.begin()->second;
 666     VNInfo* MergedVN = LI->MergeValueNumberInto(OldVN, NewVN);
 667     if (MergedVN == OldVN) std::swap(OldVN, NewVN);
 668
 669     for (DenseMap<MachineBasicBlock*, VNInfo*>::iterator LOI = LiveOut.begin(),
 670          LOE = LiveOut.end(); LOI != LOE; ++LOI)
 671       if (LOI->second == OldVN)
 672         LOI->second = MergedVN;
 673     for (DenseMap<MachineInstr*, VNInfo*>::iterator NVI = NewVNs.begin(),
 674          NVE = NewVNs.end(); NVI != NVE; ++NVI)
 675       if (NVI->second == OldVN)
 676         NVI->second = MergedVN;
 677     for (DenseMap<MachineBasicBlock*, VNInfo*>::iterator PI = Phis.begin(),
 678          PE = Phis.end(); PI != PE; ++PI)
 679       if (PI->second == OldVN)
 680         PI->second = MergedVN;
 681     RetVNI = MergedVN;
 682   } else {
 683     // Otherwise, merge the incoming VNInfos with a phi join.  Create a new
 684     // VNInfo to represent the joined value.
 685     for (DenseMap<MachineBasicBlock*, VNInfo*>::iterator I =
 686            IncomingVNs.begin(), E = IncomingVNs.end(); I != E; ++I) {
 687       I->second->setHasPHIKill(true);
 688       MachineInstrIndex KillIndex = LIs->getMBBEndIdx(I->first);
 689       if (!I->second->isKill(KillIndex))
 690         I->second->addKill(KillIndex);
 691     }
 692   }
 693
 694   MachineInstrIndex EndIndex;
 695   if (IsIntraBlock) {
 696     EndIndex = LIs->getInstructionIndex(UseI);
 697     EndIndex = LIs->getUseIndex(EndIndex);
 698   } else
 699     EndIndex = LIs->getMBBEndIdx(MBB);
 700   LI->addRange(LiveRange(StartIndex, LIs->getNextSlot(EndIndex), RetVNI));
 701   if (IsIntraBlock)
 702     RetVNI->addKill(EndIndex);
 703
 704   // Memoize results so we don't have to recompute them.
 705   if (!IsIntraBlock)
 706     LiveOut[MBB] = RetVNI;
 707   else {
 708     if (!NewVNs.count(UseI))
 709       NewVNs[UseI] = RetVNI;
 710     Visited.insert(UseI);
 711   }
 712
 713   return RetVNI;
 714 }
 715
 716 /// ReconstructLiveInterval - Recompute a live interval from scratch.
 717 void PreAllocSplitting::ReconstructLiveInterval(LiveInterval* LI) {
 718   BumpPtrAllocator& Alloc = LIs->getVNInfoAllocator();
 719
 720   // Clear the old ranges and valnos;
 721   LI->clear();
 722
 723   // Cache the uses and defs of the register
 724   typedef DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> > RegMap;
 725   RegMap Defs, Uses;
 726
 727   // Keep track of the new VNs we're creating.
 728   DenseMap<MachineInstr*, VNInfo*> NewVNs;
 729   SmallPtrSet<VNInfo*, 2> PhiVNs;
 730
 731   // Cache defs, and create a new VNInfo for each def.
 732   for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(LI->reg),
 733        DE = MRI->def_end(); DI != DE; ++DI) {
 734     Defs[(*DI).getParent()].insert(&*DI);
 735
 736     MachineInstrIndex DefIdx = LIs->getInstructionIndex(&*DI);
 737     DefIdx = LIs->getDefIndex(DefIdx);
 738
 739     assert(DI->getOpcode() != TargetInstrInfo::PHI &&
 740            "Following NewVN isPHIDef flag incorrect. Fix me!");
 741     VNInfo* NewVN = LI->getNextValue(DefIdx, 0, true, Alloc);
 742
 743     // If the def is a move, set the copy field.
 744     unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
 745     if (TII->isMoveInstr(*DI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
 746       if (DstReg == LI->reg)
 747         NewVN->setCopy(&*DI);
 748
 749     NewVNs[&*DI] = NewVN;
 750   }
 751
 752   // Cache uses as a separate pass from actually processing them.
 753   for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(LI->reg),
 754        UE = MRI->use_end(); UI != UE; ++UI)
 755     Uses[(*UI).getParent()].insert(&*UI);
 756
 757   // Now, actually process every use and use a phi construction algorithm
 758   // to walk from it to its reaching definitions, building VNInfos along
 759   // the way.
 760   DenseMap<MachineBasicBlock*, VNInfo*> LiveOut;
 761   DenseMap<MachineBasicBlock*, VNInfo*> Phis;
 762   SmallPtrSet<MachineInstr*, 4> Visited;
 763   for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(LI->reg),
 764        UE = MRI->use_end(); UI != UE; ++UI) {
 765     PerformPHIConstruction(&*UI, UI->getParent(), LI, Visited, Defs,
 766                            Uses, NewVNs, LiveOut, Phis, true, true);
 767   }
 768
 769   // Add ranges for dead defs
 770   for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(LI->reg),
 771        DE = MRI->def_end(); DI != DE; ++DI) {
 772     MachineInstrIndex DefIdx = LIs->getInstructionIndex(&*DI);
 773     DefIdx = LIs->getDefIndex(DefIdx);
 774
 775     if (LI->liveAt(DefIdx)) continue;
 776
 777     VNInfo* DeadVN = NewVNs[&*DI];
 778     LI->addRange(LiveRange(DefIdx, LIs->getNextSlot(DefIdx), DeadVN));
 779     DeadVN->addKill(DefIdx);
 780   }
 781 }
 782
 783 /// RenumberValno - Split the given valno out into a new vreg, allowing it to
 784 /// be allocated to a different register.  This function creates a new vreg,
 785 /// copies the valno and its live ranges over to the new vreg's interval,
 786 /// removes them from the old interval, and rewrites all uses and defs of
 787 /// the original reg to the new vreg within those ranges.
 788 void PreAllocSplitting::RenumberValno(VNInfo* VN) {
 789   SmallVector<VNInfo*, 4> Stack;
 790   SmallVector<VNInfo*, 4> VNsToCopy;
 791   Stack.push_back(VN);
 792
 793   // Walk through and copy the valno we care about, and any other valnos
 794   // that are two-address redefinitions of the one we care about.  These
 795   // will need to be rewritten as well.  We also check for safety of the
 796   // renumbering here, by making sure that none of the valno involved has
 797   // phi kills.
 798   while (!Stack.empty()) {
 799     VNInfo* OldVN = Stack.back();
 800     Stack.pop_back();
 801
 802     // Bail out if we ever encounter a valno that has a PHI kill.  We can't
 803     // renumber these.
 804     if (OldVN->hasPHIKill()) return;
 805
 806     VNsToCopy.push_back(OldVN);
 807
 808     // Locate two-address redefinitions
 809     for (VNInfo::KillSet::iterator KI = OldVN->kills.begin(),
 810          KE = OldVN->kills.end(); KI != KE; ++KI) {
 811       assert(!KI->isPHIIndex() &&
 812              "VN previously reported having no PHI kills.");
 813       MachineInstr* MI = LIs->getInstructionFromIndex(*KI);
 814       unsigned DefIdx = MI->findRegisterDefOperandIdx(CurrLI->reg);
 815       if (DefIdx == ~0U) continue;
 816       if (MI->isRegTiedToUseOperand(DefIdx)) {
 817         VNInfo* NextVN =
 818           CurrLI->findDefinedVNInfoForRegInt(LIs->getDefIndex(*KI));
 819         if (NextVN == OldVN) continue;
 820         Stack.push_back(NextVN);
 821       }
 822     }
 823   }
 824
 825   // Create the new vreg
 826   unsigned NewVReg = MRI->createVirtualRegister(MRI->getRegClass(CurrLI->reg));
 827
 828   // Create the new live interval
 829   LiveInterval& NewLI = LIs->getOrCreateInterval(NewVReg);
 830
 831   for (SmallVector<VNInfo*, 4>::iterator OI = VNsToCopy.begin(), OE =
 832        VNsToCopy.end(); OI != OE; ++OI) {
 833     VNInfo* OldVN = *OI;
 834
 835     // Copy the valno over
 836     VNInfo* NewVN = NewLI.createValueCopy(OldVN, LIs->getVNInfoAllocator());
 837     NewLI.MergeValueInAsValue(*CurrLI, OldVN, NewVN);
 838
 839     // Remove the valno from the old interval
 840     CurrLI->removeValNo(OldVN);
 841   }
 842
 843   // Rewrite defs and uses.  This is done in two stages to avoid invalidating
 844   // the reg_iterator.
 845   SmallVector<std::pair<MachineInstr*, unsigned>, 8> OpsToChange;
 846
 847   for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(CurrLI->reg),
 848          E = MRI->reg_end(); I != E; ++I) {
 849     MachineOperand& MO = I.getOperand();
 850     MachineInstrIndex InstrIdx = LIs->getInstructionIndex(&*I);
 851
 852     if ((MO.isUse() && NewLI.liveAt(LIs->getUseIndex(InstrIdx))) ||
 853         (MO.isDef() && NewLI.liveAt(LIs->getDefIndex(InstrIdx))))
 854       OpsToChange.push_back(std::make_pair(&*I, I.getOperandNo()));
 855   }
 856
 857   for (SmallVector<std::pair<MachineInstr*, unsigned>, 8>::iterator I =
 858        OpsToChange.begin(), E = OpsToChange.end(); I != E; ++I) {
 859     MachineInstr* Inst = I->first;
 860     unsigned OpIdx = I->second;
 861     MachineOperand& MO = Inst->getOperand(OpIdx);
 862     MO.setReg(NewVReg);
 863   }
 864
 865   // Grow the VirtRegMap, since we've created a new vreg.
 866   VRM->grow();
 867
 868   // The renumbered vreg shares a stack slot with the old register.
 869   if (IntervalSSMap.count(CurrLI->reg))
 870     IntervalSSMap[NewVReg] = IntervalSSMap[CurrLI->reg];
 871
 872   NumRenumbers++;
 873 }
 874
 875 bool PreAllocSplitting::Rematerialize(unsigned VReg, VNInfo* ValNo,
 876                                       MachineInstr* DefMI,
 877                                       MachineBasicBlock::iterator RestorePt,
 878                                       MachineInstrIndex RestoreIdx,
 879                                     SmallPtrSet<MachineInstr*, 4>& RefsInMBB) {
 880   MachineBasicBlock& MBB = *RestorePt->getParent();
 881
 882   MachineBasicBlock::iterator KillPt = BarrierMBB->end();
 883   MachineInstrIndex KillIdx;
 884   if (!ValNo->isDefAccurate() || DefMI->getParent() == BarrierMBB)
 885     KillPt = findSpillPoint(BarrierMBB, Barrier, NULL, RefsInMBB, KillIdx);
 886   else
 887     KillPt = findNextEmptySlot(DefMI->getParent(), DefMI, KillIdx);
 888
 889   if (KillPt == DefMI->getParent()->end())
 890     return false;
 891
 892   TII->reMaterialize(MBB, RestorePt, VReg, 0, DefMI);
 893   LIs->InsertMachineInstrInMaps(prior(RestorePt), RestoreIdx);
 894
 895   ReconstructLiveInterval(CurrLI);
 896   MachineInstrIndex RematIdx = LIs->getInstructionIndex(prior(RestorePt));
 897   RematIdx = LIs->getDefIndex(RematIdx);
 898   RenumberValno(CurrLI->findDefinedVNInfoForRegInt(RematIdx));
 899
 900   ++NumSplits;
 901   ++NumRemats;
 902   return true;
 903 }
 904
 905 MachineInstr* PreAllocSplitting::FoldSpill(unsigned vreg,
 906                                            const TargetRegisterClass* RC,
 907                                            MachineInstr* DefMI,
 908                                            MachineInstr* Barrier,
 909                                            MachineBasicBlock* MBB,
 910                                            int& SS,
 911                                     SmallPtrSet<MachineInstr*, 4>& RefsInMBB) {
 912   MachineBasicBlock::iterator Pt = MBB->begin();
 913
 914   // Go top down if RefsInMBB is empty.
 915   if (RefsInMBB.empty())
 916     return 0;
 917
 918   MachineBasicBlock::iterator FoldPt = Barrier;
 919   while (&*FoldPt != DefMI && FoldPt != MBB->begin() &&
 920          !RefsInMBB.count(FoldPt))
 921     --FoldPt;
 922
 923   int OpIdx = FoldPt->findRegisterDefOperandIdx(vreg, false);
 924   if (OpIdx == -1)
 925     return 0;
 926
 927   SmallVector<unsigned, 1> Ops;
 928   Ops.push_back(OpIdx);
 929
 930   if (!TII->canFoldMemoryOperand(FoldPt, Ops))
 931     return 0;
 932
 933   DenseMap<unsigned, int>::iterator I = IntervalSSMap.find(vreg);
 934   if (I != IntervalSSMap.end()) {
 935     SS = I->second;
 936   } else {
 937     SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
 938   }
 939
 940   MachineInstr* FMI = TII->foldMemoryOperand(*MBB->getParent(),
 941                                              FoldPt, Ops, SS);
 942
 943   if (FMI) {
 944     LIs->ReplaceMachineInstrInMaps(FoldPt, FMI);
 945     FMI = MBB->insert(MBB->erase(FoldPt), FMI);
 946     ++NumFolds;
 947
 948     IntervalSSMap[vreg] = SS;
 949     CurrSLI = &LSs->getOrCreateInterval(SS, RC);
 950     if (CurrSLI->hasAtLeastOneValue())
 951       CurrSValNo = CurrSLI->getValNumInfo(0);
 952     else
 953       CurrSValNo = CurrSLI->getNextValue(MachineInstrIndex(), 0, false,
 954                                          LSs->getVNInfoAllocator());
 955   }
 956
 957   return FMI;
 958 }
 959
 960 MachineInstr* PreAllocSplitting::FoldRestore(unsigned vreg,
 961                                              const TargetRegisterClass* RC,
 962                                              MachineInstr* Barrier,
 963                                              MachineBasicBlock* MBB,
 964                                              int SS,
 965                                      SmallPtrSet<MachineInstr*, 4>& RefsInMBB) {
 966   if ((int)RestoreFoldLimit != -1 && RestoreFoldLimit == (int)NumRestoreFolds)
 967     return 0;
 968
 969   // Go top down if RefsInMBB is empty.
 970   if (RefsInMBB.empty())
 971     return 0;
 972
 973   // Can't fold a restore between a call stack setup and teardown.
 974   MachineBasicBlock::iterator FoldPt = Barrier;
 975
 976   // Advance from barrier to call frame teardown.
 977   while (FoldPt != MBB->getFirstTerminator() &&
 978          FoldPt->getOpcode() != TRI->getCallFrameDestroyOpcode()) {
 979     if (RefsInMBB.count(FoldPt))
 980       return 0;
 981
 982     ++FoldPt;
 983   }
 984
 985   if (FoldPt == MBB->getFirstTerminator())
 986     return 0;
 987   else
 988     ++FoldPt;
 989
 990   // Now find the restore point.
 991   while (FoldPt != MBB->getFirstTerminator() && !RefsInMBB.count(FoldPt)) {
 992     if (FoldPt->getOpcode() == TRI->getCallFrameSetupOpcode()) {
 993       while (FoldPt != MBB->getFirstTerminator() &&
 994              FoldPt->getOpcode() != TRI->getCallFrameDestroyOpcode()) {
 995         if (RefsInMBB.count(FoldPt))
 996           return 0;
 997
 998         ++FoldPt;
 999       }
1000
1001       if (FoldPt == MBB->getFirstTerminator())
1002         return 0;
1003     }
1004
1005     ++FoldPt;
1006   }
1007
1008   if (FoldPt == MBB->getFirstTerminator())
1009     return 0;
1010
1011   int OpIdx = FoldPt->findRegisterUseOperandIdx(vreg, true);
1012   if (OpIdx == -1)
1013     return 0;
1014
1015   SmallVector<unsigned, 1> Ops;
1016   Ops.push_back(OpIdx);
1017
1018   if (!TII->canFoldMemoryOperand(FoldPt, Ops))
1019     return 0;
1020
1021   MachineInstr* FMI = TII->foldMemoryOperand(*MBB->getParent(),
1022                                              FoldPt, Ops, SS);
1023
1024   if (FMI) {
1025     LIs->ReplaceMachineInstrInMaps(FoldPt, FMI);
1026     FMI = MBB->insert(MBB->erase(FoldPt), FMI);
1027     ++NumRestoreFolds;
1028   }
1029
1030   return FMI;
1031 }
1032
1033 /// SplitRegLiveInterval - Split (spill and restore) the given live interval
1034 /// so it would not cross the barrier that's being processed. Shrink wrap
1035 /// (minimize) the live interval to the last uses.
1036 bool PreAllocSplitting::SplitRegLiveInterval(LiveInterval *LI) {
1037   CurrLI = LI;
1038
1039   // Find live range where current interval cross the barrier.
1040   LiveInterval::iterator LR =
1041     CurrLI->FindLiveRangeContaining(LIs->getUseIndex(BarrierIdx));
1042   VNInfo *ValNo = LR->valno;
1043
1044   assert(!ValNo->isUnused() && "Val# is defined by a dead def?");
1045
1046   MachineInstr *DefMI = ValNo->isDefAccurate()
1047     ? LIs->getInstructionFromIndex(ValNo->def) : NULL;
1048
1049   // If this would create a new join point, do not split.
1050   if (DefMI && createsNewJoin(LR, DefMI->getParent(), Barrier->getParent()))
1051     return false;
1052
1053   // Find all references in the barrier mbb.
1054   SmallPtrSet<MachineInstr*, 4> RefsInMBB;
1055   for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(CurrLI->reg),
1056          E = MRI->reg_end(); I != E; ++I) {
1057     MachineInstr *RefMI = &*I;
1058     if (RefMI->getParent() == BarrierMBB)
1059       RefsInMBB.insert(RefMI);
1060   }
1061
1062   // Find a point to restore the value after the barrier.
1063   MachineInstrIndex RestoreIndex;
1064   MachineBasicBlock::iterator RestorePt =
1065     findRestorePoint(BarrierMBB, Barrier, LR->end, RefsInMBB, RestoreIndex);
1066   if (RestorePt == BarrierMBB->end())
1067     return false;
1068
1069   if (DefMI && LIs->isReMaterializable(*LI, ValNo, DefMI))
1070     if (Rematerialize(LI->reg, ValNo, DefMI, RestorePt,
1071                       RestoreIndex, RefsInMBB))
1072     return true;
1073
1074   // Add a spill either before the barrier or after the definition.
1075   MachineBasicBlock *DefMBB = DefMI ? DefMI->getParent() : NULL;
1076   const TargetRegisterClass *RC = MRI->getRegClass(CurrLI->reg);
1077   MachineInstrIndex SpillIndex;
1078   MachineInstr *SpillMI = NULL;
1079   int SS = -1;
1080   if (!ValNo->isDefAccurate()) {
1081     // If we don't know where the def is we must split just before the barrier.
1082     if ((SpillMI = FoldSpill(LI->reg, RC, 0, Barrier,
1083                             BarrierMBB, SS, RefsInMBB))) {
1084       SpillIndex = LIs->getInstructionIndex(SpillMI);
1085     } else {
1086       MachineBasicBlock::iterator SpillPt =
1087         findSpillPoint(BarrierMBB, Barrier, NULL, RefsInMBB, SpillIndex);
1088       if (SpillPt == BarrierMBB->begin())
1089         return false; // No gap to insert spill.
1090       // Add spill.
1091
1092       SS = CreateSpillStackSlot(CurrLI->reg, RC);
1093       TII->storeRegToStackSlot(*BarrierMBB, SpillPt, CurrLI->reg, true, SS, RC);
1094       SpillMI = prior(SpillPt);
1095       LIs->InsertMachineInstrInMaps(SpillMI, SpillIndex);
1096     }
1097   } else if (!IsAvailableInStack(DefMBB, CurrLI->reg, ValNo->def,
1098                                  RestoreIndex, SpillIndex, SS)) {
1099     // If it's already split, just restore the value. There is no need to spill
1100     // the def again.
1101     if (!DefMI)
1102       return false; // Def is dead. Do nothing.
1103
1104     if ((SpillMI = FoldSpill(LI->reg, RC, DefMI, Barrier,
1105                             BarrierMBB, SS, RefsInMBB))) {
1106       SpillIndex = LIs->getInstructionIndex(SpillMI);
1107     } else {
1108       // Check if it's possible to insert a spill after the def MI.
1109       MachineBasicBlock::iterator SpillPt;
1110       if (DefMBB == BarrierMBB) {
1111         // Add spill after the def and the last use before the barrier.
1112         SpillPt = findSpillPoint(BarrierMBB, Barrier, DefMI,
1113                                  RefsInMBB, SpillIndex);
1114         if (SpillPt == DefMBB->begin())
1115           return false; // No gap to insert spill.
1116       } else {
1117         SpillPt = findNextEmptySlot(DefMBB, DefMI, SpillIndex);
1118         if (SpillPt == DefMBB->end())
1119           return false; // No gap to insert spill.
1120       }
1121       // Add spill. The store instruction kills the register if def is before
1122       // the barrier in the barrier block.
1123       SS = CreateSpillStackSlot(CurrLI->reg, RC);
1124       TII->storeRegToStackSlot(*DefMBB, SpillPt, CurrLI->reg,
1125                                DefMBB == BarrierMBB, SS, RC);
1126       SpillMI = prior(SpillPt);
1127       LIs->InsertMachineInstrInMaps(SpillMI, SpillIndex);
1128     }
1129   }
1130
1131   // Remember def instruction index to spill index mapping.
1132   if (DefMI && SpillMI)
1133     Def2SpillMap[ValNo->def] = SpillIndex;
1134
1135   // Add restore.
1136   bool FoldedRestore = false;
1137   if (MachineInstr* LMI = FoldRestore(CurrLI->reg, RC, Barrier,
1138                                       BarrierMBB, SS, RefsInMBB)) {
1139     RestorePt = LMI;
1140     RestoreIndex = LIs->getInstructionIndex(RestorePt);
1141     FoldedRestore = true;
1142   } else {
1143     TII->loadRegFromStackSlot(*BarrierMBB, RestorePt, CurrLI->reg, SS, RC);
1144     MachineInstr *LoadMI = prior(RestorePt);
1145     LIs->InsertMachineInstrInMaps(LoadMI, RestoreIndex);
1146   }
1147
1148   // Update spill stack slot live interval.
1149   UpdateSpillSlotInterval(ValNo, LIs->getNextSlot(LIs->getUseIndex(SpillIndex)),
1150                           LIs->getDefIndex(RestoreIndex));
1151
1152   ReconstructLiveInterval(CurrLI);
1153
1154   if (!FoldedRestore) {
1155     MachineInstrIndex RestoreIdx = LIs->getInstructionIndex(prior(RestorePt));
1156     RestoreIdx = LIs->getDefIndex(RestoreIdx);
1157     RenumberValno(CurrLI->findDefinedVNInfoForRegInt(RestoreIdx));
1158   }
1159
1160   ++NumSplits;
1161   return true;
1162 }
1163
1164 /// SplitRegLiveIntervals - Split all register live intervals that cross the
1165 /// barrier that's being processed.
1166 bool
1167 PreAllocSplitting::SplitRegLiveIntervals(const TargetRegisterClass **RCs,
1168                                          SmallPtrSet<LiveInterval*, 8>& Split) {
1169   // First find all the virtual registers whose live intervals are intercepted
1170   // by the current barrier.
1171   SmallVector<LiveInterval*, 8> Intervals;
1172   for (const TargetRegisterClass **RC = RCs; *RC; ++RC) {
1173     // FIXME: If it's not safe to move any instruction that defines the barrier
1174     // register class, then it means there are some special dependencies which
1175     // codegen is not modelling. Ignore these barriers for now.
1176     if (!TII->isSafeToMoveRegClassDefs(*RC))
1177       continue;
1178     std::vector<unsigned> &VRs = MRI->getRegClassVirtRegs(*RC);
1179     for (unsigned i = 0, e = VRs.size(); i != e; ++i) {
1180       unsigned Reg = VRs[i];
1181       if (!LIs->hasInterval(Reg))
1182         continue;
1183       LiveInterval *LI = &LIs->getInterval(Reg);
1184       if (LI->liveAt(BarrierIdx) && !Barrier->readsRegister(Reg))
1185         // Virtual register live interval is intercepted by the barrier. We
1186         // should split and shrink wrap its interval if possible.
1187         Intervals.push_back(LI);
1188     }
1189   }
1190
1191   // Process the affected live intervals.
1192   bool Change = false;
1193   while (!Intervals.empty()) {
1194     if (PreSplitLimit != -1 && (int)NumSplits == PreSplitLimit)
1195       break;
1196     else if (NumSplits == 4)
1197       Change |= Change;
1198     LiveInterval *LI = Intervals.back();
1199     Intervals.pop_back();
1200     bool result = SplitRegLiveInterval(LI);
1201     if (result) Split.insert(LI);
1202     Change |= result;
1203   }
1204
1205   return Change;
1206 }
1207
1208 unsigned PreAllocSplitting::getNumberOfNonSpills(
1209                                   SmallPtrSet<MachineInstr*, 4>& MIs,
1210                                   unsigned Reg, int FrameIndex,
1211                                   bool& FeedsTwoAddr) {
1212   unsigned NonSpills = 0;
1213   for (SmallPtrSet<MachineInstr*, 4>::iterator UI = MIs.begin(), UE = MIs.end();
1214        UI != UE; ++UI) {
1215     int StoreFrameIndex;
1216     unsigned StoreVReg = TII->isStoreToStackSlot(*UI, StoreFrameIndex);
1217     if (StoreVReg != Reg || StoreFrameIndex != FrameIndex)
1218       NonSpills++;
1219
1220     int DefIdx = (*UI)->findRegisterDefOperandIdx(Reg);
1221     if (DefIdx != -1 && (*UI)->isRegTiedToUseOperand(DefIdx))
1222       FeedsTwoAddr = true;
1223   }
1224
1225   return NonSpills;
1226 }
1227
1228 /// removeDeadSpills - After doing splitting, filter through all intervals we've
1229 /// split, and see if any of the spills are unnecessary.  If so, remove them.
1230 bool PreAllocSplitting::removeDeadSpills(SmallPtrSet<LiveInterval*, 8>& split) {
1231   bool changed = false;
1232
1233   // Walk over all of the live intervals that were touched by the splitter,
1234   // and see if we can do any DCE and/or folding.
1235   for (SmallPtrSet<LiveInterval*, 8>::iterator LI = split.begin(),
1236        LE = split.end(); LI != LE; ++LI) {
1237     DenseMap<VNInfo*, SmallPtrSet<MachineInstr*, 4> > VNUseCount;
1238
1239     // First, collect all the uses of the vreg, and sort them by their
1240     // reaching definition (VNInfo).
1241     for (MachineRegisterInfo::use_iterator UI = MRI->use_begin((*LI)->reg),
1242          UE = MRI->use_end(); UI != UE; ++UI) {
1243       MachineInstrIndex index = LIs->getInstructionIndex(&*UI);
1244       index = LIs->getUseIndex(index);
1245
1246       const LiveRange* LR = (*LI)->getLiveRangeContaining(index);
1247       VNUseCount[LR->valno].insert(&*UI);
1248     }
1249
1250     // Now, take the definitions (VNInfo's) one at a time and try to DCE
1251     // and/or fold them away.
1252     for (LiveInterval::vni_iterator VI = (*LI)->vni_begin(),
1253          VE = (*LI)->vni_end(); VI != VE; ++VI) {
1254
1255       if (DeadSplitLimit != -1 && (int)NumDeadSpills == DeadSplitLimit)
1256         return changed;
1257
1258       VNInfo* CurrVN = *VI;
1259
1260       // We don't currently try to handle definitions with PHI kills, because
1261       // it would involve processing more than one VNInfo at once.
1262       if (CurrVN->hasPHIKill()) continue;
1263
1264       // We also don't try to handle the results of PHI joins, since there's
1265       // no defining instruction to analyze.
1266       if (!CurrVN->isDefAccurate() || CurrVN->isUnused()) continue;
1267
1268       // We're only interested in eliminating cruft introduced by the splitter,
1269       // is of the form load-use or load-use-store.  First, check that the
1270       // definition is a load, and remember what stack slot we loaded it from.
1271       MachineInstr* DefMI = LIs->getInstructionFromIndex(CurrVN->def);
1272       int FrameIndex;
1273       if (!TII->isLoadFromStackSlot(DefMI, FrameIndex)) continue;
1274
1275       // If the definition has no uses at all, just DCE it.
1276       if (VNUseCount[CurrVN].size() == 0) {
1277         LIs->RemoveMachineInstrFromMaps(DefMI);
1278         (*LI)->removeValNo(CurrVN);
1279         DefMI->eraseFromParent();
1280         VNUseCount.erase(CurrVN);
1281         NumDeadSpills++;
1282         changed = true;
1283         continue;
1284       }
1285
1286       // Second, get the number of non-store uses of the definition, as well as
1287       // a flag indicating whether it feeds into a later two-address definition.
1288       bool FeedsTwoAddr = false;
1289       unsigned NonSpillCount = getNumberOfNonSpills(VNUseCount[CurrVN],
1290                                                     (*LI)->reg, FrameIndex,
1291                                                     FeedsTwoAddr);
1292
1293       // If there's one non-store use and it doesn't feed a two-addr, then
1294       // this is a load-use-store case that we can try to fold.
1295       if (NonSpillCount == 1 && !FeedsTwoAddr) {
1296         // Start by finding the non-store use MachineInstr.
1297         SmallPtrSet<MachineInstr*, 4>::iterator UI = VNUseCount[CurrVN].begin();
1298         int StoreFrameIndex;
1299         unsigned StoreVReg = TII->isStoreToStackSlot(*UI, StoreFrameIndex);
1300         while (UI != VNUseCount[CurrVN].end() &&
1301                (StoreVReg == (*LI)->reg && StoreFrameIndex == FrameIndex)) {
1302           ++UI;
1303           if (UI != VNUseCount[CurrVN].end())
1304             StoreVReg = TII->isStoreToStackSlot(*UI, StoreFrameIndex);
1305         }
1306         if (UI == VNUseCount[CurrVN].end()) continue;
1307
1308         MachineInstr* use = *UI;
1309
1310         // Attempt to fold it away!
1311         int OpIdx = use->findRegisterUseOperandIdx((*LI)->reg, false);
1312         if (OpIdx == -1) continue;
1313         SmallVector<unsigned, 1> Ops;
1314         Ops.push_back(OpIdx);
1315         if (!TII->canFoldMemoryOperand(use, Ops)) continue;
1316
1317         MachineInstr* NewMI =
1318                           TII->foldMemoryOperand(*use->getParent()->getParent(),
1319                                                  use, Ops, FrameIndex);
1320
1321         if (!NewMI) continue;
1322
1323         // Update relevant analyses.
1324         LIs->RemoveMachineInstrFromMaps(DefMI);
1325         LIs->ReplaceMachineInstrInMaps(use, NewMI);
1326         (*LI)->removeValNo(CurrVN);
1327
1328         DefMI->eraseFromParent();
1329         MachineBasicBlock* MBB = use->getParent();
1330         NewMI = MBB->insert(MBB->erase(use), NewMI);
1331         VNUseCount[CurrVN].erase(use);
1332
1333         // Remove deleted instructions.  Note that we need to remove them from
1334         // the VNInfo->use map as well, just to be safe.
1335         for (SmallPtrSet<MachineInstr*, 4>::iterator II =
1336              VNUseCount[CurrVN].begin(), IE = VNUseCount[CurrVN].end();
1337              II != IE; ++II) {
1338           for (DenseMap<VNInfo*, SmallPtrSet<MachineInstr*, 4> >::iterator
1339                VNI = VNUseCount.begin(), VNE = VNUseCount.end(); VNI != VNE;
1340                ++VNI)
1341             if (VNI->first != CurrVN)
1342               VNI->second.erase(*II);
1343           LIs->RemoveMachineInstrFromMaps(*II);
1344           (*II)->eraseFromParent();
1345         }
1346
1347         VNUseCount.erase(CurrVN);
1348
1349         for (DenseMap<VNInfo*, SmallPtrSet<MachineInstr*, 4> >::iterator
1350              VI = VNUseCount.begin(), VE = VNUseCount.end(); VI != VE; ++VI)
1351           if (VI->second.erase(use))
1352             VI->second.insert(NewMI);
1353
1354         NumDeadSpills++;
1355         changed = true;
1356         continue;
1357       }
1358
1359       // If there's more than one non-store instruction, we can't profitably
1360       // fold it, so bail.
1361       if (NonSpillCount) continue;
1362
1363       // Otherwise, this is a load-store case, so DCE them.
1364       for (SmallPtrSet<MachineInstr*, 4>::iterator UI =
1365            VNUseCount[CurrVN].begin(), UE = VNUseCount[CurrVN].end();
1366            UI != UI; ++UI) {
1367         LIs->RemoveMachineInstrFromMaps(*UI);
1368         (*UI)->eraseFromParent();
1369       }
1370
1371       VNUseCount.erase(CurrVN);
1372
1373       LIs->RemoveMachineInstrFromMaps(DefMI);
1374       (*LI)->removeValNo(CurrVN);
1375       DefMI->eraseFromParent();
1376       NumDeadSpills++;
1377       changed = true;
1378     }
1379   }
1380
1381   return changed;
1382 }
1383
1384 bool PreAllocSplitting::createsNewJoin(LiveRange* LR,
1385                                        MachineBasicBlock* DefMBB,
1386                                        MachineBasicBlock* BarrierMBB) {
1387   if (DefMBB == BarrierMBB)
1388     return false;
1389
1390   if (LR->valno->hasPHIKill())
1391     return false;
1392
1393   MachineInstrIndex MBBEnd = LIs->getMBBEndIdx(BarrierMBB);
1394   if (LR->end < MBBEnd)
1395     return false;
1396
1397   MachineLoopInfo& MLI = getAnalysis<MachineLoopInfo>();
1398   if (MLI.getLoopFor(DefMBB) != MLI.getLoopFor(BarrierMBB))
1399     return true;
1400
1401   MachineDominatorTree& MDT = getAnalysis<MachineDominatorTree>();
1402   SmallPtrSet<MachineBasicBlock*, 4> Visited;
1403   typedef std::pair<MachineBasicBlock*,
1404                     MachineBasicBlock::succ_iterator> ItPair;
1405   SmallVector<ItPair, 4> Stack;
1406   Stack.push_back(std::make_pair(BarrierMBB, BarrierMBB->succ_begin()));
1407
1408   while (!Stack.empty()) {
1409     ItPair P = Stack.back();
1410     Stack.pop_back();
1411
1412     MachineBasicBlock* PredMBB = P.first;
1413     MachineBasicBlock::succ_iterator S = P.second;
1414
1415     if (S == PredMBB->succ_end())
1416       continue;
1417     else if (Visited.count(*S)) {
1418       Stack.push_back(std::make_pair(PredMBB, ++S));
1419       continue;
1420     } else
1421       Stack.push_back(std::make_pair(PredMBB, S+1));
1422
1423     MachineBasicBlock* MBB = *S;
1424     Visited.insert(MBB);
1425
1426     if (MBB == BarrierMBB)
1427       return true;
1428
1429     MachineDomTreeNode* DefMDTN = MDT.getNode(DefMBB);
1430     MachineDomTreeNode* BarrierMDTN = MDT.getNode(BarrierMBB);
1431     MachineDomTreeNode* MDTN = MDT.getNode(MBB)->getIDom();
1432     while (MDTN) {
1433       if (MDTN == DefMDTN)
1434         return true;
1435       else if (MDTN == BarrierMDTN)
1436         break;
1437       MDTN = MDTN->getIDom();
1438     }
1439
1440     MBBEnd = LIs->getMBBEndIdx(MBB);
1441     if (LR->end > MBBEnd)
1442       Stack.push_back(std::make_pair(MBB, MBB->succ_begin()));
1443   }
1444
1445   return false;
1446 }
1447
1448
1449 bool PreAllocSplitting::runOnMachineFunction(MachineFunction &MF) {
1450   CurrMF = &MF;
1451   TM     = &MF.getTarget();
1452   TRI    = TM->getRegisterInfo();
1453   TII    = TM->getInstrInfo();
1454   MFI    = MF.getFrameInfo();
1455   MRI    = &MF.getRegInfo();
1456   LIs    = &getAnalysis<LiveIntervals>();
1457   LSs    = &getAnalysis<LiveStacks>();
1458   VRM    = &getAnalysis<VirtRegMap>();
1459
1460   bool MadeChange = false;
1461
1462   // Make sure blocks are numbered in order.
1463   MF.RenumberBlocks();
1464
1465   MachineBasicBlock *Entry = MF.begin();
1466   SmallPtrSet<MachineBasicBlock*,16> Visited;
1467
1468   SmallPtrSet<LiveInterval*, 8> Split;
1469
1470   for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
1471          DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
1472        DFI != E; ++DFI) {
1473     BarrierMBB = *DFI;
1474     for (MachineBasicBlock::iterator I = BarrierMBB->begin(),
1475            E = BarrierMBB->end(); I != E; ++I) {
1476       Barrier = &*I;
1477       const TargetRegisterClass **BarrierRCs =
1478         Barrier->getDesc().getRegClassBarriers();
1479       if (!BarrierRCs)
1480         continue;
1481       BarrierIdx = LIs->getInstructionIndex(Barrier);
1482       MadeChange |= SplitRegLiveIntervals(BarrierRCs, Split);
1483     }
1484   }
1485
1486   MadeChange |= removeDeadSpills(Split);
1487
1488   return MadeChange;
1489 }