lib/CodeGen/SelectionDAG/FastISel.cpp

   1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the implementation of the FastISel class.
  11 //
  12 // "Fast" instruction selection is designed to emit very poor code quickly.
  13 // Also, it is not designed to be able to do much lowering, so most illegal
  14 // types (e.g. i64 on 32-bit targets) and operations are not supported.  It is
  15 // also not intended to be able to do much optimization, except in a few cases
  16 // where doing optimizations reduces overall compile time.  For example, folding
  17 // constants into immediate fields is often done, because it's cheap and it
  18 // reduces the number of instructions later phases have to examine.
  19 //
  20 // "Fast" instruction selection is able to fail gracefully and transfer
  21 // control to the SelectionDAG selector for operations that it doesn't
  22 // support.  In many cases, this allows us to avoid duplicating a lot of
  23 // the complicated lowering logic that SelectionDAG currently has.
  24 //
  25 // The intended use for "fast" instruction selection is "-O0" mode
  26 // compilation, where the quality of the generated code is irrelevant when
  27 // weighed against the speed at which the code can be generated.  Also,
  28 // at -O0, the LLVM optimizers are not running, and this makes the
  29 // compile time of codegen a much higher portion of the overall compile
  30 // time.  Despite its limitations, "fast" instruction selection is able to
  31 // handle enough code on its own to provide noticeable overall speedups
  32 // in -O0 compiles.
  33 //
  34 // Basic operations are supported in a target-independent way, by reading
  35 // the same instruction descriptions that the SelectionDAG selector reads,
  36 // and identifying simple arithmetic operations that can be directly selected
  37 // from simple operators.  More complicated operations currently require
  38 // target-specific code.
  39 //
  40 //===----------------------------------------------------------------------===//
  41
  42 #include "llvm/Function.h"
  43 #include "llvm/GlobalVariable.h"
  44 #include "llvm/Instructions.h"
  45 #include "llvm/IntrinsicInst.h"
  46 #include "llvm/CodeGen/FastISel.h"
  47 #include "llvm/CodeGen/MachineInstrBuilder.h"
  48 #include "llvm/CodeGen/MachineModuleInfo.h"
  49 #include "llvm/CodeGen/MachineRegisterInfo.h"
  50 #include "llvm/CodeGen/DwarfWriter.h"
  51 #include "llvm/Analysis/DebugInfo.h"
  52 #include "llvm/Target/TargetData.h"
  53 #include "llvm/Target/TargetInstrInfo.h"
  54 #include "llvm/Target/TargetLowering.h"
  55 #include "llvm/Target/TargetMachine.h"
  56 #include "SelectionDAGBuild.h"
  57 using namespace llvm;
  58
  59 unsigned FastISel::getRegForValue(Value *V) {
  60   MVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
  61   // Don't handle non-simple values in FastISel.
  62   if (!RealVT.isSimple())
  63     return 0;
  64
  65   // Ignore illegal types. We must do this before looking up the value
  66   // in ValueMap because Arguments are given virtual registers regardless
  67   // of whether FastISel can handle them.
  68   MVT::SimpleValueType VT = RealVT.getSimpleVT();
  69   if (!TLI.isTypeLegal(VT)) {
  70     // Promote MVT::i1 to a legal type though, because it's common and easy.
  71     if (VT == MVT::i1)
  72       VT = TLI.getTypeToTransformTo(VT).getSimpleVT();
  73     else
  74       return 0;
  75   }
  76
  77   // Look up the value to see if we already have a register for it. We
  78   // cache values defined by Instructions across blocks, and other values
  79   // only locally. This is because Instructions already have the SSA
  80   // def-dominatess-use requirement enforced.
  81   if (ValueMap.count(V))
  82     return ValueMap[V];
  83   unsigned Reg = LocalValueMap[V];
  84   if (Reg != 0)
  85     return Reg;
  86
  87   if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
  88     if (CI->getValue().getActiveBits() <= 64)
  89       Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
  90   } else if (isa<AllocaInst>(V)) {
  91     Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
  92   } else if (isa<ConstantPointerNull>(V)) {
  93     // Translate this as an integer zero so that it can be
  94     // local-CSE'd with actual integer zeros.
  95     Reg = getRegForValue(Constant::getNullValue(TD.getIntPtrType()));
  96   } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
  97     Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
  98
  99     if (!Reg) {
 100       const APFloat &Flt = CF->getValueAPF();
 101       MVT IntVT = TLI.getPointerTy();
 102
 103       uint64_t x[2];
 104       uint32_t IntBitWidth = IntVT.getSizeInBits();
 105       bool isExact;
 106       (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
 107                                 APFloat::rmTowardZero, &isExact);
 108       if (isExact) {
 109         APInt IntVal(IntBitWidth, 2, x);
 110
 111         unsigned IntegerReg =
 112           getRegForValue(ConstantInt::get(V->getContext(), IntVal));
 113         if (IntegerReg != 0)
 114           Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
 115       }
 116     }
 117   } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
 118     if (!SelectOperator(CE, CE->getOpcode())) return 0;
 119     Reg = LocalValueMap[CE];
 120   } else if (isa<UndefValue>(V)) {
 121     Reg = createResultReg(TLI.getRegClassFor(VT));
 122     BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
 123   }
 124
 125   // If target-independent code couldn't handle the value, give target-specific
 126   // code a try.
 127   if (!Reg && isa<Constant>(V))
 128     Reg = TargetMaterializeConstant(cast<Constant>(V));
 129
 130   // Don't cache constant materializations in the general ValueMap.
 131   // To do so would require tracking what uses they dominate.
 132   if (Reg != 0)
 133     LocalValueMap[V] = Reg;
 134   return Reg;
 135 }
 136
 137 unsigned FastISel::lookUpRegForValue(Value *V) {
 138   // Look up the value to see if we already have a register for it. We
 139   // cache values defined by Instructions across blocks, and other values
 140   // only locally. This is because Instructions already have the SSA
 141   // def-dominatess-use requirement enforced.
 142   if (ValueMap.count(V))
 143     return ValueMap[V];
 144   return LocalValueMap[V];
 145 }
 146
 147 /// UpdateValueMap - Update the value map to include the new mapping for this
 148 /// instruction, or insert an extra copy to get the result in a previous
 149 /// determined register.
 150 /// NOTE: This is only necessary because we might select a block that uses
 151 /// a value before we select the block that defines the value.  It might be
 152 /// possible to fix this by selecting blocks in reverse postorder.
 153 unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) {
 154   if (!isa<Instruction>(I)) {
 155     LocalValueMap[I] = Reg;
 156     return Reg;
 157   }
 158
 159   unsigned &AssignedReg = ValueMap[I];
 160   if (AssignedReg == 0)
 161     AssignedReg = Reg;
 162   else if (Reg != AssignedReg) {
 163     const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
 164     TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
 165                      Reg, RegClass, RegClass);
 166   }
 167   return AssignedReg;
 168 }
 169
 170 unsigned FastISel::getRegForGEPIndex(Value *Idx) {
 171   unsigned IdxN = getRegForValue(Idx);
 172   if (IdxN == 0)
 173     // Unhandled operand. Halt "fast" selection and bail.
 174     return 0;
 175
 176   // If the index is smaller or larger than intptr_t, truncate or extend it.
 177   MVT PtrVT = TLI.getPointerTy();
 178   MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
 179   if (IdxVT.bitsLT(PtrVT))
 180     IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
 181                       ISD::SIGN_EXTEND, IdxN);
 182   else if (IdxVT.bitsGT(PtrVT))
 183     IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
 184                       ISD::TRUNCATE, IdxN);
 185   return IdxN;
 186 }
 187
 188 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
 189 /// which has an opcode which directly corresponds to the given ISD opcode.
 190 ///
 191 bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
 192   MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
 193   if (VT == MVT::Other || !VT.isSimple())
 194     // Unhandled type. Halt "fast" selection and bail.
 195     return false;
 196
 197   // We only handle legal types. For example, on x86-32 the instruction
 198   // selector contains all of the 64-bit instructions from x86-64,
 199   // under the assumption that i64 won't be used if the target doesn't
 200   // support it.
 201   if (!TLI.isTypeLegal(VT)) {
 202     // MVT::i1 is special. Allow AND, OR, or XOR because they
 203     // don't require additional zeroing, which makes them easy.
 204     if (VT == MVT::i1 &&
 205         (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
 206          ISDOpcode == ISD::XOR))
 207       VT = TLI.getTypeToTransformTo(VT);
 208     else
 209       return false;
 210   }
 211
 212   unsigned Op0 = getRegForValue(I->getOperand(0));
 213   if (Op0 == 0)
 214     // Unhandled operand. Halt "fast" selection and bail.
 215     return false;
 216
 217   // Check if the second operand is a constant and handle it appropriately.
 218   if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
 219     unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
 220                                      ISDOpcode, Op0, CI->getZExtValue());
 221     if (ResultReg != 0) {
 222       // We successfully emitted code for the given LLVM Instruction.
 223       UpdateValueMap(I, ResultReg);
 224       return true;
 225     }
 226   }
 227
 228   // Check if the second operand is a constant float.
 229   if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
 230     unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
 231                                      ISDOpcode, Op0, CF);
 232     if (ResultReg != 0) {
 233       // We successfully emitted code for the given LLVM Instruction.
 234       UpdateValueMap(I, ResultReg);
 235       return true;
 236     }
 237   }
 238
 239   unsigned Op1 = getRegForValue(I->getOperand(1));
 240   if (Op1 == 0)
 241     // Unhandled operand. Halt "fast" selection and bail.
 242     return false;
 243
 244   // Now we have both operands in registers. Emit the instruction.
 245   unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
 246                                    ISDOpcode, Op0, Op1);
 247   if (ResultReg == 0)
 248     // Target-specific code wasn't able to find a machine opcode for
 249     // the given ISD opcode and type. Halt "fast" selection and bail.
 250     return false;
 251
 252   // We successfully emitted code for the given LLVM Instruction.
 253   UpdateValueMap(I, ResultReg);
 254   return true;
 255 }
 256
 257 bool FastISel::SelectGetElementPtr(User *I) {
 258   unsigned N = getRegForValue(I->getOperand(0));
 259   if (N == 0)
 260     // Unhandled operand. Halt "fast" selection and bail.
 261     return false;
 262
 263   const Type *Ty = I->getOperand(0)->getType();
 264   MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
 265   for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
 266        OI != E; ++OI) {
 267     Value *Idx = *OI;
 268     if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
 269       unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
 270       if (Field) {
 271         // N = N + Offset
 272         uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
 273         // FIXME: This can be optimized by combining the add with a
 274         // subsequent one.
 275         N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
 276         if (N == 0)
 277           // Unhandled operand. Halt "fast" selection and bail.
 278           return false;
 279       }
 280       Ty = StTy->getElementType(Field);
 281     } else {
 282       Ty = cast<SequentialType>(Ty)->getElementType();
 283
 284       // If this is a constant subscript, handle it quickly.
 285       if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
 286         if (CI->getZExtValue() == 0) continue;
 287         uint64_t Offs =
 288           TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
 289         N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
 290         if (N == 0)
 291           // Unhandled operand. Halt "fast" selection and bail.
 292           return false;
 293         continue;
 294       }
 295
 296       // N = N + Idx * ElementSize;
 297       uint64_t ElementSize = TD.getTypeAllocSize(Ty);
 298       unsigned IdxN = getRegForGEPIndex(Idx);
 299       if (IdxN == 0)
 300         // Unhandled operand. Halt "fast" selection and bail.
 301         return false;
 302
 303       if (ElementSize != 1) {
 304         IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
 305         if (IdxN == 0)
 306           // Unhandled operand. Halt "fast" selection and bail.
 307           return false;
 308       }
 309       N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
 310       if (N == 0)
 311         // Unhandled operand. Halt "fast" selection and bail.
 312         return false;
 313     }
 314   }
 315
 316   // We successfully emitted code for the given LLVM Instruction.
 317   UpdateValueMap(I, N);
 318   return true;
 319 }
 320
 321 bool FastISel::SelectCall(User *I) {
 322   Function *F = cast<CallInst>(I)->getCalledFunction();
 323   if (!F) return false;
 324
 325   unsigned IID = F->getIntrinsicID();
 326   switch (IID) {
 327   default: break;
 328   case Intrinsic::dbg_stoppoint: {
 329     DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
 330     if (isValidDebugInfoIntrinsic(*SPI, CodeGenOpt::None))
 331       setCurDebugLoc(ExtractDebugLocation(*SPI, MF.getDebugLocInfo()));
 332     return true;
 333   }
 334   case Intrinsic::dbg_region_start: {
 335     DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
 336     if (isValidDebugInfoIntrinsic(*RSI, CodeGenOpt::None) && DW
 337         && DW->ShouldEmitDwarfDebug()) {
 338       unsigned ID =
 339         DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext()));
 340       const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
 341       BuildMI(MBB, DL, II).addImm(ID);
 342     }
 343     return true;
 344   }
 345   case Intrinsic::dbg_region_end: {
 346     DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
 347     if (isValidDebugInfoIntrinsic(*REI, CodeGenOpt::None) && DW
 348         && DW->ShouldEmitDwarfDebug()) {
 349      unsigned ID = 0;
 350      DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext()));
 351      if (isInlinedFnEnd(*REI, MF.getFunction())) {
 352         // This is end of an inlined function.
 353         const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
 354         ID = DW->RecordInlinedFnEnd(Subprogram);
 355         if (ID)
 356           // Returned ID is 0 if this is unbalanced "end of inlined
 357           // scope". This could happen if optimizer eats dbg intrinsics
 358           // or "beginning of inlined scope" is not recoginized due to
 359           // missing location info. In such cases, ignore this region.end.
 360           BuildMI(MBB, DL, II).addImm(ID);
 361       } else {
 362         const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
 363         ID =  DW->RecordRegionEnd(cast<GlobalVariable>(REI->getContext()));
 364         BuildMI(MBB, DL, II).addImm(ID);
 365       }
 366     }
 367     return true;
 368   }
 369   case Intrinsic::dbg_func_start: {
 370     DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
 371     if (!isValidDebugInfoIntrinsic(*FSI, CodeGenOpt::None) || !DW
 372         || !DW->ShouldEmitDwarfDebug())
 373       return true;
 374
 375     if (isInlinedFnStart(*FSI, MF.getFunction())) {
 376       // This is a beginning of an inlined function.
 377
 378       // If llvm.dbg.func.start is seen in a new block before any
 379       // llvm.dbg.stoppoint intrinsic then the location info is unknown.
 380       // FIXME : Why DebugLoc is reset at the beginning of each block ?
 381       DebugLoc PrevLoc = DL;
 382       if (PrevLoc.isUnknown())
 383         return true;
 384       // Record the source line.
 385       setCurDebugLoc(ExtractDebugLocation(*FSI, MF.getDebugLocInfo()));
 386
 387       DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc);
 388       DISubprogram SP(cast<GlobalVariable>(FSI->getSubprogram()));
 389       unsigned LabelID = DW->RecordInlinedFnStart(SP,
 390                                                   DICompileUnit(PrevLocTpl.CompileUnit),
 391                                                   PrevLocTpl.Line,
 392                                                   PrevLocTpl.Col);
 393       const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
 394       BuildMI(MBB, DL, II).addImm(LabelID);
 395       return true;
 396     }
 397
 398     // This is a beginning of a new function.
 399     MF.setDefaultDebugLoc(ExtractDebugLocation(*FSI, MF.getDebugLocInfo()));
 400
 401     // llvm.dbg.func_start also defines beginning of function scope.
 402     DW->RecordRegionStart(cast<GlobalVariable>(FSI->getSubprogram()));
 403     return true;
 404   }
 405   case Intrinsic::dbg_declare: {
 406     DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
 407     if (!isValidDebugInfoIntrinsic(*DI, CodeGenOpt::None) || !DW
 408         || !DW->ShouldEmitDwarfDebug())
 409       return true;
 410
 411     Value *Variable = DI->getVariable();
 412     Value *Address = DI->getAddress();
 413     if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
 414       Address = BCI->getOperand(0);
 415     AllocaInst *AI = dyn_cast<AllocaInst>(Address);
 416     // Don't handle byval struct arguments or VLAs, for example.
 417     if (!AI) break;
 418     DenseMap<const AllocaInst*, int>::iterator SI =
 419       StaticAllocaMap.find(AI);
 420     if (SI == StaticAllocaMap.end()) break; // VLAs.
 421     int FI = SI->second;
 422
 423     // Determine the debug globalvariable.
 424     GlobalValue *GV = cast<GlobalVariable>(Variable);
 425
 426     // Build the DECLARE instruction.
 427     const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE);
 428     MachineInstr *DeclareMI
 429       = BuildMI(MBB, DL, II).addFrameIndex(FI).addGlobalAddress(GV);
 430     DIVariable DV(cast<GlobalVariable>(GV));
 431     DW->RecordVariableScope(DV, DeclareMI);
 432     return true;
 433   }
 434   case Intrinsic::eh_exception: {
 435     MVT VT = TLI.getValueType(I->getType());
 436     switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
 437     default: break;
 438     case TargetLowering::Expand: {
 439       assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!");
 440       unsigned Reg = TLI.getExceptionAddressRegister();
 441       const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
 442       unsigned ResultReg = createResultReg(RC);
 443       bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
 444                                            Reg, RC, RC);
 445       assert(InsertedCopy && "Can't copy address registers!");
 446       InsertedCopy = InsertedCopy;
 447       UpdateValueMap(I, ResultReg);
 448       return true;
 449     }
 450     }
 451     break;
 452   }
 453   case Intrinsic::eh_selector_i32:
 454   case Intrinsic::eh_selector_i64: {
 455     MVT VT = TLI.getValueType(I->getType());
 456     switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
 457     default: break;
 458     case TargetLowering::Expand: {
 459       MVT VT = (IID == Intrinsic::eh_selector_i32 ?
 460                            MVT::i32 : MVT::i64);
 461
 462       if (MMI) {
 463         if (MBB->isLandingPad())
 464           AddCatchInfo(*cast<CallInst>(I), MMI, MBB);
 465         else {
 466 #ifndef NDEBUG
 467           CatchInfoLost.insert(cast<CallInst>(I));
 468 #endif
 469           // FIXME: Mark exception selector register as live in.  Hack for PR1508.
 470           unsigned Reg = TLI.getExceptionSelectorRegister();
 471           if (Reg) MBB->addLiveIn(Reg);
 472         }
 473
 474         unsigned Reg = TLI.getExceptionSelectorRegister();
 475         const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
 476         unsigned ResultReg = createResultReg(RC);
 477         bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
 478                                              Reg, RC, RC);
 479         assert(InsertedCopy && "Can't copy address registers!");
 480         InsertedCopy = InsertedCopy;
 481         UpdateValueMap(I, ResultReg);
 482       } else {
 483         unsigned ResultReg =
 484           getRegForValue(Constant::getNullValue(I->getType()));
 485         UpdateValueMap(I, ResultReg);
 486       }
 487       return true;
 488     }
 489     }
 490     break;
 491   }
 492   }
 493   return false;
 494 }
 495
 496 bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
 497   MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
 498   MVT DstVT = TLI.getValueType(I->getType());
 499
 500   if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
 501       DstVT == MVT::Other || !DstVT.isSimple())
 502     // Unhandled type. Halt "fast" selection and bail.
 503     return false;
 504
 505   // Check if the destination type is legal. Or as a special case,
 506   // it may be i1 if we're doing a truncate because that's
 507   // easy and somewhat common.
 508   if (!TLI.isTypeLegal(DstVT))
 509     if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
 510       // Unhandled type. Halt "fast" selection and bail.
 511       return false;
 512
 513   // Check if the source operand is legal. Or as a special case,
 514   // it may be i1 if we're doing zero-extension because that's
 515   // easy and somewhat common.
 516   if (!TLI.isTypeLegal(SrcVT))
 517     if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
 518       // Unhandled type. Halt "fast" selection and bail.
 519       return false;
 520
 521   unsigned InputReg = getRegForValue(I->getOperand(0));
 522   if (!InputReg)
 523     // Unhandled operand.  Halt "fast" selection and bail.
 524     return false;
 525
 526   // If the operand is i1, arrange for the high bits in the register to be zero.
 527   if (SrcVT == MVT::i1) {
 528    SrcVT = TLI.getTypeToTransformTo(SrcVT);
 529    InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
 530    if (!InputReg)
 531      return false;
 532   }
 533   // If the result is i1, truncate to the target's type for i1 first.
 534   if (DstVT == MVT::i1)
 535     DstVT = TLI.getTypeToTransformTo(DstVT);
 536
 537   unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
 538                                   DstVT.getSimpleVT(),
 539                                   Opcode,
 540                                   InputReg);
 541   if (!ResultReg)
 542     return false;
 543
 544   UpdateValueMap(I, ResultReg);
 545   return true;
 546 }
 547
 548 bool FastISel::SelectBitCast(User *I) {
 549   // If the bitcast doesn't change the type, just use the operand value.
 550   if (I->getType() == I->getOperand(0)->getType()) {
 551     unsigned Reg = getRegForValue(I->getOperand(0));
 552     if (Reg == 0)
 553       return false;
 554     UpdateValueMap(I, Reg);
 555     return true;
 556   }
 557
 558   // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
 559   MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
 560   MVT DstVT = TLI.getValueType(I->getType());
 561
 562   if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
 563       DstVT == MVT::Other || !DstVT.isSimple() ||
 564       !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
 565     // Unhandled type. Halt "fast" selection and bail.
 566     return false;
 567
 568   unsigned Op0 = getRegForValue(I->getOperand(0));
 569   if (Op0 == 0)
 570     // Unhandled operand. Halt "fast" selection and bail.
 571     return false;
 572
 573   // First, try to perform the bitcast by inserting a reg-reg copy.
 574   unsigned ResultReg = 0;
 575   if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
 576     TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
 577     TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
 578     ResultReg = createResultReg(DstClass);
 579
 580     bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
 581                                          Op0, DstClass, SrcClass);
 582     if (!InsertedCopy)
 583       ResultReg = 0;
 584   }
 585
 586   // If the reg-reg copy failed, select a BIT_CONVERT opcode.
 587   if (!ResultReg)
 588     ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
 589                            ISD::BIT_CONVERT, Op0);
 590
 591   if (!ResultReg)
 592     return false;
 593
 594   UpdateValueMap(I, ResultReg);
 595   return true;
 596 }
 597
 598 bool
 599 FastISel::SelectInstruction(Instruction *I) {
 600   return SelectOperator(I, I->getOpcode());
 601 }
 602
 603 /// FastEmitBranch - Emit an unconditional branch to the given block,
 604 /// unless it is the immediate (fall-through) successor, and update
 605 /// the CFG.
 606 void
 607 FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
 608   MachineFunction::iterator NextMBB =
 609      next(MachineFunction::iterator(MBB));
 610
 611   if (MBB->isLayoutSuccessor(MSucc)) {
 612     // The unconditional fall-through case, which needs no instructions.
 613   } else {
 614     // The unconditional branch case.
 615     TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
 616   }
 617   MBB->addSuccessor(MSucc);
 618 }
 619
 620 bool
 621 FastISel::SelectOperator(User *I, unsigned Opcode) {
 622   switch (Opcode) {
 623   case Instruction::Add:
 624     return SelectBinaryOp(I, ISD::ADD);
 625   case Instruction::FAdd:
 626     return SelectBinaryOp(I, ISD::FADD);
 627   case Instruction::Sub:
 628     return SelectBinaryOp(I, ISD::SUB);
 629   case Instruction::FSub:
 630     return SelectBinaryOp(I, ISD::FSUB);
 631   case Instruction::Mul:
 632     return SelectBinaryOp(I, ISD::MUL);
 633   case Instruction::FMul:
 634     return SelectBinaryOp(I, ISD::FMUL);
 635   case Instruction::SDiv:
 636     return SelectBinaryOp(I, ISD::SDIV);
 637   case Instruction::UDiv:
 638     return SelectBinaryOp(I, ISD::UDIV);
 639   case Instruction::FDiv:
 640     return SelectBinaryOp(I, ISD::FDIV);
 641   case Instruction::SRem:
 642     return SelectBinaryOp(I, ISD::SREM);
 643   case Instruction::URem:
 644     return SelectBinaryOp(I, ISD::UREM);
 645   case Instruction::FRem:
 646     return SelectBinaryOp(I, ISD::FREM);
 647   case Instruction::Shl:
 648     return SelectBinaryOp(I, ISD::SHL);
 649   case Instruction::LShr:
 650     return SelectBinaryOp(I, ISD::SRL);
 651   case Instruction::AShr:
 652     return SelectBinaryOp(I, ISD::SRA);
 653   case Instruction::And:
 654     return SelectBinaryOp(I, ISD::AND);
 655   case Instruction::Or:
 656     return SelectBinaryOp(I, ISD::OR);
 657   case Instruction::Xor:
 658     return SelectBinaryOp(I, ISD::XOR);
 659
 660   case Instruction::GetElementPtr:
 661     return SelectGetElementPtr(I);
 662
 663   case Instruction::Br: {
 664     BranchInst *BI = cast<BranchInst>(I);
 665
 666     if (BI->isUnconditional()) {
 667       BasicBlock *LLVMSucc = BI->getSuccessor(0);
 668       MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
 669       FastEmitBranch(MSucc);
 670       return true;
 671     }
 672
 673     // Conditional branches are not handed yet.
 674     // Halt "fast" selection and bail.
 675     return false;
 676   }
 677
 678   case Instruction::Unreachable:
 679     // Nothing to emit.
 680     return true;
 681
 682   case Instruction::PHI:
 683     // PHI nodes are already emitted.
 684     return true;
 685
 686   case Instruction::Alloca:
 687     // FunctionLowering has the static-sized case covered.
 688     if (StaticAllocaMap.count(cast<AllocaInst>(I)))
 689       return true;
 690
 691     // Dynamic-sized alloca is not handled yet.
 692     return false;
 693
 694   case Instruction::Call:
 695     return SelectCall(I);
 696
 697   case Instruction::BitCast:
 698     return SelectBitCast(I);
 699
 700   case Instruction::FPToSI:
 701     return SelectCast(I, ISD::FP_TO_SINT);
 702   case Instruction::ZExt:
 703     return SelectCast(I, ISD::ZERO_EXTEND);
 704   case Instruction::SExt:
 705     return SelectCast(I, ISD::SIGN_EXTEND);
 706   case Instruction::Trunc:
 707     return SelectCast(I, ISD::TRUNCATE);
 708   case Instruction::SIToFP:
 709     return SelectCast(I, ISD::SINT_TO_FP);
 710
 711   case Instruction::IntToPtr: // Deliberate fall-through.
 712   case Instruction::PtrToInt: {
 713     MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
 714     MVT DstVT = TLI.getValueType(I->getType());
 715     if (DstVT.bitsGT(SrcVT))
 716       return SelectCast(I, ISD::ZERO_EXTEND);
 717     if (DstVT.bitsLT(SrcVT))
 718       return SelectCast(I, ISD::TRUNCATE);
 719     unsigned Reg = getRegForValue(I->getOperand(0));
 720     if (Reg == 0) return false;
 721     UpdateValueMap(I, Reg);
 722     return true;
 723   }
 724
 725   default:
 726     // Unhandled instruction. Halt "fast" selection and bail.
 727     return false;
 728   }
 729 }
 730
 731 FastISel::FastISel(MachineFunction &mf,
 732                    MachineModuleInfo *mmi,
 733                    DwarfWriter *dw,
 734                    DenseMap<const Value *, unsigned> &vm,
 735                    DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
 736                    DenseMap<const AllocaInst *, int> &am
 737 #ifndef NDEBUG
 738                    , SmallSet<Instruction*, 8> &cil
 739 #endif
 740                    )
 741   : MBB(0),
 742     ValueMap(vm),
 743     MBBMap(bm),
 744     StaticAllocaMap(am),
 745 #ifndef NDEBUG
 746     CatchInfoLost(cil),
 747 #endif
 748     MF(mf),
 749     MMI(mmi),
 750     DW(dw),
 751     MRI(MF.getRegInfo()),
 752     MFI(*MF.getFrameInfo()),
 753     MCP(*MF.getConstantPool()),
 754     TM(MF.getTarget()),
 755     TD(*TM.getTargetData()),
 756     TII(*TM.getInstrInfo()),
 757     TLI(*TM.getTargetLowering()) {
 758 }
 759
 760 FastISel::~FastISel() {}
 761
 762 unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType,
 763                              ISD::NodeType) {
 764   return 0;
 765 }
 766
 767 unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
 768                               ISD::NodeType, unsigned /*Op0*/) {
 769   return 0;
 770 }
 771
 772 unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
 773                                ISD::NodeType, unsigned /*Op0*/,
 774                                unsigned /*Op0*/) {
 775   return 0;
 776 }
 777
 778 unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
 779                               ISD::NodeType, uint64_t /*Imm*/) {
 780   return 0;
 781 }
 782
 783 unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
 784                               ISD::NodeType, ConstantFP * /*FPImm*/) {
 785   return 0;
 786 }
 787
 788 unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
 789                                ISD::NodeType, unsigned /*Op0*/,
 790                                uint64_t /*Imm*/) {
 791   return 0;
 792 }
 793
 794 unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
 795                                ISD::NodeType, unsigned /*Op0*/,
 796                                ConstantFP * /*FPImm*/) {
 797   return 0;
 798 }
 799
 800 unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
 801                                 ISD::NodeType,
 802                                 unsigned /*Op0*/, unsigned /*Op1*/,
 803                                 uint64_t /*Imm*/) {
 804   return 0;
 805 }
 806
 807 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
 808 /// to emit an instruction with an immediate operand using FastEmit_ri.
 809 /// If that fails, it materializes the immediate into a register and try
 810 /// FastEmit_rr instead.
 811 unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
 812                                 unsigned Op0, uint64_t Imm,
 813                                 MVT::SimpleValueType ImmType) {
 814   // First check if immediate type is legal. If not, we can't use the ri form.
 815   unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
 816   if (ResultReg != 0)
 817     return ResultReg;
 818   unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
 819   if (MaterialReg == 0)
 820     return 0;
 821   return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
 822 }
 823
 824 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
 825 /// to emit an instruction with a floating-point immediate operand using
 826 /// FastEmit_rf. If that fails, it materializes the immediate into a register
 827 /// and try FastEmit_rr instead.
 828 unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
 829                                 unsigned Op0, ConstantFP *FPImm,
 830                                 MVT::SimpleValueType ImmType) {
 831   // First check if immediate type is legal. If not, we can't use the rf form.
 832   unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
 833   if (ResultReg != 0)
 834     return ResultReg;
 835
 836   // Materialize the constant in a register.
 837   unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
 838   if (MaterialReg == 0) {
 839     // If the target doesn't have a way to directly enter a floating-point
 840     // value into a register, use an alternate approach.
 841     // TODO: The current approach only supports floating-point constants
 842     // that can be constructed by conversion from integer values. This should
 843     // be replaced by code that creates a load from a constant-pool entry,
 844     // which will require some target-specific work.
 845     const APFloat &Flt = FPImm->getValueAPF();
 846     MVT IntVT = TLI.getPointerTy();
 847
 848     uint64_t x[2];
 849     uint32_t IntBitWidth = IntVT.getSizeInBits();
 850     bool isExact;
 851     (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
 852                              APFloat::rmTowardZero, &isExact);
 853     if (!isExact)
 854       return 0;
 855     APInt IntVal(IntBitWidth, 2, x);
 856
 857     unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
 858                                      ISD::Constant, IntVal.getZExtValue());
 859     if (IntegerReg == 0)
 860       return 0;
 861     MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
 862                              ISD::SINT_TO_FP, IntegerReg);
 863     if (MaterialReg == 0)
 864       return 0;
 865   }
 866   return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
 867 }
 868
 869 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
 870   return MRI.createVirtualRegister(RC);
 871 }
 872
 873 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
 874                                  const TargetRegisterClass* RC) {
 875   unsigned ResultReg = createResultReg(RC);
 876   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 877
 878   BuildMI(MBB, DL, II, ResultReg);
 879   return ResultReg;
 880 }
 881
 882 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
 883                                   const TargetRegisterClass *RC,
 884                                   unsigned Op0) {
 885   unsigned ResultReg = createResultReg(RC);
 886   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 887
 888   if (II.getNumDefs() >= 1)
 889     BuildMI(MBB, DL, II, ResultReg).addReg(Op0);
 890   else {
 891     BuildMI(MBB, DL, II).addReg(Op0);
 892     bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
 893                                          II.ImplicitDefs[0], RC, RC);
 894     if (!InsertedCopy)
 895       ResultReg = 0;
 896   }
 897
 898   return ResultReg;
 899 }
 900
 901 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
 902                                    const TargetRegisterClass *RC,
 903                                    unsigned Op0, unsigned Op1) {
 904   unsigned ResultReg = createResultReg(RC);
 905   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 906
 907   if (II.getNumDefs() >= 1)
 908     BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1);
 909   else {
 910     BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1);
 911     bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
 912                                          II.ImplicitDefs[0], RC, RC);
 913     if (!InsertedCopy)
 914       ResultReg = 0;
 915   }
 916   return ResultReg;
 917 }
 918
 919 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
 920                                    const TargetRegisterClass *RC,
 921                                    unsigned Op0, uint64_t Imm) {
 922   unsigned ResultReg = createResultReg(RC);
 923   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 924
 925   if (II.getNumDefs() >= 1)
 926     BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm);
 927   else {
 928     BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm);
 929     bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
 930                                          II.ImplicitDefs[0], RC, RC);
 931     if (!InsertedCopy)
 932       ResultReg = 0;
 933   }
 934   return ResultReg;
 935 }
 936
 937 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
 938                                    const TargetRegisterClass *RC,
 939                                    unsigned Op0, ConstantFP *FPImm) {
 940   unsigned ResultReg = createResultReg(RC);
 941   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 942
 943   if (II.getNumDefs() >= 1)
 944     BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm);
 945   else {
 946     BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm);
 947     bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
 948                                          II.ImplicitDefs[0], RC, RC);
 949     if (!InsertedCopy)
 950       ResultReg = 0;
 951   }
 952   return ResultReg;
 953 }
 954
 955 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
 956                                     const TargetRegisterClass *RC,
 957                                     unsigned Op0, unsigned Op1, uint64_t Imm) {
 958   unsigned ResultReg = createResultReg(RC);
 959   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 960
 961   if (II.getNumDefs() >= 1)
 962     BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
 963   else {
 964     BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm);
 965     bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
 966                                          II.ImplicitDefs[0], RC, RC);
 967     if (!InsertedCopy)
 968       ResultReg = 0;
 969   }
 970   return ResultReg;
 971 }
 972
 973 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
 974                                   const TargetRegisterClass *RC,
 975                                   uint64_t Imm) {
 976   unsigned ResultReg = createResultReg(RC);
 977   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 978
 979   if (II.getNumDefs() >= 1)
 980     BuildMI(MBB, DL, II, ResultReg).addImm(Imm);
 981   else {
 982     BuildMI(MBB, DL, II).addImm(Imm);
 983     bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
 984                                          II.ImplicitDefs[0], RC, RC);
 985     if (!InsertedCopy)
 986       ResultReg = 0;
 987   }
 988   return ResultReg;
 989 }
 990
 991 unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT,
 992                                               unsigned Op0, uint32_t Idx) {
 993   const TargetRegisterClass* RC = MRI.getRegClass(Op0);
 994
 995   unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
 996   const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
 997
 998   if (II.getNumDefs() >= 1)
 999     BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx);
1000   else {
1001     BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx);
1002     bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1003                                          II.ImplicitDefs[0], RC, RC);
1004     if (!InsertedCopy)
1005       ResultReg = 0;
1006   }
1007   return ResultReg;
1008 }
1009
1010 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
1011 /// with all but the least significant bit set to zero.
1012 unsigned FastISel::FastEmitZExtFromI1(MVT::SimpleValueType VT, unsigned Op) {
1013   return FastEmit_ri(VT, VT, ISD::AND, Op, 1);
1014 }