lib/CodeGen/SelectionDAG/FastISel.cpp

   1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the implementation of the FastISel class.
  11 //
  12 // "Fast" instruction selection is designed to emit very poor code quickly.
  13 // Also, it is not designed to be able to do much lowering, so most illegal
  14 // types (e.g. i64 on 32-bit targets) and operations are not supported.  It is
  15 // also not intended to be able to do much optimization, except in a few cases
  16 // where doing optimizations reduces overall compile time.  For example, folding
  17 // constants into immediate fields is often done, because it's cheap and it
  18 // reduces the number of instructions later phases have to examine.
  19 //
  20 // "Fast" instruction selection is able to fail gracefully and transfer
  21 // control to the SelectionDAG selector for operations that it doesn't
  22 // support.  In many cases, this allows us to avoid duplicating a lot of
  23 // the complicated lowering logic that SelectionDAG currently has.
  24 //
  25 // The intended use for "fast" instruction selection is "-O0" mode
  26 // compilation, where the quality of the generated code is irrelevant when
  27 // weighed against the speed at which the code can be generated.  Also,
  28 // at -O0, the LLVM optimizers are not running, and this makes the
  29 // compile time of codegen a much higher portion of the overall compile
  30 // time.  Despite its limitations, "fast" instruction selection is able to
  31 // handle enough code on its own to provide noticeable overall speedups
  32 // in -O0 compiles.
  33 //
  34 // Basic operations are supported in a target-independent way, by reading
  35 // the same instruction descriptions that the SelectionDAG selector reads,
  36 // and identifying simple arithmetic operations that can be directly selected
  37 // from simple operators.  More complicated operations currently require
  38 // target-specific code.
  39 //
  40 //===----------------------------------------------------------------------===//
  41
  42 #include "llvm/Function.h"
  43 #include "llvm/GlobalVariable.h"
  44 #include "llvm/Instructions.h"
  45 #include "llvm/IntrinsicInst.h"
  46 #include "llvm/CodeGen/FastISel.h"
  47 #include "llvm/CodeGen/MachineInstrBuilder.h"
  48 #include "llvm/CodeGen/MachineModuleInfo.h"
  49 #include "llvm/CodeGen/MachineRegisterInfo.h"
  50 #include "llvm/CodeGen/DwarfWriter.h"
  51 #include "llvm/Analysis/DebugInfo.h"
  52 #include "llvm/Target/TargetData.h"
  53 #include "llvm/Target/TargetInstrInfo.h"
  54 #include "llvm/Target/TargetLowering.h"
  55 #include "llvm/Target/TargetMachine.h"
  56 #include "SelectionDAGBuild.h"
  57 using namespace llvm;
  58
  59 unsigned FastISel::getRegForValue(Value *V) {
  60   EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
  61   // Don't handle non-simple values in FastISel.
  62   if (!RealVT.isSimple())
  63     return 0;
  64
  65   // Ignore illegal types. We must do this before looking up the value
  66   // in ValueMap because Arguments are given virtual registers regardless
  67   // of whether FastISel can handle them.
  68   MVT VT = RealVT.getSimpleVT();
  69   if (!TLI.isTypeLegal(VT)) {
  70     // Promote MVT::i1 to a legal type though, because it's common and easy.
  71     if (VT == MVT::i1)
  72       VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
  73     else
  74       return 0;
  75   }
  76
  77   // Look up the value to see if we already have a register for it. We
  78   // cache values defined by Instructions across blocks, and other values
  79   // only locally. This is because Instructions already have the SSA
  80   // def-dominatess-use requirement enforced.
  81   if (ValueMap.count(V))
  82     return ValueMap[V];
  83   unsigned Reg = LocalValueMap[V];
  84   if (Reg != 0)
  85     return Reg;
  86
  87   if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
  88     if (CI->getValue().getActiveBits() <= 64)
  89       Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
  90   } else if (isa<AllocaInst>(V)) {
  91     Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
  92   } else if (isa<ConstantPointerNull>(V)) {
  93     // Translate this as an integer zero so that it can be
  94     // local-CSE'd with actual integer zeros.
  95     Reg =
  96       getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext())));
  97   } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
  98     Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
  99
 100     if (!Reg) {
 101       const APFloat &Flt = CF->getValueAPF();
 102       EVT IntVT = TLI.getPointerTy();
 103
 104       uint64_t x[2];
 105       uint32_t IntBitWidth = IntVT.getSizeInBits();
 106       bool isExact;
 107       (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
 108                                 APFloat::rmTowardZero, &isExact);
 109       if (isExact) {
 110         APInt IntVal(IntBitWidth, 2, x);
 111
 112         unsigned IntegerReg =
 113           getRegForValue(ConstantInt::get(V->getContext(), IntVal));
 114         if (IntegerReg != 0)
 115           Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
 116       }
 117     }
 118   } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
 119     if (!SelectOperator(CE, CE->getOpcode())) return 0;
 120     Reg = LocalValueMap[CE];
 121   } else if (isa<UndefValue>(V)) {
 122     Reg = createResultReg(TLI.getRegClassFor(VT));
 123     BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
 124   }
 125
 126   // If target-independent code couldn't handle the value, give target-specific
 127   // code a try.
 128   if (!Reg && isa<Constant>(V))
 129     Reg = TargetMaterializeConstant(cast<Constant>(V));
 130
 131   // Don't cache constant materializations in the general ValueMap.
 132   // To do so would require tracking what uses they dominate.
 133   if (Reg != 0)
 134     LocalValueMap[V] = Reg;
 135   return Reg;
 136 }
 137
 138 unsigned FastISel::lookUpRegForValue(Value *V) {
 139   // Look up the value to see if we already have a register for it. We
 140   // cache values defined by Instructions across blocks, and other values
 141   // only locally. This is because Instructions already have the SSA
 142   // def-dominatess-use requirement enforced.
 143   if (ValueMap.count(V))
 144     return ValueMap[V];
 145   return LocalValueMap[V];
 146 }
 147
 148 /// UpdateValueMap - Update the value map to include the new mapping for this
 149 /// instruction, or insert an extra copy to get the result in a previous
 150 /// determined register.
 151 /// NOTE: This is only necessary because we might select a block that uses
 152 /// a value before we select the block that defines the value.  It might be
 153 /// possible to fix this by selecting blocks in reverse postorder.
 154 unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) {
 155   if (!isa<Instruction>(I)) {
 156     LocalValueMap[I] = Reg;
 157     return Reg;
 158   }
 159
 160   unsigned &AssignedReg = ValueMap[I];
 161   if (AssignedReg == 0)
 162     AssignedReg = Reg;
 163   else if (Reg != AssignedReg) {
 164     const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
 165     TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
 166                      Reg, RegClass, RegClass);
 167   }
 168   return AssignedReg;
 169 }
 170
 171 unsigned FastISel::getRegForGEPIndex(Value *Idx) {
 172   unsigned IdxN = getRegForValue(Idx);
 173   if (IdxN == 0)
 174     // Unhandled operand. Halt "fast" selection and bail.
 175     return 0;
 176
 177   // If the index is smaller or larger than intptr_t, truncate or extend it.
 178   MVT PtrVT = TLI.getPointerTy();
 179   EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
 180   if (IdxVT.bitsLT(PtrVT))
 181     IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN);
 182   else if (IdxVT.bitsGT(PtrVT))
 183     IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN);
 184   return IdxN;
 185 }
 186
 187 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
 188 /// which has an opcode which directly corresponds to the given ISD opcode.
 189 ///
 190 bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
 191   EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
 192   if (VT == MVT::Other || !VT.isSimple())
 193     // Unhandled type. Halt "fast" selection and bail.
 194     return false;
 195
 196   // We only handle legal types. For example, on x86-32 the instruction
 197   // selector contains all of the 64-bit instructions from x86-64,
 198   // under the assumption that i64 won't be used if the target doesn't
 199   // support it.
 200   if (!TLI.isTypeLegal(VT)) {
 201     // MVT::i1 is special. Allow AND, OR, or XOR because they
 202     // don't require additional zeroing, which makes them easy.
 203     if (VT == MVT::i1 &&
 204         (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
 205          ISDOpcode == ISD::XOR))
 206       VT = TLI.getTypeToTransformTo(I->getContext(), VT);
 207     else
 208       return false;
 209   }
 210
 211   unsigned Op0 = getRegForValue(I->getOperand(0));
 212   if (Op0 == 0)
 213     // Unhandled operand. Halt "fast" selection and bail.
 214     return false;
 215
 216   // Check if the second operand is a constant and handle it appropriately.
 217   if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
 218     unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
 219                                      ISDOpcode, Op0, CI->getZExtValue());
 220     if (ResultReg != 0) {
 221       // We successfully emitted code for the given LLVM Instruction.
 222       UpdateValueMap(I, ResultReg);
 223       return true;
 224     }
 225   }
 226
 227   // Check if the second operand is a constant float.
 228   if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
 229     unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
 230                                      ISDOpcode, Op0, CF);
 231     if (ResultReg != 0) {
 232       // We successfully emitted code for the given LLVM Instruction.
 233       UpdateValueMap(I, ResultReg);
 234       return true;
 235     }
 236   }
 237
 238   unsigned Op1 = getRegForValue(I->getOperand(1));
 239   if (Op1 == 0)
 240     // Unhandled operand. Halt "fast" selection and bail.
 241     return false;
 242
 243   // Now we have both operands in registers. Emit the instruction.
 244   unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
 245                                    ISDOpcode, Op0, Op1);
 246   if (ResultReg == 0)
 247     // Target-specific code wasn't able to find a machine opcode for
 248     // the given ISD opcode and type. Halt "fast" selection and bail.
 249     return false;
 250
 251   // We successfully emitted code for the given LLVM Instruction.
 252   UpdateValueMap(I, ResultReg);
 253   return true;
 254 }
 255
 256 bool FastISel::SelectGetElementPtr(User *I) {
 257   unsigned N = getRegForValue(I->getOperand(0));
 258   if (N == 0)
 259     // Unhandled operand. Halt "fast" selection and bail.
 260     return false;
 261
 262   const Type *Ty = I->getOperand(0)->getType();
 263   MVT VT = TLI.getPointerTy();
 264   for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
 265        OI != E; ++OI) {
 266     Value *Idx = *OI;
 267     if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
 268       unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
 269       if (Field) {
 270         // N = N + Offset
 271         uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
 272         // FIXME: This can be optimized by combining the add with a
 273         // subsequent one.
 274         N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
 275         if (N == 0)
 276           // Unhandled operand. Halt "fast" selection and bail.
 277           return false;
 278       }
 279       Ty = StTy->getElementType(Field);
 280     } else {
 281       Ty = cast<SequentialType>(Ty)->getElementType();
 282
 283       // If this is a constant subscript, handle it quickly.
 284       if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
 285         if (CI->getZExtValue() == 0) continue;
 286         uint64_t Offs =
 287           TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
 288         N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
 289         if (N == 0)
 290           // Unhandled operand. Halt "fast" selection and bail.
 291           return false;
 292         continue;
 293       }
 294
 295       // N = N + Idx * ElementSize;
 296       uint64_t ElementSize = TD.getTypeAllocSize(Ty);
 297       unsigned IdxN = getRegForGEPIndex(Idx);
 298       if (IdxN == 0)
 299         // Unhandled operand. Halt "fast" selection and bail.
 300         return false;
 301
 302       if (ElementSize != 1) {
 303         IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
 304         if (IdxN == 0)
 305           // Unhandled operand. Halt "fast" selection and bail.
 306           return false;
 307       }
 308       N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
 309       if (N == 0)
 310         // Unhandled operand. Halt "fast" selection and bail.
 311         return false;
 312     }
 313   }
 314
 315   // We successfully emitted code for the given LLVM Instruction.
 316   UpdateValueMap(I, N);
 317   return true;
 318 }
 319
 320 bool FastISel::SelectCall(User *I) {
 321   Function *F = cast<CallInst>(I)->getCalledFunction();
 322   if (!F) return false;
 323
 324   unsigned IID = F->getIntrinsicID();
 325   switch (IID) {
 326   default: break;
 327   case Intrinsic::dbg_stoppoint: {
 328     DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
 329     if (isValidDebugInfoIntrinsic(*SPI, CodeGenOpt::None))
 330       setCurDebugLoc(ExtractDebugLocation(*SPI, MF.getDebugLocInfo()));
 331     return true;
 332   }
 333   case Intrinsic::dbg_region_start: {
 334     DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
 335     if (isValidDebugInfoIntrinsic(*RSI, CodeGenOpt::None) && DW
 336         && DW->ShouldEmitDwarfDebug()) {
 337       unsigned ID =
 338         DW->RecordRegionStart(RSI->getContext());
 339       const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
 340       BuildMI(MBB, DL, II).addImm(ID);
 341     }
 342     return true;
 343   }
 344   case Intrinsic::dbg_region_end: {
 345     DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
 346     if (isValidDebugInfoIntrinsic(*REI, CodeGenOpt::None) && DW
 347         && DW->ShouldEmitDwarfDebug()) {
 348      unsigned ID = 0;
 349      DISubprogram Subprogram(REI->getContext());
 350      if (isInlinedFnEnd(*REI, MF.getFunction())) {
 351         // This is end of an inlined function.
 352         const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
 353         ID = DW->RecordInlinedFnEnd(Subprogram);
 354         if (ID)
 355           // Returned ID is 0 if this is unbalanced "end of inlined
 356           // scope". This could happen if optimizer eats dbg intrinsics
 357           // or "beginning of inlined scope" is not recoginized due to
 358           // missing location info. In such cases, ignore this region.end.
 359           BuildMI(MBB, DL, II).addImm(ID);
 360       } else {
 361         const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
 362         ID =  DW->RecordRegionEnd(REI->getContext());
 363         BuildMI(MBB, DL, II).addImm(ID);
 364       }
 365     }
 366     return true;
 367   }
 368   case Intrinsic::dbg_func_start: {
 369     DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
 370     if (!isValidDebugInfoIntrinsic(*FSI, CodeGenOpt::None) || !DW
 371         || !DW->ShouldEmitDwarfDebug())
 372       return true;
 373
 374     if (isInlinedFnStart(*FSI, MF.getFunction())) {
 375       // This is a beginning of an inlined function.
 376
 377       // If llvm.dbg.func.start is seen in a new block before any
 378       // llvm.dbg.stoppoint intrinsic then the location info is unknown.
 379       // FIXME : Why DebugLoc is reset at the beginning of each block ?
 380       DebugLoc PrevLoc = DL;
 381       if (PrevLoc.isUnknown())
 382         return true;
 383       // Record the source line.
 384       setCurDebugLoc(ExtractDebugLocation(*FSI, MF.getDebugLocInfo()));
 385
 386       DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc);
 387       DISubprogram SP(FSI->getSubprogram());
 388       unsigned LabelID = DW->RecordInlinedFnStart(SP,
 389                                                   DICompileUnit(PrevLocTpl.CompileUnit),
 390                                                   PrevLocTpl.Line,
 391                                                   PrevLocTpl.Col);
 392       const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
 393       BuildMI(MBB, DL, II).addImm(LabelID);
 394       return true;
 395     }
 396
 397     // This is a beginning of a new function.
 398     MF.setDefaultDebugLoc(ExtractDebugLocation(*FSI, MF.getDebugLocInfo()));
 399
 400     // llvm.dbg.func_start also defines beginning of function scope.
 401     DW->RecordRegionStart(FSI->getSubprogram());
 402     return true;
 403   }
 404   case Intrinsic::dbg_declare: {
 405     DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
 406     if (!isValidDebugInfoIntrinsic(*DI, CodeGenOpt::None) || !DW
 407         || !DW->ShouldEmitDwarfDebug())
 408       return true;
 409
 410     Value *Variable = DI->getVariable();
 411     Value *Address = DI->getAddress();
 412     if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
 413       Address = BCI->getOperand(0);
 414     AllocaInst *AI = dyn_cast<AllocaInst>(Address);
 415     // Don't handle byval struct arguments or VLAs, for example.
 416     if (!AI) break;
 417     DenseMap<const AllocaInst*, int>::iterator SI =
 418       StaticAllocaMap.find(AI);
 419     if (SI == StaticAllocaMap.end()) break; // VLAs.
 420     int FI = SI->second;
 421
 422     DW->RecordVariable(cast<MDNode>(Variable), FI);
 423     return true;
 424   }
 425   case Intrinsic::eh_exception: {
 426     EVT VT = TLI.getValueType(I->getType());
 427     switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
 428     default: break;
 429     case TargetLowering::Expand: {
 430       assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!");
 431       unsigned Reg = TLI.getExceptionAddressRegister();
 432       const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
 433       unsigned ResultReg = createResultReg(RC);
 434       bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
 435                                            Reg, RC, RC);
 436       assert(InsertedCopy && "Can't copy address registers!");
 437       InsertedCopy = InsertedCopy;
 438       UpdateValueMap(I, ResultReg);
 439       return true;
 440     }
 441     }
 442     break;
 443   }
 444   case Intrinsic::eh_selector_i32:
 445   case Intrinsic::eh_selector_i64: {
 446     EVT VT = TLI.getValueType(I->getType());
 447     switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
 448     default: break;
 449     case TargetLowering::Expand: {
 450       EVT VT = (IID == Intrinsic::eh_selector_i32 ?
 451                            MVT::i32 : MVT::i64);
 452
 453       if (MMI) {
 454         if (MBB->isLandingPad())
 455           AddCatchInfo(*cast<CallInst>(I), MMI, MBB);
 456         else {
 457 #ifndef NDEBUG
 458           CatchInfoLost.insert(cast<CallInst>(I));
 459 #endif
 460           // FIXME: Mark exception selector register as live in.  Hack for PR1508.
 461           unsigned Reg = TLI.getExceptionSelectorRegister();
 462           if (Reg) MBB->addLiveIn(Reg);
 463         }
 464
 465         unsigned Reg = TLI.getExceptionSelectorRegister();
 466         const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
 467         unsigned ResultReg = createResultReg(RC);
 468         bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
 469                                              Reg, RC, RC);
 470         assert(InsertedCopy && "Can't copy address registers!");
 471         InsertedCopy = InsertedCopy;
 472         UpdateValueMap(I, ResultReg);
 473       } else {
 474         unsigned ResultReg =
 475           getRegForValue(Constant::getNullValue(I->getType()));
 476         UpdateValueMap(I, ResultReg);
 477       }
 478       return true;
 479     }
 480     }
 481     break;
 482   }
 483   }
 484   return false;
 485 }
 486
 487 bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
 488   EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
 489   EVT DstVT = TLI.getValueType(I->getType());
 490
 491   if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
 492       DstVT == MVT::Other || !DstVT.isSimple())
 493     // Unhandled type. Halt "fast" selection and bail.
 494     return false;
 495
 496   // Check if the destination type is legal. Or as a special case,
 497   // it may be i1 if we're doing a truncate because that's
 498   // easy and somewhat common.
 499   if (!TLI.isTypeLegal(DstVT))
 500     if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
 501       // Unhandled type. Halt "fast" selection and bail.
 502       return false;
 503
 504   // Check if the source operand is legal. Or as a special case,
 505   // it may be i1 if we're doing zero-extension because that's
 506   // easy and somewhat common.
 507   if (!TLI.isTypeLegal(SrcVT))
 508     if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
 509       // Unhandled type. Halt "fast" selection and bail.
 510       return false;
 511
 512   unsigned InputReg = getRegForValue(I->getOperand(0));
 513   if (!InputReg)
 514     // Unhandled operand.  Halt "fast" selection and bail.
 515     return false;
 516
 517   // If the operand is i1, arrange for the high bits in the register to be zero.
 518   if (SrcVT == MVT::i1) {
 519    SrcVT = TLI.getTypeToTransformTo(I->getContext(), SrcVT);
 520    InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
 521    if (!InputReg)
 522      return false;
 523   }
 524   // If the result is i1, truncate to the target's type for i1 first.
 525   if (DstVT == MVT::i1)
 526     DstVT = TLI.getTypeToTransformTo(I->getContext(), DstVT);
 527
 528   unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
 529                                   DstVT.getSimpleVT(),
 530                                   Opcode,
 531                                   InputReg);
 532   if (!ResultReg)
 533     return false;
 534
 535   UpdateValueMap(I, ResultReg);
 536   return true;
 537 }
 538
 539 bool FastISel::SelectBitCast(User *I) {
 540   // If the bitcast doesn't change the type, just use the operand value.
 541   if (I->getType() == I->getOperand(0)->getType()) {
 542     unsigned Reg = getRegForValue(I->getOperand(0));
 543     if (Reg == 0)
 544       return false;
 545     UpdateValueMap(I, Reg);
 546     return true;
 547   }
 548
 549   // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
 550   EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
 551   EVT DstVT = TLI.getValueType(I->getType());
 552
 553   if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
 554       DstVT == MVT::Other || !DstVT.isSimple() ||
 555       !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
 556     // Unhandled type. Halt "fast" selection and bail.
 557     return false;
 558
 559   unsigned Op0 = getRegForValue(I->getOperand(0));
 560   if (Op0 == 0)
 561     // Unhandled operand. Halt "fast" selection and bail.
 562     return false;
 563
 564   // First, try to perform the bitcast by inserting a reg-reg copy.
 565   unsigned ResultReg = 0;
 566   if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
 567     TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
 568     TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
 569     ResultReg = createResultReg(DstClass);
 570
 571     bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
 572                                          Op0, DstClass, SrcClass);
 573     if (!InsertedCopy)
 574       ResultReg = 0;
 575   }
 576
 577   // If the reg-reg copy failed, select a BIT_CONVERT opcode.
 578   if (!ResultReg)
 579     ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
 580                            ISD::BIT_CONVERT, Op0);
 581
 582   if (!ResultReg)
 583     return false;
 584
 585   UpdateValueMap(I, ResultReg);
 586   return true;
 587 }
 588
 589 bool
 590 FastISel::SelectInstruction(Instruction *I) {
 591   return SelectOperator(I, I->getOpcode());
 592 }
 593
 594 /// FastEmitBranch - Emit an unconditional branch to the given block,
 595 /// unless it is the immediate (fall-through) successor, and update
 596 /// the CFG.
 597 void
 598 FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
 599   MachineFunction::iterator NextMBB =
 600      next(MachineFunction::iterator(MBB));
 601
 602   if (MBB->isLayoutSuccessor(MSucc)) {
 603     // The unconditional fall-through case, which needs no instructions.
 604   } else {
 605     // The unconditional branch case.
 606     TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
 607   }
 608   MBB->addSuccessor(MSucc);
 609 }
 610
 611 /// SelectFNeg - Emit an FNeg operation.
 612 ///
 613 bool
 614 FastISel::SelectFNeg(User *I) {
 615   unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
 616   if (OpReg == 0) return false;
 617
 618   // If the target has ISD::FNEG, use it.
 619   EVT VT = TLI.getValueType(I->getType());
 620   unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(),
 621                                   ISD::FNEG, OpReg);
 622   if (ResultReg != 0) {
 623     UpdateValueMap(I, ResultReg);
 624     return true;
 625   }
 626
 627   // Bitcast the value to integer, twiddle the sign bit with xor,
 628   // and then bitcast it back to floating-point.
 629   if (VT.getSizeInBits() > 64) return false;
 630   EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
 631   if (!TLI.isTypeLegal(IntVT))
 632     return false;
 633
 634   unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
 635                                ISD::BIT_CONVERT, OpReg);
 636   if (IntReg == 0)
 637     return false;
 638
 639   unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, IntReg,
 640                                        UINT64_C(1) << (VT.getSizeInBits()-1),
 641                                        IntVT.getSimpleVT());
 642   if (IntResultReg == 0)
 643     return false;
 644
 645   ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(),
 646                          ISD::BIT_CONVERT, IntResultReg);
 647   if (ResultReg == 0)
 648     return false;
 649
 650   UpdateValueMap(I, ResultReg);
 651   return true;
 652 }
 653
 654 bool
 655 FastISel::SelectOperator(User *I, unsigned Opcode) {
 656   switch (Opcode) {
 657   case Instruction::Add:
 658     return SelectBinaryOp(I, ISD::ADD);
 659   case Instruction::FAdd:
 660     return SelectBinaryOp(I, ISD::FADD);
 661   case Instruction::Sub:
 662     return SelectBinaryOp(I, ISD::SUB);
 663   case Instruction::FSub:
 664     // FNeg is currently represented in LLVM IR as a special case of FSub.
 665     if (BinaryOperator::isFNeg(I))
 666       return SelectFNeg(I);
 667     return SelectBinaryOp(I, ISD::FSUB);
 668   case Instruction::Mul:
 669     return SelectBinaryOp(I, ISD::MUL);
 670   case Instruction::FMul:
 671     return SelectBinaryOp(I, ISD::FMUL);
 672   case Instruction::SDiv:
 673     return SelectBinaryOp(I, ISD::SDIV);
 674   case Instruction::UDiv:
 675     return SelectBinaryOp(I, ISD::UDIV);
 676   case Instruction::FDiv:
 677     return SelectBinaryOp(I, ISD::FDIV);
 678   case Instruction::SRem:
 679     return SelectBinaryOp(I, ISD::SREM);
 680   case Instruction::URem:
 681     return SelectBinaryOp(I, ISD::UREM);
 682   case Instruction::FRem:
 683     return SelectBinaryOp(I, ISD::FREM);
 684   case Instruction::Shl:
 685     return SelectBinaryOp(I, ISD::SHL);
 686   case Instruction::LShr:
 687     return SelectBinaryOp(I, ISD::SRL);
 688   case Instruction::AShr:
 689     return SelectBinaryOp(I, ISD::SRA);
 690   case Instruction::And:
 691     return SelectBinaryOp(I, ISD::AND);
 692   case Instruction::Or:
 693     return SelectBinaryOp(I, ISD::OR);
 694   case Instruction::Xor:
 695     return SelectBinaryOp(I, ISD::XOR);
 696
 697   case Instruction::GetElementPtr:
 698     return SelectGetElementPtr(I);
 699
 700   case Instruction::Br: {
 701     BranchInst *BI = cast<BranchInst>(I);
 702
 703     if (BI->isUnconditional()) {
 704       BasicBlock *LLVMSucc = BI->getSuccessor(0);
 705       MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
 706       FastEmitBranch(MSucc);
 707       return true;
 708     }
 709
 710     // Conditional branches are not handed yet.
 711     // Halt "fast" selection and bail.
 712     return false;
 713   }
 714
 715   case Instruction::Unreachable:
 716     // Nothing to emit.
 717     return true;
 718
 719   case Instruction::PHI:
 720     // PHI nodes are already emitted.
 721     return true;
 722
 723   case Instruction::Alloca:
 724     // FunctionLowering has the static-sized case covered.
 725     if (StaticAllocaMap.count(cast<AllocaInst>(I)))
 726       return true;
 727
 728     // Dynamic-sized alloca is not handled yet.
 729     return false;
 730
 731   case Instruction::Call:
 732     return SelectCall(I);
 733
 734   case Instruction::BitCast:
 735     return SelectBitCast(I);
 736
 737   case Instruction::FPToSI:
 738     return SelectCast(I, ISD::FP_TO_SINT);
 739   case Instruction::ZExt:
 740     return SelectCast(I, ISD::ZERO_EXTEND);
 741   case Instruction::SExt:
 742     return SelectCast(I, ISD::SIGN_EXTEND);
 743   case Instruction::Trunc:
 744     return SelectCast(I, ISD::TRUNCATE);
 745   case Instruction::SIToFP:
 746     return SelectCast(I, ISD::SINT_TO_FP);
 747
 748   case Instruction::IntToPtr: // Deliberate fall-through.
 749   case Instruction::PtrToInt: {
 750     EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
 751     EVT DstVT = TLI.getValueType(I->getType());
 752     if (DstVT.bitsGT(SrcVT))
 753       return SelectCast(I, ISD::ZERO_EXTEND);
 754     if (DstVT.bitsLT(SrcVT))
 755       return SelectCast(I, ISD::TRUNCATE);
 756     unsigned Reg = getRegForValue(I->getOperand(0));
 757     if (Reg == 0) return false;
 758     UpdateValueMap(I, Reg);
 759     return true;
 760   }
 761
 762   default:
 763     // Unhandled instruction. Halt "fast" selection and bail.
 764     return false;
 765   }
 766 }
 767
 768 FastISel::FastISel(MachineFunction &mf,
 769                    MachineModuleInfo *mmi,
 770                    DwarfWriter *dw,
 771                    DenseMap<const Value *, unsigned> &vm,
 772                    DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
 773                    DenseMap<const AllocaInst *, int> &am
 774 #ifndef NDEBUG
 775                    , SmallSet<Instruction*, 8> &cil
 776 #endif
 777                    )
 778   : MBB(0),
 779     ValueMap(vm),
 780     MBBMap(bm),
 781     StaticAllocaMap(am),
 782 #ifndef NDEBUG
 783     CatchInfoLost(cil),
 784 #endif
 785     MF(mf),
 786     MMI(mmi),
 787     DW(dw),
 788     MRI(MF.getRegInfo()),
 789     MFI(*MF.getFrameInfo()),
 790     MCP(*MF.getConstantPool()),
 791     TM(MF.getTarget()),
 792     TD(*TM.getTargetData()),
 793     TII(*TM.getInstrInfo()),
 794     TLI(*TM.getTargetLowering()) {
 795 }
 796
 797 FastISel::~FastISel() {}
 798
 799 unsigned FastISel::FastEmit_(MVT, MVT,
 800                              ISD::NodeType) {
 801   return 0;
 802 }
 803
 804 unsigned FastISel::FastEmit_r(MVT, MVT,
 805                               ISD::NodeType, unsigned /*Op0*/) {
 806   return 0;
 807 }
 808
 809 unsigned FastISel::FastEmit_rr(MVT, MVT,
 810                                ISD::NodeType, unsigned /*Op0*/,
 811                                unsigned /*Op0*/) {
 812   return 0;
 813 }
 814
 815 unsigned FastISel::FastEmit_i(MVT, MVT, ISD::NodeType, uint64_t /*Imm*/) {
 816   return 0;
 817 }
 818
 819 unsigned FastISel::FastEmit_f(MVT, MVT,
 820                               ISD::NodeType, ConstantFP * /*FPImm*/) {
 821   return 0;
 822 }
 823
 824 unsigned FastISel::FastEmit_ri(MVT, MVT,
 825                                ISD::NodeType, unsigned /*Op0*/,
 826                                uint64_t /*Imm*/) {
 827   return 0;
 828 }
 829
 830 unsigned FastISel::FastEmit_rf(MVT, MVT,
 831                                ISD::NodeType, unsigned /*Op0*/,
 832                                ConstantFP * /*FPImm*/) {
 833   return 0;
 834 }
 835
 836 unsigned FastISel::FastEmit_rri(MVT, MVT,
 837                                 ISD::NodeType,
 838                                 unsigned /*Op0*/, unsigned /*Op1*/,
 839                                 uint64_t /*Imm*/) {
 840   return 0;
 841 }
 842
 843 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
 844 /// to emit an instruction with an immediate operand using FastEmit_ri.
 845 /// If that fails, it materializes the immediate into a register and try
 846 /// FastEmit_rr instead.
 847 unsigned FastISel::FastEmit_ri_(MVT VT, ISD::NodeType Opcode,
 848                                 unsigned Op0, uint64_t Imm,
 849                                 MVT ImmType) {
 850   // First check if immediate type is legal. If not, we can't use the ri form.
 851   unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
 852   if (ResultReg != 0)
 853     return ResultReg;
 854   unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
 855   if (MaterialReg == 0)
 856     return 0;
 857   return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
 858 }
 859
 860 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
 861 /// to emit an instruction with a floating-point immediate operand using
 862 /// FastEmit_rf. If that fails, it materializes the immediate into a register
 863 /// and try FastEmit_rr instead.
 864 unsigned FastISel::FastEmit_rf_(MVT VT, ISD::NodeType Opcode,
 865                                 unsigned Op0, ConstantFP *FPImm,
 866                                 MVT ImmType) {
 867   // First check if immediate type is legal. If not, we can't use the rf form.
 868   unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
 869   if (ResultReg != 0)
 870     return ResultReg;
 871
 872   // Materialize the constant in a register.
 873   unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
 874   if (MaterialReg == 0) {
 875     // If the target doesn't have a way to directly enter a floating-point
 876     // value into a register, use an alternate approach.
 877     // TODO: The current approach only supports floating-point constants
 878     // that can be constructed by conversion from integer values. This should
 879     // be replaced by code that creates a load from a constant-pool entry,
 880     // which will require some target-specific work.
 881     const APFloat &Flt = FPImm->getValueAPF();
 882     EVT IntVT = TLI.getPointerTy();
 883
 884     uint64_t x[2];
 885     uint32_t IntBitWidth = IntVT.getSizeInBits();
 886     bool isExact;
 887     (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
 888                              APFloat::rmTowardZero, &isExact);
 889     if (!isExact)
 890       return 0;
 891     APInt IntVal(IntBitWidth, 2, x);
 892
 893     unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
 894                                      ISD::Constant, IntVal.getZExtValue());
 895     if (IntegerReg == 0)
 896       return 0;
 897     MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
 898                              ISD::SINT_TO_FP, IntegerReg);
 899     if (MaterialReg == 0)
 900       return 0;
 901   }
 902   return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
 903 }
 904
 905 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
 906   return MRI.createVirtualRegister(RC);
 907 }
 908
 909 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
 910                                  const TargetRegisterClass* RC) {
 911   unsigned ResultReg = createResultReg(RC);
 912   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 913
 914   BuildMI(MBB, DL, II, ResultReg);
 915   return ResultReg;
 916 }
 917
 918 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
 919                                   const TargetRegisterClass *RC,
 920                                   unsigned Op0) {
 921   unsigned ResultReg = createResultReg(RC);
 922   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 923
 924   if (II.getNumDefs() >= 1)
 925     BuildMI(MBB, DL, II, ResultReg).addReg(Op0);
 926   else {
 927     BuildMI(MBB, DL, II).addReg(Op0);
 928     bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
 929                                          II.ImplicitDefs[0], RC, RC);
 930     if (!InsertedCopy)
 931       ResultReg = 0;
 932   }
 933
 934   return ResultReg;
 935 }
 936
 937 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
 938                                    const TargetRegisterClass *RC,
 939                                    unsigned Op0, unsigned Op1) {
 940   unsigned ResultReg = createResultReg(RC);
 941   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 942
 943   if (II.getNumDefs() >= 1)
 944     BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1);
 945   else {
 946     BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1);
 947     bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
 948                                          II.ImplicitDefs[0], RC, RC);
 949     if (!InsertedCopy)
 950       ResultReg = 0;
 951   }
 952   return ResultReg;
 953 }
 954
 955 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
 956                                    const TargetRegisterClass *RC,
 957                                    unsigned Op0, uint64_t Imm) {
 958   unsigned ResultReg = createResultReg(RC);
 959   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 960
 961   if (II.getNumDefs() >= 1)
 962     BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm);
 963   else {
 964     BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm);
 965     bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
 966                                          II.ImplicitDefs[0], RC, RC);
 967     if (!InsertedCopy)
 968       ResultReg = 0;
 969   }
 970   return ResultReg;
 971 }
 972
 973 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
 974                                    const TargetRegisterClass *RC,
 975                                    unsigned Op0, ConstantFP *FPImm) {
 976   unsigned ResultReg = createResultReg(RC);
 977   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 978
 979   if (II.getNumDefs() >= 1)
 980     BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm);
 981   else {
 982     BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm);
 983     bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
 984                                          II.ImplicitDefs[0], RC, RC);
 985     if (!InsertedCopy)
 986       ResultReg = 0;
 987   }
 988   return ResultReg;
 989 }
 990
 991 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
 992                                     const TargetRegisterClass *RC,
 993                                     unsigned Op0, unsigned Op1, uint64_t Imm) {
 994   unsigned ResultReg = createResultReg(RC);
 995   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 996
 997   if (II.getNumDefs() >= 1)
 998     BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
 999   else {
1000     BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm);
1001     bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1002                                          II.ImplicitDefs[0], RC, RC);
1003     if (!InsertedCopy)
1004       ResultReg = 0;
1005   }
1006   return ResultReg;
1007 }
1008
1009 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
1010                                   const TargetRegisterClass *RC,
1011                                   uint64_t Imm) {
1012   unsigned ResultReg = createResultReg(RC);
1013   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1014
1015   if (II.getNumDefs() >= 1)
1016     BuildMI(MBB, DL, II, ResultReg).addImm(Imm);
1017   else {
1018     BuildMI(MBB, DL, II).addImm(Imm);
1019     bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1020                                          II.ImplicitDefs[0], RC, RC);
1021     if (!InsertedCopy)
1022       ResultReg = 0;
1023   }
1024   return ResultReg;
1025 }
1026
1027 unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT,
1028                                               unsigned Op0, uint32_t Idx) {
1029   const TargetRegisterClass* RC = MRI.getRegClass(Op0);
1030
1031   unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1032   const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
1033
1034   if (II.getNumDefs() >= 1)
1035     BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx);
1036   else {
1037     BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx);
1038     bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1039                                          II.ImplicitDefs[0], RC, RC);
1040     if (!InsertedCopy)
1041       ResultReg = 0;
1042   }
1043   return ResultReg;
1044 }
1045
1046 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
1047 /// with all but the least significant bit set to zero.
1048 unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op) {
1049   return FastEmit_ri(VT, VT, ISD::AND, Op, 1);
1050 }