lib/Target/X86/X86ISelDAGToDAG.cpp

   1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines a DAG pattern matching instruction selector for X86,
  11 // converting from a legalized dag to a X86 dag.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #define DEBUG_TYPE "x86-isel"
  16 #include "X86.h"
  17 #include "X86InstrBuilder.h"
  18 #include "X86ISelLowering.h"
  19 #include "X86MachineFunctionInfo.h"
  20 #include "X86RegisterInfo.h"
  21 #include "X86Subtarget.h"
  22 #include "X86TargetMachine.h"
  23 #include "llvm/GlobalValue.h"
  24 #include "llvm/Instructions.h"
  25 #include "llvm/Intrinsics.h"
  26 #include "llvm/Support/CFG.h"
  27 #include "llvm/Type.h"
  28 #include "llvm/CodeGen/MachineConstantPool.h"
  29 #include "llvm/CodeGen/MachineFunction.h"
  30 #include "llvm/CodeGen/MachineFrameInfo.h"
  31 #include "llvm/CodeGen/MachineInstrBuilder.h"
  32 #include "llvm/CodeGen/MachineRegisterInfo.h"
  33 #include "llvm/CodeGen/SelectionDAGISel.h"
  34 #include "llvm/Target/TargetMachine.h"
  35 #include "llvm/Target/TargetOptions.h"
  36 #include "llvm/Support/Compiler.h"
  37 #include "llvm/Support/Debug.h"
  38 #include "llvm/Support/ErrorHandling.h"
  39 #include "llvm/Support/MathExtras.h"
  40 #include "llvm/Support/Streams.h"
  41 #include "llvm/Support/raw_ostream.h"
  42 #include "llvm/ADT/SmallPtrSet.h"
  43 #include "llvm/ADT/Statistic.h"
  44 using namespace llvm;
  45
  46 #include "llvm/Support/CommandLine.h"
  47 static cl::opt<bool> AvoidDupAddrCompute("x86-avoid-dup-address", cl::Hidden);
  48
  49 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
  50
  51 //===----------------------------------------------------------------------===//
  52 //                      Pattern Matcher Implementation
  53 //===----------------------------------------------------------------------===//
  54
  55 namespace {
  56   /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
  57   /// SDValue's instead of register numbers for the leaves of the matched
  58   /// tree.
  59   struct X86ISelAddressMode {
  60     enum {
  61       RegBase,
  62       FrameIndexBase
  63     } BaseType;
  64
  65     struct {            // This is really a union, discriminated by BaseType!
  66       SDValue Reg;
  67       int FrameIndex;
  68     } Base;
  69
  70     unsigned Scale;
  71     SDValue IndexReg;
  72     int32_t Disp;
  73     SDValue Segment;
  74     GlobalValue *GV;
  75     Constant *CP;
  76     const char *ES;
  77     int JT;
  78     unsigned Align;    // CP alignment.
  79     unsigned char SymbolFlags;  // X86II::MO_*
  80
  81     X86ISelAddressMode()
  82       : BaseType(RegBase), Scale(1), IndexReg(), Disp(0),
  83         Segment(), GV(0), CP(0), ES(0), JT(-1), Align(0), SymbolFlags(0) {
  84     }
  85
  86     bool hasSymbolicDisplacement() const {
  87       return GV != 0 || CP != 0 || ES != 0 || JT != -1;
  88     }
  89
  90     bool hasBaseOrIndexReg() const {
  91       return IndexReg.getNode() != 0 || Base.Reg.getNode() != 0;
  92     }
  93
  94     /// isRIPRelative - Return true if this addressing mode is already RIP
  95     /// relative.
  96     bool isRIPRelative() const {
  97       if (BaseType != RegBase) return false;
  98       if (RegisterSDNode *RegNode =
  99             dyn_cast_or_null<RegisterSDNode>(Base.Reg.getNode()))
 100         return RegNode->getReg() == X86::RIP;
 101       return false;
 102     }
 103
 104     void setBaseReg(SDValue Reg) {
 105       BaseType = RegBase;
 106       Base.Reg = Reg;
 107     }
 108
 109     void dump() {
 110       cerr << "X86ISelAddressMode " << this << '\n';
 111       cerr << "Base.Reg ";
 112       if (Base.Reg.getNode() != 0)
 113         Base.Reg.getNode()->dump();
 114       else
 115         cerr << "nul";
 116       cerr << " Base.FrameIndex " << Base.FrameIndex << '\n';
 117       cerr << " Scale" << Scale << '\n';
 118       cerr << "IndexReg ";
 119       if (IndexReg.getNode() != 0)
 120         IndexReg.getNode()->dump();
 121       else
 122         cerr << "nul";
 123       cerr << " Disp " << Disp << '\n';
 124       cerr << "GV ";
 125       if (GV)
 126         GV->dump();
 127       else
 128         cerr << "nul";
 129       cerr << " CP ";
 130       if (CP)
 131         CP->dump();
 132       else
 133         cerr << "nul";
 134       cerr << '\n';
 135       cerr << "ES ";
 136       if (ES)
 137         cerr << ES;
 138       else
 139         cerr << "nul";
 140       cerr << " JT" << JT << " Align" << Align << '\n';
 141     }
 142   };
 143 }
 144
 145 namespace {
 146   //===--------------------------------------------------------------------===//
 147   /// ISel - X86 specific code to select X86 machine instructions for
 148   /// SelectionDAG operations.
 149   ///
 150   class VISIBILITY_HIDDEN X86DAGToDAGISel : public SelectionDAGISel {
 151     /// X86Lowering - This object fully describes how to lower LLVM code to an
 152     /// X86-specific SelectionDAG.
 153     X86TargetLowering &X86Lowering;
 154
 155     /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
 156     /// make the right decision when generating code for different targets.
 157     const X86Subtarget *Subtarget;
 158
 159     /// OptForSize - If true, selector should try to optimize for code size
 160     /// instead of performance.
 161     bool OptForSize;
 162
 163   public:
 164     explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
 165       : SelectionDAGISel(tm, OptLevel),
 166         X86Lowering(*tm.getTargetLowering()),
 167         Subtarget(&tm.getSubtarget<X86Subtarget>()),
 168         OptForSize(false) {}
 169
 170     virtual const char *getPassName() const {
 171       return "X86 DAG->DAG Instruction Selection";
 172     }
 173
 174     /// InstructionSelect - This callback is invoked by
 175     /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
 176     virtual void InstructionSelect();
 177
 178     virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
 179
 180     virtual
 181       bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const;
 182
 183 // Include the pieces autogenerated from the target description.
 184 #include "X86GenDAGISel.inc"
 185
 186   private:
 187     SDNode *Select(SDValue N);
 188     SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
 189     SDNode *SelectAtomicLoadAdd(SDNode *Node, EVT NVT);
 190
 191     bool MatchSegmentBaseAddress(SDValue N, X86ISelAddressMode &AM);
 192     bool MatchLoad(SDValue N, X86ISelAddressMode &AM);
 193     bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
 194     bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
 195     bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
 196                                  unsigned Depth);
 197     bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
 198     bool SelectAddr(SDValue Op, SDValue N, SDValue &Base,
 199                     SDValue &Scale, SDValue &Index, SDValue &Disp,
 200                     SDValue &Segment);
 201     bool SelectLEAAddr(SDValue Op, SDValue N, SDValue &Base,
 202                        SDValue &Scale, SDValue &Index, SDValue &Disp);
 203     bool SelectTLSADDRAddr(SDValue Op, SDValue N, SDValue &Base,
 204                        SDValue &Scale, SDValue &Index, SDValue &Disp);
 205     bool SelectScalarSSELoad(SDValue Op, SDValue Pred,
 206                              SDValue N, SDValue &Base, SDValue &Scale,
 207                              SDValue &Index, SDValue &Disp,
 208                              SDValue &Segment,
 209                              SDValue &InChain, SDValue &OutChain);
 210     bool TryFoldLoad(SDValue P, SDValue N,
 211                      SDValue &Base, SDValue &Scale,
 212                      SDValue &Index, SDValue &Disp,
 213                      SDValue &Segment);
 214     void PreprocessForRMW();
 215     void PreprocessForFPConvert();
 216
 217     /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
 218     /// inline asm expressions.
 219     virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
 220                                               char ConstraintCode,
 221                                               std::vector<SDValue> &OutOps);
 222
 223     void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
 224
 225     inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
 226                                    SDValue &Scale, SDValue &Index,
 227                                    SDValue &Disp, SDValue &Segment) {
 228       Base  = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
 229         CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) :
 230         AM.Base.Reg;
 231       Scale = getI8Imm(AM.Scale);
 232       Index = AM.IndexReg;
 233       // These are 32-bit even in 64-bit mode since RIP relative offset
 234       // is 32-bit.
 235       if (AM.GV)
 236         Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp,
 237                                               AM.SymbolFlags);
 238       else if (AM.CP)
 239         Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
 240                                              AM.Align, AM.Disp, AM.SymbolFlags);
 241       else if (AM.ES)
 242         Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
 243       else if (AM.JT != -1)
 244         Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
 245       else
 246         Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
 247
 248       if (AM.Segment.getNode())
 249         Segment = AM.Segment;
 250       else
 251         Segment = CurDAG->getRegister(0, MVT::i32);
 252     }
 253
 254     /// getI8Imm - Return a target constant with the specified value, of type
 255     /// i8.
 256     inline SDValue getI8Imm(unsigned Imm) {
 257       return CurDAG->getTargetConstant(Imm, MVT::i8);
 258     }
 259
 260     /// getI16Imm - Return a target constant with the specified value, of type
 261     /// i16.
 262     inline SDValue getI16Imm(unsigned Imm) {
 263       return CurDAG->getTargetConstant(Imm, MVT::i16);
 264     }
 265
 266     /// getI32Imm - Return a target constant with the specified value, of type
 267     /// i32.
 268     inline SDValue getI32Imm(unsigned Imm) {
 269       return CurDAG->getTargetConstant(Imm, MVT::i32);
 270     }
 271
 272     /// getGlobalBaseReg - Return an SDNode that returns the value of
 273     /// the global base register. Output instructions required to
 274     /// initialize the global base register, if necessary.
 275     ///
 276     SDNode *getGlobalBaseReg();
 277
 278     /// getTargetMachine - Return a reference to the TargetMachine, casted
 279     /// to the target-specific type.
 280     const X86TargetMachine &getTargetMachine() {
 281       return static_cast<const X86TargetMachine &>(TM);
 282     }
 283
 284     /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
 285     /// to the target-specific type.
 286     const X86InstrInfo *getInstrInfo() {
 287       return getTargetMachine().getInstrInfo();
 288     }
 289
 290 #ifndef NDEBUG
 291     unsigned Indent;
 292 #endif
 293   };
 294 }
 295
 296
 297 bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
 298                                                  SDNode *Root) const {
 299   if (OptLevel == CodeGenOpt::None) return false;
 300
 301   if (U == Root)
 302     switch (U->getOpcode()) {
 303     default: break;
 304     case ISD::ADD:
 305     case ISD::ADDC:
 306     case ISD::ADDE:
 307     case ISD::AND:
 308     case ISD::OR:
 309     case ISD::XOR: {
 310       SDValue Op1 = U->getOperand(1);
 311
 312       // If the other operand is a 8-bit immediate we should fold the immediate
 313       // instead. This reduces code size.
 314       // e.g.
 315       // movl 4(%esp), %eax
 316       // addl $4, %eax
 317       // vs.
 318       // movl $4, %eax
 319       // addl 4(%esp), %eax
 320       // The former is 2 bytes shorter. In case where the increment is 1, then
 321       // the saving can be 4 bytes (by using incl %eax).
 322       if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
 323         if (Imm->getAPIntValue().isSignedIntN(8))
 324           return false;
 325
 326       // If the other operand is a TLS address, we should fold it instead.
 327       // This produces
 328       // movl    %gs:0, %eax
 329       // leal    i@NTPOFF(%eax), %eax
 330       // instead of
 331       // movl    $i@NTPOFF, %eax
 332       // addl    %gs:0, %eax
 333       // if the block also has an access to a second TLS address this will save
 334       // a load.
 335       // FIXME: This is probably also true for non TLS addresses.
 336       if (Op1.getOpcode() == X86ISD::Wrapper) {
 337         SDValue Val = Op1.getOperand(0);
 338         if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
 339           return false;
 340       }
 341     }
 342     }
 343
 344   // Proceed to 'generic' cycle finder code
 345   return SelectionDAGISel::IsLegalAndProfitableToFold(N, U, Root);
 346 }
 347
 348 /// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand
 349 /// and move load below the TokenFactor. Replace store's chain operand with
 350 /// load's chain result.
 351 static void MoveBelowTokenFactor(SelectionDAG *CurDAG, SDValue Load,
 352                                  SDValue Store, SDValue TF) {
 353   SmallVector<SDValue, 4> Ops;
 354   for (unsigned i = 0, e = TF.getNode()->getNumOperands(); i != e; ++i)
 355     if (Load.getNode() == TF.getOperand(i).getNode())
 356       Ops.push_back(Load.getOperand(0));
 357     else
 358       Ops.push_back(TF.getOperand(i));
 359   SDValue NewTF = CurDAG->UpdateNodeOperands(TF, &Ops[0], Ops.size());
 360   SDValue NewLoad = CurDAG->UpdateNodeOperands(Load, NewTF,
 361                                                Load.getOperand(1),
 362                                                Load.getOperand(2));
 363   CurDAG->UpdateNodeOperands(Store, NewLoad.getValue(1), Store.getOperand(1),
 364                              Store.getOperand(2), Store.getOperand(3));
 365 }
 366
 367 /// isRMWLoad - Return true if N is a load that's part of RMW sub-DAG.
 368 ///
 369 static bool isRMWLoad(SDValue N, SDValue Chain, SDValue Address,
 370                       SDValue &Load) {
 371   if (N.getOpcode() == ISD::BIT_CONVERT)
 372     N = N.getOperand(0);
 373
 374   LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
 375   if (!LD || LD->isVolatile())
 376     return false;
 377   if (LD->getAddressingMode() != ISD::UNINDEXED)
 378     return false;
 379
 380   ISD::LoadExtType ExtType = LD->getExtensionType();
 381   if (ExtType != ISD::NON_EXTLOAD && ExtType != ISD::EXTLOAD)
 382     return false;
 383
 384   if (N.hasOneUse() &&
 385       N.getOperand(1) == Address &&
 386       N.getNode()->isOperandOf(Chain.getNode())) {
 387     Load = N;
 388     return true;
 389   }
 390   return false;
 391 }
 392
 393 /// MoveBelowCallSeqStart - Replace CALLSEQ_START operand with load's chain
 394 /// operand and move load below the call's chain operand.
 395 static void MoveBelowCallSeqStart(SelectionDAG *CurDAG, SDValue Load,
 396                                   SDValue Call, SDValue CallSeqStart) {
 397   SmallVector<SDValue, 8> Ops;
 398   SDValue Chain = CallSeqStart.getOperand(0);
 399   if (Chain.getNode() == Load.getNode())
 400     Ops.push_back(Load.getOperand(0));
 401   else {
 402     assert(Chain.getOpcode() == ISD::TokenFactor &&
 403            "Unexpected CallSeqStart chain operand");
 404     for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
 405       if (Chain.getOperand(i).getNode() == Load.getNode())
 406         Ops.push_back(Load.getOperand(0));
 407       else
 408         Ops.push_back(Chain.getOperand(i));
 409     SDValue NewChain =
 410       CurDAG->getNode(ISD::TokenFactor, Load.getDebugLoc(),
 411                       MVT::Other, &Ops[0], Ops.size());
 412     Ops.clear();
 413     Ops.push_back(NewChain);
 414   }
 415   for (unsigned i = 1, e = CallSeqStart.getNumOperands(); i != e; ++i)
 416     Ops.push_back(CallSeqStart.getOperand(i));
 417   CurDAG->UpdateNodeOperands(CallSeqStart, &Ops[0], Ops.size());
 418   CurDAG->UpdateNodeOperands(Load, Call.getOperand(0),
 419                              Load.getOperand(1), Load.getOperand(2));
 420   Ops.clear();
 421   Ops.push_back(SDValue(Load.getNode(), 1));
 422   for (unsigned i = 1, e = Call.getNode()->getNumOperands(); i != e; ++i)
 423     Ops.push_back(Call.getOperand(i));
 424   CurDAG->UpdateNodeOperands(Call, &Ops[0], Ops.size());
 425 }
 426
 427 /// isCalleeLoad - Return true if call address is a load and it can be
 428 /// moved below CALLSEQ_START and the chains leading up to the call.
 429 /// Return the CALLSEQ_START by reference as a second output.
 430 static bool isCalleeLoad(SDValue Callee, SDValue &Chain) {
 431   if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
 432     return false;
 433   LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
 434   if (!LD ||
 435       LD->isVolatile() ||
 436       LD->getAddressingMode() != ISD::UNINDEXED ||
 437       LD->getExtensionType() != ISD::NON_EXTLOAD)
 438     return false;
 439
 440   // Now let's find the callseq_start.
 441   while (Chain.getOpcode() != ISD::CALLSEQ_START) {
 442     if (!Chain.hasOneUse())
 443       return false;
 444     Chain = Chain.getOperand(0);
 445   }
 446
 447   if (Chain.getOperand(0).getNode() == Callee.getNode())
 448     return true;
 449   if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
 450       Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()))
 451     return true;
 452   return false;
 453 }
 454
 455
 456 /// PreprocessForRMW - Preprocess the DAG to make instruction selection better.
 457 /// This is only run if not in -O0 mode.
 458 /// This allows the instruction selector to pick more read-modify-write
 459 /// instructions. This is a common case:
 460 ///
 461 ///     [Load chain]
 462 ///         ^
 463 ///         |
 464 ///       [Load]
 465 ///       ^    ^
 466 ///       |    |
 467 ///      /      \-
 468 ///     /         |
 469 /// [TokenFactor] [Op]
 470 ///     ^          ^
 471 ///     |          |
 472 ///      \        /
 473 ///       \      /
 474 ///       [Store]
 475 ///
 476 /// The fact the store's chain operand != load's chain will prevent the
 477 /// (store (op (load))) instruction from being selected. We can transform it to:
 478 ///
 479 ///     [Load chain]
 480 ///         ^
 481 ///         |
 482 ///    [TokenFactor]
 483 ///         ^
 484 ///         |
 485 ///       [Load]
 486 ///       ^    ^
 487 ///       |    |
 488 ///       |     \-
 489 ///       |       |
 490 ///       |     [Op]
 491 ///       |       ^
 492 ///       |       |
 493 ///       \      /
 494 ///        \    /
 495 ///       [Store]
 496 void X86DAGToDAGISel::PreprocessForRMW() {
 497   for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
 498          E = CurDAG->allnodes_end(); I != E; ++I) {
 499     if (I->getOpcode() == X86ISD::CALL) {
 500       /// Also try moving call address load from outside callseq_start to just
 501       /// before the call to allow it to be folded.
 502       ///
 503       ///     [Load chain]
 504       ///         ^
 505       ///         |
 506       ///       [Load]
 507       ///       ^    ^
 508       ///       |    |
 509       ///      /      \--
 510       ///     /          |
 511       ///[CALLSEQ_START] |
 512       ///     ^          |
 513       ///     |          |
 514       /// [LOAD/C2Reg]   |
 515       ///     |          |
 516       ///      \        /
 517       ///       \      /
 518       ///       [CALL]
 519       SDValue Chain = I->getOperand(0);
 520       SDValue Load  = I->getOperand(1);
 521       if (!isCalleeLoad(Load, Chain))
 522         continue;
 523       MoveBelowCallSeqStart(CurDAG, Load, SDValue(I, 0), Chain);
 524       ++NumLoadMoved;
 525       continue;
 526     }
 527
 528     if (!ISD::isNON_TRUNCStore(I))
 529       continue;
 530     SDValue Chain = I->getOperand(0);
 531
 532     if (Chain.getNode()->getOpcode() != ISD::TokenFactor)
 533       continue;
 534
 535     SDValue N1 = I->getOperand(1);
 536     SDValue N2 = I->getOperand(2);
 537     if ((N1.getValueType().isFloatingPoint() &&
 538          !N1.getValueType().isVector()) ||
 539         !N1.hasOneUse())
 540       continue;
 541
 542     bool RModW = false;
 543     SDValue Load;
 544     unsigned Opcode = N1.getNode()->getOpcode();
 545     switch (Opcode) {
 546     case ISD::ADD:
 547     case ISD::MUL:
 548     case ISD::AND:
 549     case ISD::OR:
 550     case ISD::XOR:
 551     case ISD::ADDC:
 552     case ISD::ADDE:
 553     case ISD::VECTOR_SHUFFLE: {
 554       SDValue N10 = N1.getOperand(0);
 555       SDValue N11 = N1.getOperand(1);
 556       RModW = isRMWLoad(N10, Chain, N2, Load);
 557       if (!RModW)
 558         RModW = isRMWLoad(N11, Chain, N2, Load);
 559       break;
 560     }
 561     case ISD::SUB:
 562     case ISD::SHL:
 563     case ISD::SRA:
 564     case ISD::SRL:
 565     case ISD::ROTL:
 566     case ISD::ROTR:
 567     case ISD::SUBC:
 568     case ISD::SUBE:
 569     case X86ISD::SHLD:
 570     case X86ISD::SHRD: {
 571       SDValue N10 = N1.getOperand(0);
 572       RModW = isRMWLoad(N10, Chain, N2, Load);
 573       break;
 574     }
 575     }
 576
 577     if (RModW) {
 578       MoveBelowTokenFactor(CurDAG, Load, SDValue(I, 0), Chain);
 579       ++NumLoadMoved;
 580     }
 581   }
 582 }
 583
 584
 585 /// PreprocessForFPConvert - Walk over the dag lowering fpround and fpextend
 586 /// nodes that target the FP stack to be store and load to the stack.  This is a
 587 /// gross hack.  We would like to simply mark these as being illegal, but when
 588 /// we do that, legalize produces these when it expands calls, then expands
 589 /// these in the same legalize pass.  We would like dag combine to be able to
 590 /// hack on these between the call expansion and the node legalization.  As such
 591 /// this pass basically does "really late" legalization of these inline with the
 592 /// X86 isel pass.
 593 void X86DAGToDAGISel::PreprocessForFPConvert() {
 594   for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
 595        E = CurDAG->allnodes_end(); I != E; ) {
 596     SDNode *N = I++;  // Preincrement iterator to avoid invalidation issues.
 597     if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
 598       continue;
 599
 600     // If the source and destination are SSE registers, then this is a legal
 601     // conversion that should not be lowered.
 602     EVT SrcVT = N->getOperand(0).getValueType();
 603     EVT DstVT = N->getValueType(0);
 604     bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT);
 605     bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT);
 606     if (SrcIsSSE && DstIsSSE)
 607       continue;
 608
 609     if (!SrcIsSSE && !DstIsSSE) {
 610       // If this is an FPStack extension, it is a noop.
 611       if (N->getOpcode() == ISD::FP_EXTEND)
 612         continue;
 613       // If this is a value-preserving FPStack truncation, it is a noop.
 614       if (N->getConstantOperandVal(1))
 615         continue;
 616     }
 617
 618     // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
 619     // FPStack has extload and truncstore.  SSE can fold direct loads into other
 620     // operations.  Based on this, decide what we want to do.
 621     EVT MemVT;
 622     if (N->getOpcode() == ISD::FP_ROUND)
 623       MemVT = DstVT;  // FP_ROUND must use DstVT, we can't do a 'trunc load'.
 624     else
 625       MemVT = SrcIsSSE ? SrcVT : DstVT;
 626
 627     SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
 628     DebugLoc dl = N->getDebugLoc();
 629
 630     // FIXME: optimize the case where the src/dest is a load or store?
 631     SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
 632                                           N->getOperand(0),
 633                                           MemTmp, NULL, 0, MemVT);
 634     SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
 635                                         NULL, 0, MemVT);
 636
 637     // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
 638     // extload we created.  This will cause general havok on the dag because
 639     // anything below the conversion could be folded into other existing nodes.
 640     // To avoid invalidating 'I', back it up to the convert node.
 641     --I;
 642     CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
 643
 644     // Now that we did that, the node is dead.  Increment the iterator to the
 645     // next node to process, then delete N.
 646     ++I;
 647     CurDAG->DeleteNode(N);
 648   }
 649 }
 650
 651 /// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
 652 /// when it has created a SelectionDAG for us to codegen.
 653 void X86DAGToDAGISel::InstructionSelect() {
 654   const Function *F = MF->getFunction();
 655   OptForSize = F->hasFnAttr(Attribute::OptimizeForSize);
 656
 657   DEBUG(BB->dump());
 658   if (OptLevel != CodeGenOpt::None)
 659     PreprocessForRMW();
 660
 661   // FIXME: This should only happen when not compiled with -O0.
 662   PreprocessForFPConvert();
 663
 664   // Codegen the basic block.
 665 #ifndef NDEBUG
 666   DEBUG(errs() << "===== Instruction selection begins:\n");
 667   Indent = 0;
 668 #endif
 669   SelectRoot(*CurDAG);
 670 #ifndef NDEBUG
 671   DEBUG(errs() << "===== Instruction selection ends:\n");
 672 #endif
 673
 674   CurDAG->RemoveDeadNodes();
 675 }
 676
 677 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
 678 /// the main function.
 679 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
 680                                              MachineFrameInfo *MFI) {
 681   const TargetInstrInfo *TII = TM.getInstrInfo();
 682   if (Subtarget->isTargetCygMing())
 683     BuildMI(BB, DebugLoc::getUnknownLoc(),
 684             TII->get(X86::CALLpcrel32)).addExternalSymbol("__main");
 685 }
 686
 687 void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
 688   // If this is main, emit special code for main.
 689   MachineBasicBlock *BB = MF.begin();
 690   if (Fn.hasExternalLinkage() && Fn.getName() == "main")
 691     EmitSpecialCodeForMain(BB, MF.getFrameInfo());
 692 }
 693
 694
 695 bool X86DAGToDAGISel::MatchSegmentBaseAddress(SDValue N,
 696                                               X86ISelAddressMode &AM) {
 697   assert(N.getOpcode() == X86ISD::SegmentBaseAddress);
 698   SDValue Segment = N.getOperand(0);
 699
 700   if (AM.Segment.getNode() == 0) {
 701     AM.Segment = Segment;
 702     return false;
 703   }
 704
 705   return true;
 706 }
 707
 708 bool X86DAGToDAGISel::MatchLoad(SDValue N, X86ISelAddressMode &AM) {
 709   // This optimization is valid because the GNU TLS model defines that
 710   // gs:0 (or fs:0 on X86-64) contains its own address.
 711   // For more information see http://people.redhat.com/drepper/tls.pdf
 712
 713   SDValue Address = N.getOperand(1);
 714   if (Address.getOpcode() == X86ISD::SegmentBaseAddress &&
 715       !MatchSegmentBaseAddress (Address, AM))
 716     return false;
 717
 718   return true;
 719 }
 720
 721 /// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes
 722 /// into an addressing mode.  These wrap things that will resolve down into a
 723 /// symbol reference.  If no match is possible, this returns true, otherwise it
 724 /// returns false.
 725 bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
 726   // If the addressing mode already has a symbol as the displacement, we can
 727   // never match another symbol.
 728   if (AM.hasSymbolicDisplacement())
 729     return true;
 730
 731   SDValue N0 = N.getOperand(0);
 732   CodeModel::Model M = TM.getCodeModel();
 733
 734   // Handle X86-64 rip-relative addresses.  We check this before checking direct
 735   // folding because RIP is preferable to non-RIP accesses.
 736   if (Subtarget->is64Bit() &&
 737       // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
 738       // they cannot be folded into immediate fields.
 739       // FIXME: This can be improved for kernel and other models?
 740       (M == CodeModel::Small || CodeModel::Kernel) &&
 741       // Base and index reg must be 0 in order to use %rip as base and lowering
 742       // must allow RIP.
 743       !AM.hasBaseOrIndexReg() && N.getOpcode() == X86ISD::WrapperRIP) {
 744     if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
 745       int64_t Offset = AM.Disp + G->getOffset();
 746       if (!X86::isOffsetSuitableForCodeModel(Offset, M)) return true;
 747       AM.GV = G->getGlobal();
 748       AM.Disp = Offset;
 749       AM.SymbolFlags = G->getTargetFlags();
 750     } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
 751       int64_t Offset = AM.Disp + CP->getOffset();
 752       if (!X86::isOffsetSuitableForCodeModel(Offset, M)) return true;
 753       AM.CP = CP->getConstVal();
 754       AM.Align = CP->getAlignment();
 755       AM.Disp = Offset;
 756       AM.SymbolFlags = CP->getTargetFlags();
 757     } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
 758       AM.ES = S->getSymbol();
 759       AM.SymbolFlags = S->getTargetFlags();
 760     } else {
 761       JumpTableSDNode *J = cast<JumpTableSDNode>(N0);
 762       AM.JT = J->getIndex();
 763       AM.SymbolFlags = J->getTargetFlags();
 764     }
 765
 766     if (N.getOpcode() == X86ISD::WrapperRIP)
 767       AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
 768     return false;
 769   }
 770
 771   // Handle the case when globals fit in our immediate field: This is true for
 772   // X86-32 always and X86-64 when in -static -mcmodel=small mode.  In 64-bit
 773   // mode, this results in a non-RIP-relative computation.
 774   if (!Subtarget->is64Bit() ||
 775       ((M == CodeModel::Small || M == CodeModel::Kernel) &&
 776        TM.getRelocationModel() == Reloc::Static)) {
 777     if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
 778       AM.GV = G->getGlobal();
 779       AM.Disp += G->getOffset();
 780       AM.SymbolFlags = G->getTargetFlags();
 781     } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
 782       AM.CP = CP->getConstVal();
 783       AM.Align = CP->getAlignment();
 784       AM.Disp += CP->getOffset();
 785       AM.SymbolFlags = CP->getTargetFlags();
 786     } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
 787       AM.ES = S->getSymbol();
 788       AM.SymbolFlags = S->getTargetFlags();
 789     } else {
 790       JumpTableSDNode *J = cast<JumpTableSDNode>(N0);
 791       AM.JT = J->getIndex();
 792       AM.SymbolFlags = J->getTargetFlags();
 793     }
 794     return false;
 795   }
 796
 797   return true;
 798 }
 799
 800 /// MatchAddress - Add the specified node to the specified addressing mode,
 801 /// returning true if it cannot be done.  This just pattern matches for the
 802 /// addressing mode.
 803 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) {
 804   if (MatchAddressRecursively(N, AM, 0))
 805     return true;
 806
 807   // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
 808   // a smaller encoding and avoids a scaled-index.
 809   if (AM.Scale == 2 &&
 810       AM.BaseType == X86ISelAddressMode::RegBase &&
 811       AM.Base.Reg.getNode() == 0) {
 812     AM.Base.Reg = AM.IndexReg;
 813     AM.Scale = 1;
 814   }
 815
 816   return false;
 817 }
 818
 819 bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
 820                                               unsigned Depth) {
 821   bool is64Bit = Subtarget->is64Bit();
 822   DebugLoc dl = N.getDebugLoc();
 823   DEBUG({
 824       errs() << "MatchAddress: ";
 825       AM.dump();
 826     });
 827   // Limit recursion.
 828   if (Depth > 5)
 829     return MatchAddressBase(N, AM);
 830
 831   CodeModel::Model M = TM.getCodeModel();
 832
 833   // If this is already a %rip relative address, we can only merge immediates
 834   // into it.  Instead of handling this in every case, we handle it here.
 835   // RIP relative addressing: %rip + 32-bit displacement!
 836   if (AM.isRIPRelative()) {
 837     // FIXME: JumpTable and ExternalSymbol address currently don't like
 838     // displacements.  It isn't very important, but this should be fixed for
 839     // consistency.
 840     if (!AM.ES && AM.JT != -1) return true;
 841
 842     if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N)) {
 843       int64_t Val = AM.Disp + Cst->getSExtValue();
 844       if (X86::isOffsetSuitableForCodeModel(Val, M,
 845                                             AM.hasSymbolicDisplacement())) {
 846         AM.Disp = Val;
 847         return false;
 848       }
 849     }
 850     return true;
 851   }
 852
 853   switch (N.getOpcode()) {
 854   default: break;
 855   case ISD::Constant: {
 856     uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
 857     if (!is64Bit ||
 858         X86::isOffsetSuitableForCodeModel(AM.Disp + Val, M,
 859                                           AM.hasSymbolicDisplacement())) {
 860       AM.Disp += Val;
 861       return false;
 862     }
 863     break;
 864   }
 865
 866   case X86ISD::SegmentBaseAddress:
 867     if (!MatchSegmentBaseAddress(N, AM))
 868       return false;
 869     break;
 870
 871   case X86ISD::Wrapper:
 872   case X86ISD::WrapperRIP:
 873     if (!MatchWrapper(N, AM))
 874       return false;
 875     break;
 876
 877   case ISD::LOAD:
 878     if (!MatchLoad(N, AM))
 879       return false;
 880     break;
 881
 882   case ISD::FrameIndex:
 883     if (AM.BaseType == X86ISelAddressMode::RegBase
 884         && AM.Base.Reg.getNode() == 0) {
 885       AM.BaseType = X86ISelAddressMode::FrameIndexBase;
 886       AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
 887       return false;
 888     }
 889     break;
 890
 891   case ISD::SHL:
 892     if (AM.IndexReg.getNode() != 0 || AM.Scale != 1)
 893       break;
 894
 895     if (ConstantSDNode
 896           *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
 897       unsigned Val = CN->getZExtValue();
 898       // Note that we handle x<<1 as (,x,2) rather than (x,x) here so
 899       // that the base operand remains free for further matching. If
 900       // the base doesn't end up getting used, a post-processing step
 901       // in MatchAddress turns (,x,2) into (x,x), which is cheaper.
 902       if (Val == 1 || Val == 2 || Val == 3) {
 903         AM.Scale = 1 << Val;
 904         SDValue ShVal = N.getNode()->getOperand(0);
 905
 906         // Okay, we know that we have a scale by now.  However, if the scaled
 907         // value is an add of something and a constant, we can fold the
 908         // constant into the disp field here.
 909         if (ShVal.getNode()->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
 910             isa<ConstantSDNode>(ShVal.getNode()->getOperand(1))) {
 911           AM.IndexReg = ShVal.getNode()->getOperand(0);
 912           ConstantSDNode *AddVal =
 913             cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
 914           uint64_t Disp = AM.Disp + (AddVal->getSExtValue() << Val);
 915           if (!is64Bit ||
 916               X86::isOffsetSuitableForCodeModel(Disp, M,
 917                                                 AM.hasSymbolicDisplacement()))
 918             AM.Disp = Disp;
 919           else
 920             AM.IndexReg = ShVal;
 921         } else {
 922           AM.IndexReg = ShVal;
 923         }
 924         return false;
 925       }
 926     break;
 927     }
 928
 929   case ISD::SMUL_LOHI:
 930   case ISD::UMUL_LOHI:
 931     // A mul_lohi where we need the low part can be folded as a plain multiply.
 932     if (N.getResNo() != 0) break;
 933     // FALL THROUGH
 934   case ISD::MUL:
 935   case X86ISD::MUL_IMM:
 936     // X*[3,5,9] -> X+X*[2,4,8]
 937     if (AM.BaseType == X86ISelAddressMode::RegBase &&
 938         AM.Base.Reg.getNode() == 0 &&
 939         AM.IndexReg.getNode() == 0) {
 940       if (ConstantSDNode
 941             *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
 942         if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
 943             CN->getZExtValue() == 9) {
 944           AM.Scale = unsigned(CN->getZExtValue())-1;
 945
 946           SDValue MulVal = N.getNode()->getOperand(0);
 947           SDValue Reg;
 948
 949           // Okay, we know that we have a scale by now.  However, if the scaled
 950           // value is an add of something and a constant, we can fold the
 951           // constant into the disp field here.
 952           if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
 953               isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
 954             Reg = MulVal.getNode()->getOperand(0);
 955             ConstantSDNode *AddVal =
 956               cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
 957             uint64_t Disp = AM.Disp + AddVal->getSExtValue() *
 958                                       CN->getZExtValue();
 959             if (!is64Bit ||
 960                 X86::isOffsetSuitableForCodeModel(Disp, M,
 961                                                   AM.hasSymbolicDisplacement()))
 962               AM.Disp = Disp;
 963             else
 964               Reg = N.getNode()->getOperand(0);
 965           } else {
 966             Reg = N.getNode()->getOperand(0);
 967           }
 968
 969           AM.IndexReg = AM.Base.Reg = Reg;
 970           return false;
 971         }
 972     }
 973     break;
 974
 975   case ISD::SUB: {
 976     // Given A-B, if A can be completely folded into the address and
 977     // the index field with the index field unused, use -B as the index.
 978     // This is a win if a has multiple parts that can be folded into
 979     // the address. Also, this saves a mov if the base register has
 980     // other uses, since it avoids a two-address sub instruction, however
 981     // it costs an additional mov if the index register has other uses.
 982
 983     // Test if the LHS of the sub can be folded.
 984     X86ISelAddressMode Backup = AM;
 985     if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
 986       AM = Backup;
 987       break;
 988     }
 989     // Test if the index field is free for use.
 990     if (AM.IndexReg.getNode() || AM.isRIPRelative()) {
 991       AM = Backup;
 992       break;
 993     }
 994     int Cost = 0;
 995     SDValue RHS = N.getNode()->getOperand(1);
 996     // If the RHS involves a register with multiple uses, this
 997     // transformation incurs an extra mov, due to the neg instruction
 998     // clobbering its operand.
 999     if (!RHS.getNode()->hasOneUse() ||
1000         RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
1001         RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
1002         RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
1003         (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
1004          RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
1005       ++Cost;
1006     // If the base is a register with multiple uses, this
1007     // transformation may save a mov.
1008     if ((AM.BaseType == X86ISelAddressMode::RegBase &&
1009          AM.Base.Reg.getNode() &&
1010          !AM.Base.Reg.getNode()->hasOneUse()) ||
1011         AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1012       --Cost;
1013     // If the folded LHS was interesting, this transformation saves
1014     // address arithmetic.
1015     if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) +
1016         ((AM.Disp != 0) && (Backup.Disp == 0)) +
1017         (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2)
1018       --Cost;
1019     // If it doesn't look like it may be an overall win, don't do it.
1020     if (Cost >= 0) {
1021       AM = Backup;
1022       break;
1023     }
1024
1025     // Ok, the transformation is legal and appears profitable. Go for it.
1026     SDValue Zero = CurDAG->getConstant(0, N.getValueType());
1027     SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
1028     AM.IndexReg = Neg;
1029     AM.Scale = 1;
1030
1031     // Insert the new nodes into the topological ordering.
1032     if (Zero.getNode()->getNodeId() == -1 ||
1033         Zero.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1034       CurDAG->RepositionNode(N.getNode(), Zero.getNode());
1035       Zero.getNode()->setNodeId(N.getNode()->getNodeId());
1036     }
1037     if (Neg.getNode()->getNodeId() == -1 ||
1038         Neg.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1039       CurDAG->RepositionNode(N.getNode(), Neg.getNode());
1040       Neg.getNode()->setNodeId(N.getNode()->getNodeId());
1041     }
1042     return false;
1043   }
1044
1045   case ISD::ADD: {
1046     X86ISelAddressMode Backup = AM;
1047     if (!MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1) &&
1048         !MatchAddressRecursively(N.getNode()->getOperand(1), AM, Depth+1))
1049       return false;
1050     AM = Backup;
1051     if (!MatchAddressRecursively(N.getNode()->getOperand(1), AM, Depth+1) &&
1052         !MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1))
1053       return false;
1054     AM = Backup;
1055
1056     // If we couldn't fold both operands into the address at the same time,
1057     // see if we can just put each operand into a register and fold at least
1058     // the add.
1059     if (AM.BaseType == X86ISelAddressMode::RegBase &&
1060         !AM.Base.Reg.getNode() &&
1061         !AM.IndexReg.getNode()) {
1062       AM.Base.Reg = N.getNode()->getOperand(0);
1063       AM.IndexReg = N.getNode()->getOperand(1);
1064       AM.Scale = 1;
1065       return false;
1066     }
1067     break;
1068   }
1069
1070   case ISD::OR:
1071     // Handle "X | C" as "X + C" iff X is known to have C bits clear.
1072     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1073       X86ISelAddressMode Backup = AM;
1074       uint64_t Offset = CN->getSExtValue();
1075       // Start with the LHS as an addr mode.
1076       if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1077           // Address could not have picked a GV address for the displacement.
1078           AM.GV == NULL &&
1079           // On x86-64, the resultant disp must fit in 32-bits.
1080           (!is64Bit ||
1081            X86::isOffsetSuitableForCodeModel(AM.Disp + Offset, M,
1082                                              AM.hasSymbolicDisplacement())) &&
1083           // Check to see if the LHS & C is zero.
1084           CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
1085         AM.Disp += Offset;
1086         return false;
1087       }
1088       AM = Backup;
1089     }
1090     break;
1091
1092   case ISD::AND: {
1093     // Perform some heroic transforms on an and of a constant-count shift
1094     // with a constant to enable use of the scaled offset field.
1095
1096     SDValue Shift = N.getOperand(0);
1097     if (Shift.getNumOperands() != 2) break;
1098
1099     // Scale must not be used already.
1100     if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
1101
1102     SDValue X = Shift.getOperand(0);
1103     ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N.getOperand(1));
1104     ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
1105     if (!C1 || !C2) break;
1106
1107     // Handle "(X >> (8-C1)) & C2" as "(X >> 8) & 0xff)" if safe. This
1108     // allows us to convert the shift and and into an h-register extract and
1109     // a scaled index.
1110     if (Shift.getOpcode() == ISD::SRL && Shift.hasOneUse()) {
1111       unsigned ScaleLog = 8 - C1->getZExtValue();
1112       if (ScaleLog > 0 && ScaleLog < 4 &&
1113           C2->getZExtValue() == (UINT64_C(0xff) << ScaleLog)) {
1114         SDValue Eight = CurDAG->getConstant(8, MVT::i8);
1115         SDValue Mask = CurDAG->getConstant(0xff, N.getValueType());
1116         SDValue Srl = CurDAG->getNode(ISD::SRL, dl, N.getValueType(),
1117                                       X, Eight);
1118         SDValue And = CurDAG->getNode(ISD::AND, dl, N.getValueType(),
1119                                       Srl, Mask);
1120         SDValue ShlCount = CurDAG->getConstant(ScaleLog, MVT::i8);
1121         SDValue Shl = CurDAG->getNode(ISD::SHL, dl, N.getValueType(),
1122                                       And, ShlCount);
1123
1124         // Insert the new nodes into the topological ordering.
1125         if (Eight.getNode()->getNodeId() == -1 ||
1126             Eight.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1127           CurDAG->RepositionNode(X.getNode(), Eight.getNode());
1128           Eight.getNode()->setNodeId(X.getNode()->getNodeId());
1129         }
1130         if (Mask.getNode()->getNodeId() == -1 ||
1131             Mask.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1132           CurDAG->RepositionNode(X.getNode(), Mask.getNode());
1133           Mask.getNode()->setNodeId(X.getNode()->getNodeId());
1134         }
1135         if (Srl.getNode()->getNodeId() == -1 ||
1136             Srl.getNode()->getNodeId() > Shift.getNode()->getNodeId()) {
1137           CurDAG->RepositionNode(Shift.getNode(), Srl.getNode());
1138           Srl.getNode()->setNodeId(Shift.getNode()->getNodeId());
1139         }
1140         if (And.getNode()->getNodeId() == -1 ||
1141             And.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1142           CurDAG->RepositionNode(N.getNode(), And.getNode());
1143           And.getNode()->setNodeId(N.getNode()->getNodeId());
1144         }
1145         if (ShlCount.getNode()->getNodeId() == -1 ||
1146             ShlCount.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1147           CurDAG->RepositionNode(X.getNode(), ShlCount.getNode());
1148           ShlCount.getNode()->setNodeId(N.getNode()->getNodeId());
1149         }
1150         if (Shl.getNode()->getNodeId() == -1 ||
1151             Shl.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1152           CurDAG->RepositionNode(N.getNode(), Shl.getNode());
1153           Shl.getNode()->setNodeId(N.getNode()->getNodeId());
1154         }
1155         CurDAG->ReplaceAllUsesWith(N, Shl);
1156         AM.IndexReg = And;
1157         AM.Scale = (1 << ScaleLog);
1158         return false;
1159       }
1160     }
1161
1162     // Handle "(X << C1) & C2" as "(X & (C2>>C1)) << C1" if safe and if this
1163     // allows us to fold the shift into this addressing mode.
1164     if (Shift.getOpcode() != ISD::SHL) break;
1165
1166     // Not likely to be profitable if either the AND or SHIFT node has more
1167     // than one use (unless all uses are for address computation). Besides,
1168     // isel mechanism requires their node ids to be reused.
1169     if (!N.hasOneUse() || !Shift.hasOneUse())
1170       break;
1171
1172     // Verify that the shift amount is something we can fold.
1173     unsigned ShiftCst = C1->getZExtValue();
1174     if (ShiftCst != 1 && ShiftCst != 2 && ShiftCst != 3)
1175       break;
1176
1177     // Get the new AND mask, this folds to a constant.
1178     SDValue NewANDMask = CurDAG->getNode(ISD::SRL, dl, N.getValueType(),
1179                                          SDValue(C2, 0), SDValue(C1, 0));
1180     SDValue NewAND = CurDAG->getNode(ISD::AND, dl, N.getValueType(), X,
1181                                      NewANDMask);
1182     SDValue NewSHIFT = CurDAG->getNode(ISD::SHL, dl, N.getValueType(),
1183                                        NewAND, SDValue(C1, 0));
1184
1185     // Insert the new nodes into the topological ordering.
1186     if (C1->getNodeId() > X.getNode()->getNodeId()) {
1187       CurDAG->RepositionNode(X.getNode(), C1);
1188       C1->setNodeId(X.getNode()->getNodeId());
1189     }
1190     if (NewANDMask.getNode()->getNodeId() == -1 ||
1191         NewANDMask.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1192       CurDAG->RepositionNode(X.getNode(), NewANDMask.getNode());
1193       NewANDMask.getNode()->setNodeId(X.getNode()->getNodeId());
1194     }
1195     if (NewAND.getNode()->getNodeId() == -1 ||
1196         NewAND.getNode()->getNodeId() > Shift.getNode()->getNodeId()) {
1197       CurDAG->RepositionNode(Shift.getNode(), NewAND.getNode());
1198       NewAND.getNode()->setNodeId(Shift.getNode()->getNodeId());
1199     }
1200     if (NewSHIFT.getNode()->getNodeId() == -1 ||
1201         NewSHIFT.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1202       CurDAG->RepositionNode(N.getNode(), NewSHIFT.getNode());
1203       NewSHIFT.getNode()->setNodeId(N.getNode()->getNodeId());
1204     }
1205
1206     CurDAG->ReplaceAllUsesWith(N, NewSHIFT);
1207
1208     AM.Scale = 1 << ShiftCst;
1209     AM.IndexReg = NewAND;
1210     return false;
1211   }
1212   }
1213
1214   return MatchAddressBase(N, AM);
1215 }
1216
1217 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
1218 /// specified addressing mode without any further recursion.
1219 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
1220   // Is the base register already occupied?
1221   if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.getNode()) {
1222     // If so, check to see if the scale index register is set.
1223     if (AM.IndexReg.getNode() == 0) {
1224       AM.IndexReg = N;
1225       AM.Scale = 1;
1226       return false;
1227     }
1228
1229     // Otherwise, we cannot select it.
1230     return true;
1231   }
1232
1233   // Default, generate it as a register.
1234   AM.BaseType = X86ISelAddressMode::RegBase;
1235   AM.Base.Reg = N;
1236   return false;
1237 }
1238
1239 /// SelectAddr - returns true if it is able pattern match an addressing mode.
1240 /// It returns the operands which make up the maximal addressing mode it can
1241 /// match by reference.
1242 bool X86DAGToDAGISel::SelectAddr(SDValue Op, SDValue N, SDValue &Base,
1243                                  SDValue &Scale, SDValue &Index,
1244                                  SDValue &Disp, SDValue &Segment) {
1245   X86ISelAddressMode AM;
1246   bool Done = false;
1247   if (AvoidDupAddrCompute && !N.hasOneUse()) {
1248     unsigned Opcode = N.getOpcode();
1249     if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex &&
1250         Opcode != X86ISD::Wrapper && Opcode != X86ISD::WrapperRIP) {
1251       // If we are able to fold N into addressing mode, then we'll allow it even
1252       // if N has multiple uses. In general, addressing computation is used as
1253       // addresses by all of its uses. But watch out for CopyToReg uses, that
1254       // means the address computation is liveout. It will be computed by a LEA
1255       // so we want to avoid computing the address twice.
1256       for (SDNode::use_iterator UI = N.getNode()->use_begin(),
1257              UE = N.getNode()->use_end(); UI != UE; ++UI) {
1258         if (UI->getOpcode() == ISD::CopyToReg) {
1259           MatchAddressBase(N, AM);
1260           Done = true;
1261           break;
1262         }
1263       }
1264     }
1265   }
1266
1267   if (!Done && MatchAddress(N, AM))
1268     return false;
1269
1270   EVT VT = N.getValueType();
1271   if (AM.BaseType == X86ISelAddressMode::RegBase) {
1272     if (!AM.Base.Reg.getNode())
1273       AM.Base.Reg = CurDAG->getRegister(0, VT);
1274   }
1275
1276   if (!AM.IndexReg.getNode())
1277     AM.IndexReg = CurDAG->getRegister(0, VT);
1278
1279   getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1280   return true;
1281 }
1282
1283 /// SelectScalarSSELoad - Match a scalar SSE load.  In particular, we want to
1284 /// match a load whose top elements are either undef or zeros.  The load flavor
1285 /// is derived from the type of N, which is either v4f32 or v2f64.
1286 bool X86DAGToDAGISel::SelectScalarSSELoad(SDValue Op, SDValue Pred,
1287                                           SDValue N, SDValue &Base,
1288                                           SDValue &Scale, SDValue &Index,
1289                                           SDValue &Disp, SDValue &Segment,
1290                                           SDValue &InChain,
1291                                           SDValue &OutChain) {
1292   if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1293     InChain = N.getOperand(0).getValue(1);
1294     if (ISD::isNON_EXTLoad(InChain.getNode()) &&
1295         InChain.getValue(0).hasOneUse() &&
1296         N.hasOneUse() &&
1297         IsLegalAndProfitableToFold(N.getNode(), Pred.getNode(), Op.getNode())) {
1298       LoadSDNode *LD = cast<LoadSDNode>(InChain);
1299       if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1300         return false;
1301       OutChain = LD->getChain();
1302       return true;
1303     }
1304   }
1305
1306   // Also handle the case where we explicitly require zeros in the top
1307   // elements.  This is a vector shuffle from the zero vector.
1308   if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1309       // Check to see if the top elements are all zeros (or bitcast of zeros).
1310       N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1311       N.getOperand(0).getNode()->hasOneUse() &&
1312       ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1313       N.getOperand(0).getOperand(0).hasOneUse()) {
1314     // Okay, this is a zero extending load.  Fold it.
1315     LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1316     if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1317       return false;
1318     OutChain = LD->getChain();
1319     InChain = SDValue(LD, 1);
1320     return true;
1321   }
1322   return false;
1323 }
1324
1325
1326 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
1327 /// mode it matches can be cost effectively emitted as an LEA instruction.
1328 bool X86DAGToDAGISel::SelectLEAAddr(SDValue Op, SDValue N,
1329                                     SDValue &Base, SDValue &Scale,
1330                                     SDValue &Index, SDValue &Disp) {
1331   X86ISelAddressMode AM;
1332
1333   // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
1334   // segments.
1335   SDValue Copy = AM.Segment;
1336   SDValue T = CurDAG->getRegister(0, MVT::i32);
1337   AM.Segment = T;
1338   if (MatchAddress(N, AM))
1339     return false;
1340   assert (T == AM.Segment);
1341   AM.Segment = Copy;
1342
1343   EVT VT = N.getValueType();
1344   unsigned Complexity = 0;
1345   if (AM.BaseType == X86ISelAddressMode::RegBase)
1346     if (AM.Base.Reg.getNode())
1347       Complexity = 1;
1348     else
1349       AM.Base.Reg = CurDAG->getRegister(0, VT);
1350   else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1351     Complexity = 4;
1352
1353   if (AM.IndexReg.getNode())
1354     Complexity++;
1355   else
1356     AM.IndexReg = CurDAG->getRegister(0, VT);
1357
1358   // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1359   // a simple shift.
1360   if (AM.Scale > 1)
1361     Complexity++;
1362
1363   // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1364   // to a LEA. This is determined with some expermentation but is by no means
1365   // optimal (especially for code size consideration). LEA is nice because of
1366   // its three-address nature. Tweak the cost function again when we can run
1367   // convertToThreeAddress() at register allocation time.
1368   if (AM.hasSymbolicDisplacement()) {
1369     // For X86-64, we should always use lea to materialize RIP relative
1370     // addresses.
1371     if (Subtarget->is64Bit())
1372       Complexity = 4;
1373     else
1374       Complexity += 2;
1375   }
1376
1377   if (AM.Disp && (AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
1378     Complexity++;
1379
1380   // If it isn't worth using an LEA, reject it.
1381   if (Complexity <= 2)
1382     return false;
1383
1384   SDValue Segment;
1385   getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1386   return true;
1387 }
1388
1389 /// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes.
1390 bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue Op, SDValue N, SDValue &Base,
1391                                         SDValue &Scale, SDValue &Index,
1392                                         SDValue &Disp) {
1393   assert(Op.getOpcode() == X86ISD::TLSADDR);
1394   assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
1395   const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1396
1397   X86ISelAddressMode AM;
1398   AM.GV = GA->getGlobal();
1399   AM.Disp += GA->getOffset();
1400   AM.Base.Reg = CurDAG->getRegister(0, N.getValueType());
1401   AM.SymbolFlags = GA->getTargetFlags();
1402
1403   if (N.getValueType() == MVT::i32) {
1404     AM.Scale = 1;
1405     AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
1406   } else {
1407     AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
1408   }
1409
1410   SDValue Segment;
1411   getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1412   return true;
1413 }
1414
1415
1416 bool X86DAGToDAGISel::TryFoldLoad(SDValue P, SDValue N,
1417                                   SDValue &Base, SDValue &Scale,
1418                                   SDValue &Index, SDValue &Disp,
1419                                   SDValue &Segment) {
1420   if (ISD::isNON_EXTLoad(N.getNode()) &&
1421       N.hasOneUse() &&
1422       IsLegalAndProfitableToFold(N.getNode(), P.getNode(), P.getNode()))
1423     return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp, Segment);
1424   return false;
1425 }
1426
1427 /// getGlobalBaseReg - Return an SDNode that returns the value of
1428 /// the global base register. Output instructions required to
1429 /// initialize the global base register, if necessary.
1430 ///
1431 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1432   unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
1433   return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
1434 }
1435
1436 static SDNode *FindCallStartFromCall(SDNode *Node) {
1437   if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
1438     assert(Node->getOperand(0).getValueType() == MVT::Other &&
1439          "Node doesn't have a token chain argument!");
1440   return FindCallStartFromCall(Node->getOperand(0).getNode());
1441 }
1442
1443 SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
1444   SDValue Chain = Node->getOperand(0);
1445   SDValue In1 = Node->getOperand(1);
1446   SDValue In2L = Node->getOperand(2);
1447   SDValue In2H = Node->getOperand(3);
1448   SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1449   if (!SelectAddr(In1, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1450     return NULL;
1451   SDValue LSI = Node->getOperand(4);    // MemOperand
1452   const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, LSI, Chain};
1453   return CurDAG->getTargetNode(Opc, Node->getDebugLoc(),
1454                                MVT::i32, MVT::i32, MVT::Other, Ops,
1455                                array_lengthof(Ops));
1456 }
1457
1458 SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
1459   if (Node->hasAnyUseOfValue(0))
1460     return 0;
1461
1462   // Optimize common patterns for __sync_add_and_fetch and
1463   // __sync_sub_and_fetch where the result is not used. This allows us
1464   // to use "lock" version of add, sub, inc, dec instructions.
1465   // FIXME: Do not use special instructions but instead add the "lock"
1466   // prefix to the target node somehow. The extra information will then be
1467   // transferred to machine instruction and it denotes the prefix.
1468   SDValue Chain = Node->getOperand(0);
1469   SDValue Ptr = Node->getOperand(1);
1470   SDValue Val = Node->getOperand(2);
1471   SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1472   if (!SelectAddr(Ptr, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1473     return 0;
1474
1475   bool isInc = false, isDec = false, isSub = false, isCN = false;
1476   ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val);
1477   if (CN) {
1478     isCN = true;
1479     int64_t CNVal = CN->getSExtValue();
1480     if (CNVal == 1)
1481       isInc = true;
1482     else if (CNVal == -1)
1483       isDec = true;
1484     else if (CNVal >= 0)
1485       Val = CurDAG->getTargetConstant(CNVal, NVT);
1486     else {
1487       isSub = true;
1488       Val = CurDAG->getTargetConstant(-CNVal, NVT);
1489     }
1490   } else if (Val.hasOneUse() &&
1491              Val.getOpcode() == ISD::SUB &&
1492              X86::isZeroNode(Val.getOperand(0))) {
1493     isSub = true;
1494     Val = Val.getOperand(1);
1495   }
1496
1497   unsigned Opc = 0;
1498   switch (NVT.getSimpleVT().SimpleTy) {
1499   default: return 0;
1500   case MVT::i8:
1501     if (isInc)
1502       Opc = X86::LOCK_INC8m;
1503     else if (isDec)
1504       Opc = X86::LOCK_DEC8m;
1505     else if (isSub) {
1506       if (isCN)
1507         Opc = X86::LOCK_SUB8mi;
1508       else
1509         Opc = X86::LOCK_SUB8mr;
1510     } else {
1511       if (isCN)
1512         Opc = X86::LOCK_ADD8mi;
1513       else
1514         Opc = X86::LOCK_ADD8mr;
1515     }
1516     break;
1517   case MVT::i16:
1518     if (isInc)
1519       Opc = X86::LOCK_INC16m;
1520     else if (isDec)
1521       Opc = X86::LOCK_DEC16m;
1522     else if (isSub) {
1523       if (isCN) {
1524         if (Predicate_i16immSExt8(Val.getNode()))
1525           Opc = X86::LOCK_SUB16mi8;
1526         else
1527           Opc = X86::LOCK_SUB16mi;
1528       } else
1529         Opc = X86::LOCK_SUB16mr;
1530     } else {
1531       if (isCN) {
1532         if (Predicate_i16immSExt8(Val.getNode()))
1533           Opc = X86::LOCK_ADD16mi8;
1534         else
1535           Opc = X86::LOCK_ADD16mi;
1536       } else
1537         Opc = X86::LOCK_ADD16mr;
1538     }
1539     break;
1540   case MVT::i32:
1541     if (isInc)
1542       Opc = X86::LOCK_INC32m;
1543     else if (isDec)
1544       Opc = X86::LOCK_DEC32m;
1545     else if (isSub) {
1546       if (isCN) {
1547         if (Predicate_i32immSExt8(Val.getNode()))
1548           Opc = X86::LOCK_SUB32mi8;
1549         else
1550           Opc = X86::LOCK_SUB32mi;
1551       } else
1552         Opc = X86::LOCK_SUB32mr;
1553     } else {
1554       if (isCN) {
1555         if (Predicate_i32immSExt8(Val.getNode()))
1556           Opc = X86::LOCK_ADD32mi8;
1557         else
1558           Opc = X86::LOCK_ADD32mi;
1559       } else
1560         Opc = X86::LOCK_ADD32mr;
1561     }
1562     break;
1563   case MVT::i64:
1564     if (isInc)
1565       Opc = X86::LOCK_INC64m;
1566     else if (isDec)
1567       Opc = X86::LOCK_DEC64m;
1568     else if (isSub) {
1569       Opc = X86::LOCK_SUB64mr;
1570       if (isCN) {
1571         if (Predicate_i64immSExt8(Val.getNode()))
1572           Opc = X86::LOCK_SUB64mi8;
1573         else if (Predicate_i64immSExt32(Val.getNode()))
1574           Opc = X86::LOCK_SUB64mi32;
1575       }
1576     } else {
1577       Opc = X86::LOCK_ADD64mr;
1578       if (isCN) {
1579         if (Predicate_i64immSExt8(Val.getNode()))
1580           Opc = X86::LOCK_ADD64mi8;
1581         else if (Predicate_i64immSExt32(Val.getNode()))
1582           Opc = X86::LOCK_ADD64mi32;
1583       }
1584     }
1585     break;
1586   }
1587
1588   DebugLoc dl = Node->getDebugLoc();
1589   SDValue Undef = SDValue(CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF,
1590                                                 dl, NVT), 0);
1591   SDValue MemOp = CurDAG->getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
1592   if (isInc || isDec) {
1593     SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, MemOp, Chain };
1594     SDValue Ret = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7), 0);
1595     SDValue RetVals[] = { Undef, Ret };
1596     return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1597   } else {
1598     SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, MemOp, Chain };
1599     SDValue Ret = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 8), 0);
1600     SDValue RetVals[] = { Undef, Ret };
1601     return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1602   }
1603 }
1604
1605 SDNode *X86DAGToDAGISel::Select(SDValue N) {
1606   SDNode *Node = N.getNode();
1607   EVT NVT = Node->getValueType(0);
1608   unsigned Opc, MOpc;
1609   unsigned Opcode = Node->getOpcode();
1610   DebugLoc dl = Node->getDebugLoc();
1611
1612 #ifndef NDEBUG
1613   DEBUG({
1614       errs() << std::string(Indent, ' ') << "Selecting: ";
1615       Node->dump(CurDAG);
1616       errs() << '\n';
1617     });
1618   Indent += 2;
1619 #endif
1620
1621   if (Node->isMachineOpcode()) {
1622 #ifndef NDEBUG
1623     DEBUG({
1624         errs() << std::string(Indent-2, ' ') << "== ";
1625         Node->dump(CurDAG);
1626         errs() << '\n';
1627       });
1628     Indent -= 2;
1629 #endif
1630     return NULL;   // Already selected.
1631   }
1632
1633   switch (Opcode) {
1634   default: break;
1635   case X86ISD::GlobalBaseReg:
1636     return getGlobalBaseReg();
1637
1638   case X86ISD::ATOMOR64_DAG:
1639     return SelectAtomic64(Node, X86::ATOMOR6432);
1640   case X86ISD::ATOMXOR64_DAG:
1641     return SelectAtomic64(Node, X86::ATOMXOR6432);
1642   case X86ISD::ATOMADD64_DAG:
1643     return SelectAtomic64(Node, X86::ATOMADD6432);
1644   case X86ISD::ATOMSUB64_DAG:
1645     return SelectAtomic64(Node, X86::ATOMSUB6432);
1646   case X86ISD::ATOMNAND64_DAG:
1647     return SelectAtomic64(Node, X86::ATOMNAND6432);
1648   case X86ISD::ATOMAND64_DAG:
1649     return SelectAtomic64(Node, X86::ATOMAND6432);
1650   case X86ISD::ATOMSWAP64_DAG:
1651     return SelectAtomic64(Node, X86::ATOMSWAP6432);
1652
1653   case ISD::ATOMIC_LOAD_ADD: {
1654     SDNode *RetVal = SelectAtomicLoadAdd(Node, NVT);
1655     if (RetVal)
1656       return RetVal;
1657     break;
1658   }
1659
1660   case ISD::SMUL_LOHI:
1661   case ISD::UMUL_LOHI: {
1662     SDValue N0 = Node->getOperand(0);
1663     SDValue N1 = Node->getOperand(1);
1664
1665     bool isSigned = Opcode == ISD::SMUL_LOHI;
1666     if (!isSigned) {
1667       switch (NVT.getSimpleVT().SimpleTy) {
1668       default: llvm_unreachable("Unsupported VT!");
1669       case MVT::i8:  Opc = X86::MUL8r;  MOpc = X86::MUL8m;  break;
1670       case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
1671       case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
1672       case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
1673       }
1674     } else {
1675       switch (NVT.getSimpleVT().SimpleTy) {
1676       default: llvm_unreachable("Unsupported VT!");
1677       case MVT::i8:  Opc = X86::IMUL8r;  MOpc = X86::IMUL8m;  break;
1678       case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
1679       case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
1680       case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
1681       }
1682     }
1683
1684     unsigned LoReg, HiReg;
1685     switch (NVT.getSimpleVT().SimpleTy) {
1686     default: llvm_unreachable("Unsupported VT!");
1687     case MVT::i8:  LoReg = X86::AL;  HiReg = X86::AH;  break;
1688     case MVT::i16: LoReg = X86::AX;  HiReg = X86::DX;  break;
1689     case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
1690     case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
1691     }
1692
1693     SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1694     bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
1695     // Multiply is commmutative.
1696     if (!foldedLoad) {
1697       foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
1698       if (foldedLoad)
1699         std::swap(N0, N1);
1700     }
1701
1702     SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
1703                                             N0, SDValue()).getValue(1);
1704
1705     if (foldedLoad) {
1706       SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
1707                         InFlag };
1708       SDNode *CNode =
1709         CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
1710                               array_lengthof(Ops));
1711       InFlag = SDValue(CNode, 1);
1712       // Update the chain.
1713       ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
1714     } else {
1715       InFlag =
1716         SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
1717     }
1718
1719     // Copy the low half of the result, if it is needed.
1720     if (!N.getValue(0).use_empty()) {
1721       SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1722                                                 LoReg, NVT, InFlag);
1723       InFlag = Result.getValue(2);
1724       ReplaceUses(N.getValue(0), Result);
1725 #ifndef NDEBUG
1726       DEBUG({
1727           errs() << std::string(Indent-2, ' ') << "=> ";
1728           Result.getNode()->dump(CurDAG);
1729           errs() << '\n';
1730         });
1731 #endif
1732     }
1733     // Copy the high half of the result, if it is needed.
1734     if (!N.getValue(1).use_empty()) {
1735       SDValue Result;
1736       if (HiReg == X86::AH && Subtarget->is64Bit()) {
1737         // Prevent use of AH in a REX instruction by referencing AX instead.
1738         // Shift it down 8 bits.
1739         Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1740                                         X86::AX, MVT::i16, InFlag);
1741         InFlag = Result.getValue(2);
1742         Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16,
1743                                                Result,
1744                                    CurDAG->getTargetConstant(8, MVT::i8)), 0);
1745         // Then truncate it down to i8.
1746         SDValue SRIdx = CurDAG->getTargetConstant(X86::SUBREG_8BIT, MVT::i32);
1747         Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl,
1748                                                  MVT::i8, Result, SRIdx), 0);
1749       } else {
1750         Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1751                                         HiReg, NVT, InFlag);
1752         InFlag = Result.getValue(2);
1753       }
1754       ReplaceUses(N.getValue(1), Result);
1755 #ifndef NDEBUG
1756       DEBUG({
1757           errs() << std::string(Indent-2, ' ') << "=> ";
1758           Result.getNode()->dump(CurDAG);
1759           errs() << '\n';
1760         });
1761 #endif
1762     }
1763
1764 #ifndef NDEBUG
1765     Indent -= 2;
1766 #endif
1767
1768     return NULL;
1769   }
1770
1771   case ISD::SDIVREM:
1772   case ISD::UDIVREM: {
1773     SDValue N0 = Node->getOperand(0);
1774     SDValue N1 = Node->getOperand(1);
1775
1776     bool isSigned = Opcode == ISD::SDIVREM;
1777     if (!isSigned) {
1778       switch (NVT.getSimpleVT().SimpleTy) {
1779       default: llvm_unreachable("Unsupported VT!");
1780       case MVT::i8:  Opc = X86::DIV8r;  MOpc = X86::DIV8m;  break;
1781       case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
1782       case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
1783       case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
1784       }
1785     } else {
1786       switch (NVT.getSimpleVT().SimpleTy) {
1787       default: llvm_unreachable("Unsupported VT!");
1788       case MVT::i8:  Opc = X86::IDIV8r;  MOpc = X86::IDIV8m;  break;
1789       case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
1790       case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
1791       case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
1792       }
1793     }
1794
1795     unsigned LoReg, HiReg;
1796     unsigned ClrOpcode, SExtOpcode;
1797     switch (NVT.getSimpleVT().SimpleTy) {
1798     default: llvm_unreachable("Unsupported VT!");
1799     case MVT::i8:
1800       LoReg = X86::AL;  HiReg = X86::AH;
1801       ClrOpcode  = 0;
1802       SExtOpcode = X86::CBW;
1803       break;
1804     case MVT::i16:
1805       LoReg = X86::AX;  HiReg = X86::DX;
1806       ClrOpcode  = X86::MOV16r0;
1807       SExtOpcode = X86::CWD;
1808       break;
1809     case MVT::i32:
1810       LoReg = X86::EAX; HiReg = X86::EDX;
1811       ClrOpcode  = X86::MOV32r0;
1812       SExtOpcode = X86::CDQ;
1813       break;
1814     case MVT::i64:
1815       LoReg = X86::RAX; HiReg = X86::RDX;
1816       ClrOpcode  = ~0U; // NOT USED.
1817       SExtOpcode = X86::CQO;
1818       break;
1819     }
1820
1821     SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1822     bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
1823     bool signBitIsZero = CurDAG->SignBitIsZero(N0);
1824
1825     SDValue InFlag;
1826     if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
1827       // Special case for div8, just use a move with zero extension to AX to
1828       // clear the upper 8 bits (AH).
1829       SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
1830       if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
1831         SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
1832         Move =
1833           SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, dl, MVT::i16,
1834                                         MVT::Other, Ops,
1835                                         array_lengthof(Ops)), 0);
1836         Chain = Move.getValue(1);
1837         ReplaceUses(N0.getValue(1), Chain);
1838       } else {
1839         Move =
1840           SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, dl, MVT::i16, N0),0);
1841         Chain = CurDAG->getEntryNode();
1842       }
1843       Chain  = CurDAG->getCopyToReg(Chain, dl, X86::AX, Move, SDValue());
1844       InFlag = Chain.getValue(1);
1845     } else {
1846       InFlag =
1847         CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
1848                              LoReg, N0, SDValue()).getValue(1);
1849       if (isSigned && !signBitIsZero) {
1850         // Sign extend the low part into the high part.
1851         InFlag =
1852           SDValue(CurDAG->getTargetNode(SExtOpcode, dl, MVT::Flag, InFlag),0);
1853       } else {
1854         // Zero out the high part, effectively zero extending the input.
1855         SDValue ClrNode;
1856
1857         if (NVT.getSimpleVT() == MVT::i64) {
1858           ClrNode = SDValue(CurDAG->getTargetNode(X86::MOV32r0, dl, MVT::i32),
1859                             0);
1860           // We just did a 32-bit clear, insert it into a 64-bit register to
1861           // clear the whole 64-bit reg.
1862           SDValue Undef =
1863             SDValue(CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF,
1864                                           dl, MVT::i64), 0);
1865           SDValue SubRegNo =
1866             CurDAG->getTargetConstant(X86::SUBREG_32BIT, MVT::i32);
1867           ClrNode =
1868             SDValue(CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl,
1869                                           MVT::i64, Undef, ClrNode, SubRegNo),
1870                     0);
1871         } else {
1872           ClrNode = SDValue(CurDAG->getTargetNode(ClrOpcode, dl, NVT), 0);
1873         }
1874
1875         InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, HiReg,
1876                                       ClrNode, InFlag).getValue(1);
1877       }
1878     }
1879
1880     if (foldedLoad) {
1881       SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
1882                         InFlag };
1883       SDNode *CNode =
1884         CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
1885                               array_lengthof(Ops));
1886       InFlag = SDValue(CNode, 1);
1887       // Update the chain.
1888       ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
1889     } else {
1890       InFlag =
1891         SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
1892     }
1893
1894     // Copy the division (low) result, if it is needed.
1895     if (!N.getValue(0).use_empty()) {
1896       SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1897                                                 LoReg, NVT, InFlag);
1898       InFlag = Result.getValue(2);
1899       ReplaceUses(N.getValue(0), Result);
1900 #ifndef NDEBUG
1901       DEBUG({
1902           errs() << std::string(Indent-2, ' ') << "=> ";
1903           Result.getNode()->dump(CurDAG);
1904           errs() << '\n';
1905         });
1906 #endif
1907     }
1908     // Copy the remainder (high) result, if it is needed.
1909     if (!N.getValue(1).use_empty()) {
1910       SDValue Result;
1911       if (HiReg == X86::AH && Subtarget->is64Bit()) {
1912         // Prevent use of AH in a REX instruction by referencing AX instead.
1913         // Shift it down 8 bits.
1914         Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1915                                         X86::AX, MVT::i16, InFlag);
1916         InFlag = Result.getValue(2);
1917         Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16,
1918                                       Result,
1919                                       CurDAG->getTargetConstant(8, MVT::i8)),
1920                          0);
1921         // Then truncate it down to i8.
1922         SDValue SRIdx = CurDAG->getTargetConstant(X86::SUBREG_8BIT, MVT::i32);
1923         Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl,
1924                                                  MVT::i8, Result, SRIdx), 0);
1925       } else {
1926         Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1927                                         HiReg, NVT, InFlag);
1928         InFlag = Result.getValue(2);
1929       }
1930       ReplaceUses(N.getValue(1), Result);
1931 #ifndef NDEBUG
1932       DEBUG({
1933           errs() << std::string(Indent-2, ' ') << "=> ";
1934           Result.getNode()->dump(CurDAG);
1935           errs() << '\n';
1936         });
1937 #endif
1938     }
1939
1940 #ifndef NDEBUG
1941     Indent -= 2;
1942 #endif
1943
1944     return NULL;
1945   }
1946
1947   case ISD::DECLARE: {
1948     // Handle DECLARE nodes here because the second operand may have been
1949     // wrapped in X86ISD::Wrapper.
1950     SDValue Chain = Node->getOperand(0);
1951     SDValue N1 = Node->getOperand(1);
1952     SDValue N2 = Node->getOperand(2);
1953     FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N1);
1954
1955     // FIXME: We need to handle this for VLAs.
1956     if (!FINode) {
1957       ReplaceUses(N.getValue(0), Chain);
1958       return NULL;
1959     }
1960
1961     if (N2.getOpcode() == ISD::ADD &&
1962         N2.getOperand(0).getOpcode() == X86ISD::GlobalBaseReg)
1963       N2 = N2.getOperand(1);
1964
1965     // If N2 is not Wrapper(decriptor) then the llvm.declare is mangled
1966     // somehow, just ignore it.
1967     if (N2.getOpcode() != X86ISD::Wrapper &&
1968         N2.getOpcode() != X86ISD::WrapperRIP) {
1969       ReplaceUses(N.getValue(0), Chain);
1970       return NULL;
1971     }
1972     GlobalAddressSDNode *GVNode =
1973       dyn_cast<GlobalAddressSDNode>(N2.getOperand(0));
1974     if (GVNode == 0) {
1975       ReplaceUses(N.getValue(0), Chain);
1976       return NULL;
1977     }
1978     SDValue Tmp1 = CurDAG->getTargetFrameIndex(FINode->getIndex(),
1979                                                TLI.getPointerTy());
1980     SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GVNode->getGlobal(),
1981                                                   TLI.getPointerTy());
1982     SDValue Ops[] = { Tmp1, Tmp2, Chain };
1983     return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl,
1984                                  MVT::Other, Ops,
1985                                  array_lengthof(Ops));
1986   }
1987   }
1988
1989   SDNode *ResNode = SelectCode(N);
1990
1991 #ifndef NDEBUG
1992   DEBUG({
1993       errs() << std::string(Indent-2, ' ') << "=> ";
1994       if (ResNode == NULL || ResNode == N.getNode())
1995         N.getNode()->dump(CurDAG);
1996       else
1997         ResNode->dump(CurDAG);
1998       errs() << '\n';
1999     });
2000   Indent -= 2;
2001 #endif
2002
2003   return ResNode;
2004 }
2005
2006 bool X86DAGToDAGISel::
2007 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2008                              std::vector<SDValue> &OutOps) {
2009   SDValue Op0, Op1, Op2, Op3, Op4;
2010   switch (ConstraintCode) {
2011   case 'o':   // offsetable        ??
2012   case 'v':   // not offsetable    ??
2013   default: return true;
2014   case 'm':   // memory
2015     if (!SelectAddr(Op, Op, Op0, Op1, Op2, Op3, Op4))
2016       return true;
2017     break;
2018   }
2019
2020   OutOps.push_back(Op0);
2021   OutOps.push_back(Op1);
2022   OutOps.push_back(Op2);
2023   OutOps.push_back(Op3);
2024   OutOps.push_back(Op4);
2025   return false;
2026 }
2027
2028 /// createX86ISelDag - This pass converts a legalized DAG into a
2029 /// X86-specific DAG, ready for instruction scheduling.
2030 ///
2031 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
2032                                      llvm::CodeGenOpt::Level OptLevel) {
2033   return new X86DAGToDAGISel(TM, OptLevel);
2034 }