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Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
[llvm/avr.git] / lib / Target / X86 / X86FloatingPoint.cpp
blob91a0a2a626f3ac5d44c97b10c0ebd8e088e7f7a0
1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the pass which converts floating point instructions from
11 // virtual registers into register stack instructions. This pass uses live
12 // variable information to indicate where the FPn registers are used and their
13 // lifetimes.
14 //
15 // This pass is hampered by the lack of decent CFG manipulation routines for
16 // machine code. In particular, this wants to be able to split critical edges
17 // as necessary, traverse the machine basic block CFG in depth-first order, and
18 // allow there to be multiple machine basic blocks for each LLVM basicblock
19 // (needed for critical edge splitting).
20 //
21 // In particular, this pass currently barfs on critical edges. Because of this,
22 // it requires the instruction selector to insert FP_REG_KILL instructions on
23 // the exits of any basic block that has critical edges going from it, or which
24 // branch to a critical basic block.
25 //
26 // FIXME: this is not implemented yet. The stackifier pass only works on local
27 // basic blocks.
28 //
29 //===----------------------------------------------------------------------===//
30
31 #define DEBUG_TYPE "x86-codegen"
32 #include "X86.h"
33 #include "X86InstrInfo.h"
34 #include "llvm/ADT/DepthFirstIterator.h"
35 #include "llvm/ADT/SmallPtrSet.h"
36 #include "llvm/ADT/SmallVector.h"
37 #include "llvm/ADT/Statistic.h"
38 #include "llvm/ADT/STLExtras.h"
39 #include "llvm/CodeGen/MachineFunctionPass.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineRegisterInfo.h"
42 #include "llvm/CodeGen/Passes.h"
43 #include "llvm/Support/Compiler.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Support/raw_ostream.h"
47 #include "llvm/Target/TargetInstrInfo.h"
48 #include "llvm/Target/TargetMachine.h"
49 #include <algorithm>
50 using namespace llvm;
51
52 STATISTIC(NumFXCH, "Number of fxch instructions inserted");
53 STATISTIC(NumFP , "Number of floating point instructions");
54
55 namespace {
56 struct VISIBILITY_HIDDEN FPS : public MachineFunctionPass {
57 static char ID;
58 FPS() : MachineFunctionPass(&ID) {}
59
60 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.setPreservesCFG();
62 AU.addPreservedID(MachineLoopInfoID);
63 AU.addPreservedID(MachineDominatorsID);
64 MachineFunctionPass::getAnalysisUsage(AU);
65 }
66
67 virtual bool runOnMachineFunction(MachineFunction &MF);
68
69 virtual const char *getPassName() const { return "X86 FP Stackifier"; }
70
71 private:
72 const TargetInstrInfo *TII; // Machine instruction info.
73 MachineBasicBlock *MBB; // Current basic block
74 unsigned Stack[8]; // FP<n> Registers in each stack slot...
75 unsigned RegMap[8]; // Track which stack slot contains each register
76 unsigned StackTop; // The current top of the FP stack.
77
78 void dumpStack() const {
79 cerr << "Stack contents:";
80 for (unsigned i = 0; i != StackTop; ++i) {
81 cerr << " FP" << Stack[i];
82 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
83 }
84 cerr << "\n";
85 }
86 private:
87 /// isStackEmpty - Return true if the FP stack is empty.
88 bool isStackEmpty() const {
89 return StackTop == 0;
90 }
91
92 // getSlot - Return the stack slot number a particular register number is
93 // in.
94 unsigned getSlot(unsigned RegNo) const {
95 assert(RegNo < 8 && "Regno out of range!");
96 return RegMap[RegNo];
97 }
98
99 // getStackEntry - Return the X86::FP<n> register in register ST(i).
100 unsigned getStackEntry(unsigned STi) const {
101 assert(STi < StackTop && "Access past stack top!");
102 return Stack[StackTop-1-STi];
103 }
104
105 // getSTReg - Return the X86::ST(i) register which contains the specified
106 // FP<RegNo> register.
107 unsigned getSTReg(unsigned RegNo) const {
108 return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0;
109 }
110
111 // pushReg - Push the specified FP<n> register onto the stack.
112 void pushReg(unsigned Reg) {
113 assert(Reg < 8 && "Register number out of range!");
114 assert(StackTop < 8 && "Stack overflow!");
115 Stack[StackTop] = Reg;
116 RegMap[Reg] = StackTop++;
117 }
118
119 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
120 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) {
121 MachineInstr *MI = I;
122 DebugLoc dl = MI->getDebugLoc();
123 if (isAtTop(RegNo)) return;
124
125 unsigned STReg = getSTReg(RegNo);
126 unsigned RegOnTop = getStackEntry(0);
127
128 // Swap the slots the regs are in.
129 std::swap(RegMap[RegNo], RegMap[RegOnTop]);
130
131 // Swap stack slot contents.
132 assert(RegMap[RegOnTop] < StackTop);
133 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
134
135 // Emit an fxch to update the runtime processors version of the state.
136 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
137 NumFXCH++;
138 }
139
140 void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
141 DebugLoc dl = I->getDebugLoc();
142 unsigned STReg = getSTReg(RegNo);
143 pushReg(AsReg); // New register on top of stack
144
145 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
146 }
147
148 // popStackAfter - Pop the current value off of the top of the FP stack
149 // after the specified instruction.
150 void popStackAfter(MachineBasicBlock::iterator &I);
151
152 // freeStackSlotAfter - Free the specified register from the register stack,
153 // so that it is no longer in a register. If the register is currently at
154 // the top of the stack, we just pop the current instruction, otherwise we
155 // store the current top-of-stack into the specified slot, then pop the top
156 // of stack.
157 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
158
159 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
160
161 void handleZeroArgFP(MachineBasicBlock::iterator &I);
162 void handleOneArgFP(MachineBasicBlock::iterator &I);
163 void handleOneArgFPRW(MachineBasicBlock::iterator &I);
164 void handleTwoArgFP(MachineBasicBlock::iterator &I);
165 void handleCompareFP(MachineBasicBlock::iterator &I);
166 void handleCondMovFP(MachineBasicBlock::iterator &I);
167 void handleSpecialFP(MachineBasicBlock::iterator &I);
168 };
169 char FPS::ID = 0;
170 }
171
172 FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
173
174 /// getFPReg - Return the X86::FPx register number for the specified operand.
175 /// For example, this returns 3 for X86::FP3.
176 static unsigned getFPReg(const MachineOperand &MO) {
177 assert(MO.isReg() && "Expected an FP register!");
178 unsigned Reg = MO.getReg();
179 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
180 return Reg - X86::FP0;
181 }
182
183
184 /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
185 /// register references into FP stack references.
186 ///
187 bool FPS::runOnMachineFunction(MachineFunction &MF) {
188 // We only need to run this pass if there are any FP registers used in this
189 // function. If it is all integer, there is nothing for us to do!
190 bool FPIsUsed = false;
191
192 assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!");
193 for (unsigned i = 0; i <= 6; ++i)
194 if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) {
195 FPIsUsed = true;
196 break;
197 }
198
199 // Early exit.
200 if (!FPIsUsed) return false;
201
202 TII = MF.getTarget().getInstrInfo();
203 StackTop = 0;
204
205 // Process the function in depth first order so that we process at least one
206 // of the predecessors for every reachable block in the function.
207 SmallPtrSet<MachineBasicBlock*, 8> Processed;
208 MachineBasicBlock *Entry = MF.begin();
209
210 bool Changed = false;
211 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*, 8> >
212 I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed);
213 I != E; ++I)
214 Changed |= processBasicBlock(MF, **I);
215
216 return Changed;
217 }
218
219 /// processBasicBlock - Loop over all of the instructions in the basic block,
220 /// transforming FP instructions into their stack form.
221 ///
222 bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
223 bool Changed = false;
224 MBB = &BB;
225
226 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
227 MachineInstr *MI = I;
228 unsigned Flags = MI->getDesc().TSFlags;
229
230 unsigned FPInstClass = Flags & X86II::FPTypeMask;
231 if (MI->getOpcode() == TargetInstrInfo::INLINEASM)
232 FPInstClass = X86II::SpecialFP;
233
234 if (FPInstClass == X86II::NotFP)
235 continue; // Efficiently ignore non-fp insts!
236
237 MachineInstr *PrevMI = 0;
238 if (I != BB.begin())
239 PrevMI = prior(I);
240
241 ++NumFP; // Keep track of # of pseudo instrs
242 DEBUG(errs() << "\nFPInst:\t" << *MI);
243
244 // Get dead variables list now because the MI pointer may be deleted as part
245 // of processing!
246 SmallVector<unsigned, 8> DeadRegs;
247 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
248 const MachineOperand &MO = MI->getOperand(i);
249 if (MO.isReg() && MO.isDead())
250 DeadRegs.push_back(MO.getReg());
251 }
252
253 switch (FPInstClass) {
254 case X86II::ZeroArgFP: handleZeroArgFP(I); break;
255 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0)
256 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
257 case X86II::TwoArgFP: handleTwoArgFP(I); break;
258 case X86II::CompareFP: handleCompareFP(I); break;
259 case X86II::CondMovFP: handleCondMovFP(I); break;
260 case X86II::SpecialFP: handleSpecialFP(I); break;
261 default: llvm_unreachable("Unknown FP Type!");
262 }
263
264 // Check to see if any of the values defined by this instruction are dead
265 // after definition. If so, pop them.
266 for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
267 unsigned Reg = DeadRegs[i];
268 if (Reg >= X86::FP0 && Reg <= X86::FP6) {
269 DEBUG(errs() << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
270 freeStackSlotAfter(I, Reg-X86::FP0);
271 }
272 }
273
274 // Print out all of the instructions expanded to if -debug
275 DEBUG(
276 MachineBasicBlock::iterator PrevI(PrevMI);
277 if (I == PrevI) {
278 cerr << "Just deleted pseudo instruction\n";
279 } else {
280 MachineBasicBlock::iterator Start = I;
281 // Rewind to first instruction newly inserted.
282 while (Start != BB.begin() && prior(Start) != PrevI) --Start;
283 cerr << "Inserted instructions:\n\t";
284 Start->print(*cerr.stream(), &MF.getTarget());
285 while (++Start != next(I)) {}
286 }
287 dumpStack();
288 );
289
290 Changed = true;
291 }
292
293 assert(isStackEmpty() && "Stack not empty at end of basic block?");
294 return Changed;
295 }
296
297 //===----------------------------------------------------------------------===//
298 // Efficient Lookup Table Support
299 //===----------------------------------------------------------------------===//
300
301 namespace {
302 struct TableEntry {
303 unsigned from;
304 unsigned to;
305 bool operator<(const TableEntry &TE) const { return from < TE.from; }
306 friend bool operator<(const TableEntry &TE, unsigned V) {
307 return TE.from < V;
308 }
309 friend bool operator<(unsigned V, const TableEntry &TE) {
310 return V < TE.from;
311 }
312 };
313 }
314
315 #ifndef NDEBUG
316 static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
317 for (unsigned i = 0; i != NumEntries-1; ++i)
318 if (!(Table[i] < Table[i+1])) return false;
319 return true;
320 }
321 #endif
322
323 static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
324 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
325 if (I != Table+N && I->from == Opcode)
326 return I->to;
327 return -1;
328 }
329
330 #ifdef NDEBUG
331 #define ASSERT_SORTED(TABLE)
332 #else
333 #define ASSERT_SORTED(TABLE) \
334 { static bool TABLE##Checked = false; \
335 if (!TABLE##Checked) { \
336 assert(TableIsSorted(TABLE, array_lengthof(TABLE)) && \
337 "All lookup tables must be sorted for efficient access!"); \
338 TABLE##Checked = true; \
339 } \
340 }
341 #endif
342
343 //===----------------------------------------------------------------------===//
344 // Register File -> Register Stack Mapping Methods
345 //===----------------------------------------------------------------------===//
346
347 // OpcodeTable - Sorted map of register instructions to their stack version.
348 // The first element is an register file pseudo instruction, the second is the
349 // concrete X86 instruction which uses the register stack.
350 //
351 static const TableEntry OpcodeTable[] = {
352 { X86::ABS_Fp32 , X86::ABS_F },
353 { X86::ABS_Fp64 , X86::ABS_F },
354 { X86::ABS_Fp80 , X86::ABS_F },
355 { X86::ADD_Fp32m , X86::ADD_F32m },
356 { X86::ADD_Fp64m , X86::ADD_F64m },
357 { X86::ADD_Fp64m32 , X86::ADD_F32m },
358 { X86::ADD_Fp80m32 , X86::ADD_F32m },
359 { X86::ADD_Fp80m64 , X86::ADD_F64m },
360 { X86::ADD_FpI16m32 , X86::ADD_FI16m },
361 { X86::ADD_FpI16m64 , X86::ADD_FI16m },
362 { X86::ADD_FpI16m80 , X86::ADD_FI16m },
363 { X86::ADD_FpI32m32 , X86::ADD_FI32m },
364 { X86::ADD_FpI32m64 , X86::ADD_FI32m },
365 { X86::ADD_FpI32m80 , X86::ADD_FI32m },
366 { X86::CHS_Fp32 , X86::CHS_F },
367 { X86::CHS_Fp64 , X86::CHS_F },
368 { X86::CHS_Fp80 , X86::CHS_F },
369 { X86::CMOVBE_Fp32 , X86::CMOVBE_F },
370 { X86::CMOVBE_Fp64 , X86::CMOVBE_F },
371 { X86::CMOVBE_Fp80 , X86::CMOVBE_F },
372 { X86::CMOVB_Fp32 , X86::CMOVB_F },
373 { X86::CMOVB_Fp64 , X86::CMOVB_F },
374 { X86::CMOVB_Fp80 , X86::CMOVB_F },
375 { X86::CMOVE_Fp32 , X86::CMOVE_F },
376 { X86::CMOVE_Fp64 , X86::CMOVE_F },
377 { X86::CMOVE_Fp80 , X86::CMOVE_F },
378 { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F },
379 { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F },
380 { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F },
381 { X86::CMOVNB_Fp32 , X86::CMOVNB_F },
382 { X86::CMOVNB_Fp64 , X86::CMOVNB_F },
383 { X86::CMOVNB_Fp80 , X86::CMOVNB_F },
384 { X86::CMOVNE_Fp32 , X86::CMOVNE_F },
385 { X86::CMOVNE_Fp64 , X86::CMOVNE_F },
386 { X86::CMOVNE_Fp80 , X86::CMOVNE_F },
387 { X86::CMOVNP_Fp32 , X86::CMOVNP_F },
388 { X86::CMOVNP_Fp64 , X86::CMOVNP_F },
389 { X86::CMOVNP_Fp80 , X86::CMOVNP_F },
390 { X86::CMOVP_Fp32 , X86::CMOVP_F },
391 { X86::CMOVP_Fp64 , X86::CMOVP_F },
392 { X86::CMOVP_Fp80 , X86::CMOVP_F },
393 { X86::COS_Fp32 , X86::COS_F },
394 { X86::COS_Fp64 , X86::COS_F },
395 { X86::COS_Fp80 , X86::COS_F },
396 { X86::DIVR_Fp32m , X86::DIVR_F32m },
397 { X86::DIVR_Fp64m , X86::DIVR_F64m },
398 { X86::DIVR_Fp64m32 , X86::DIVR_F32m },
399 { X86::DIVR_Fp80m32 , X86::DIVR_F32m },
400 { X86::DIVR_Fp80m64 , X86::DIVR_F64m },
401 { X86::DIVR_FpI16m32, X86::DIVR_FI16m},
402 { X86::DIVR_FpI16m64, X86::DIVR_FI16m},
403 { X86::DIVR_FpI16m80, X86::DIVR_FI16m},
404 { X86::DIVR_FpI32m32, X86::DIVR_FI32m},
405 { X86::DIVR_FpI32m64, X86::DIVR_FI32m},
406 { X86::DIVR_FpI32m80, X86::DIVR_FI32m},
407 { X86::DIV_Fp32m , X86::DIV_F32m },
408 { X86::DIV_Fp64m , X86::DIV_F64m },
409 { X86::DIV_Fp64m32 , X86::DIV_F32m },
410 { X86::DIV_Fp80m32 , X86::DIV_F32m },
411 { X86::DIV_Fp80m64 , X86::DIV_F64m },
412 { X86::DIV_FpI16m32 , X86::DIV_FI16m },
413 { X86::DIV_FpI16m64 , X86::DIV_FI16m },
414 { X86::DIV_FpI16m80 , X86::DIV_FI16m },
415 { X86::DIV_FpI32m32 , X86::DIV_FI32m },
416 { X86::DIV_FpI32m64 , X86::DIV_FI32m },
417 { X86::DIV_FpI32m80 , X86::DIV_FI32m },
418 { X86::ILD_Fp16m32 , X86::ILD_F16m },
419 { X86::ILD_Fp16m64 , X86::ILD_F16m },
420 { X86::ILD_Fp16m80 , X86::ILD_F16m },
421 { X86::ILD_Fp32m32 , X86::ILD_F32m },
422 { X86::ILD_Fp32m64 , X86::ILD_F32m },
423 { X86::ILD_Fp32m80 , X86::ILD_F32m },
424 { X86::ILD_Fp64m32 , X86::ILD_F64m },
425 { X86::ILD_Fp64m64 , X86::ILD_F64m },
426 { X86::ILD_Fp64m80 , X86::ILD_F64m },
427 { X86::ISTT_Fp16m32 , X86::ISTT_FP16m},
428 { X86::ISTT_Fp16m64 , X86::ISTT_FP16m},
429 { X86::ISTT_Fp16m80 , X86::ISTT_FP16m},
430 { X86::ISTT_Fp32m32 , X86::ISTT_FP32m},
431 { X86::ISTT_Fp32m64 , X86::ISTT_FP32m},
432 { X86::ISTT_Fp32m80 , X86::ISTT_FP32m},
433 { X86::ISTT_Fp64m32 , X86::ISTT_FP64m},
434 { X86::ISTT_Fp64m64 , X86::ISTT_FP64m},
435 { X86::ISTT_Fp64m80 , X86::ISTT_FP64m},
436 { X86::IST_Fp16m32 , X86::IST_F16m },
437 { X86::IST_Fp16m64 , X86::IST_F16m },
438 { X86::IST_Fp16m80 , X86::IST_F16m },
439 { X86::IST_Fp32m32 , X86::IST_F32m },
440 { X86::IST_Fp32m64 , X86::IST_F32m },
441 { X86::IST_Fp32m80 , X86::IST_F32m },
442 { X86::IST_Fp64m32 , X86::IST_FP64m },
443 { X86::IST_Fp64m64 , X86::IST_FP64m },
444 { X86::IST_Fp64m80 , X86::IST_FP64m },
445 { X86::LD_Fp032 , X86::LD_F0 },
446 { X86::LD_Fp064 , X86::LD_F0 },
447 { X86::LD_Fp080 , X86::LD_F0 },
448 { X86::LD_Fp132 , X86::LD_F1 },
449 { X86::LD_Fp164 , X86::LD_F1 },
450 { X86::LD_Fp180 , X86::LD_F1 },
451 { X86::LD_Fp32m , X86::LD_F32m },
452 { X86::LD_Fp32m64 , X86::LD_F32m },
453 { X86::LD_Fp32m80 , X86::LD_F32m },
454 { X86::LD_Fp64m , X86::LD_F64m },
455 { X86::LD_Fp64m80 , X86::LD_F64m },
456 { X86::LD_Fp80m , X86::LD_F80m },
457 { X86::MUL_Fp32m , X86::MUL_F32m },
458 { X86::MUL_Fp64m , X86::MUL_F64m },
459 { X86::MUL_Fp64m32 , X86::MUL_F32m },
460 { X86::MUL_Fp80m32 , X86::MUL_F32m },
461 { X86::MUL_Fp80m64 , X86::MUL_F64m },
462 { X86::MUL_FpI16m32 , X86::MUL_FI16m },
463 { X86::MUL_FpI16m64 , X86::MUL_FI16m },
464 { X86::MUL_FpI16m80 , X86::MUL_FI16m },
465 { X86::MUL_FpI32m32 , X86::MUL_FI32m },
466 { X86::MUL_FpI32m64 , X86::MUL_FI32m },
467 { X86::MUL_FpI32m80 , X86::MUL_FI32m },
468 { X86::SIN_Fp32 , X86::SIN_F },
469 { X86::SIN_Fp64 , X86::SIN_F },
470 { X86::SIN_Fp80 , X86::SIN_F },
471 { X86::SQRT_Fp32 , X86::SQRT_F },
472 { X86::SQRT_Fp64 , X86::SQRT_F },
473 { X86::SQRT_Fp80 , X86::SQRT_F },
474 { X86::ST_Fp32m , X86::ST_F32m },
475 { X86::ST_Fp64m , X86::ST_F64m },
476 { X86::ST_Fp64m32 , X86::ST_F32m },
477 { X86::ST_Fp80m32 , X86::ST_F32m },
478 { X86::ST_Fp80m64 , X86::ST_F64m },
479 { X86::ST_FpP80m , X86::ST_FP80m },
480 { X86::SUBR_Fp32m , X86::SUBR_F32m },
481 { X86::SUBR_Fp64m , X86::SUBR_F64m },
482 { X86::SUBR_Fp64m32 , X86::SUBR_F32m },
483 { X86::SUBR_Fp80m32 , X86::SUBR_F32m },
484 { X86::SUBR_Fp80m64 , X86::SUBR_F64m },
485 { X86::SUBR_FpI16m32, X86::SUBR_FI16m},
486 { X86::SUBR_FpI16m64, X86::SUBR_FI16m},
487 { X86::SUBR_FpI16m80, X86::SUBR_FI16m},
488 { X86::SUBR_FpI32m32, X86::SUBR_FI32m},
489 { X86::SUBR_FpI32m64, X86::SUBR_FI32m},
490 { X86::SUBR_FpI32m80, X86::SUBR_FI32m},
491 { X86::SUB_Fp32m , X86::SUB_F32m },
492 { X86::SUB_Fp64m , X86::SUB_F64m },
493 { X86::SUB_Fp64m32 , X86::SUB_F32m },
494 { X86::SUB_Fp80m32 , X86::SUB_F32m },
495 { X86::SUB_Fp80m64 , X86::SUB_F64m },
496 { X86::SUB_FpI16m32 , X86::SUB_FI16m },
497 { X86::SUB_FpI16m64 , X86::SUB_FI16m },
498 { X86::SUB_FpI16m80 , X86::SUB_FI16m },
499 { X86::SUB_FpI32m32 , X86::SUB_FI32m },
500 { X86::SUB_FpI32m64 , X86::SUB_FI32m },
501 { X86::SUB_FpI32m80 , X86::SUB_FI32m },
502 { X86::TST_Fp32 , X86::TST_F },
503 { X86::TST_Fp64 , X86::TST_F },
504 { X86::TST_Fp80 , X86::TST_F },
505 { X86::UCOM_FpIr32 , X86::UCOM_FIr },
506 { X86::UCOM_FpIr64 , X86::UCOM_FIr },
507 { X86::UCOM_FpIr80 , X86::UCOM_FIr },
508 { X86::UCOM_Fpr32 , X86::UCOM_Fr },
509 { X86::UCOM_Fpr64 , X86::UCOM_Fr },
510 { X86::UCOM_Fpr80 , X86::UCOM_Fr },
511 };
512
513 static unsigned getConcreteOpcode(unsigned Opcode) {
514 ASSERT_SORTED(OpcodeTable);
515 int Opc = Lookup(OpcodeTable, array_lengthof(OpcodeTable), Opcode);
516 assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
517 return Opc;
518 }
519
520 //===----------------------------------------------------------------------===//
521 // Helper Methods
522 //===----------------------------------------------------------------------===//
523
524 // PopTable - Sorted map of instructions to their popping version. The first
525 // element is an instruction, the second is the version which pops.
526 //
527 static const TableEntry PopTable[] = {
528 { X86::ADD_FrST0 , X86::ADD_FPrST0 },
529
530 { X86::DIVR_FrST0, X86::DIVR_FPrST0 },
531 { X86::DIV_FrST0 , X86::DIV_FPrST0 },
532
533 { X86::IST_F16m , X86::IST_FP16m },
534 { X86::IST_F32m , X86::IST_FP32m },
535
536 { X86::MUL_FrST0 , X86::MUL_FPrST0 },
537
538 { X86::ST_F32m , X86::ST_FP32m },
539 { X86::ST_F64m , X86::ST_FP64m },
540 { X86::ST_Frr , X86::ST_FPrr },
541
542 { X86::SUBR_FrST0, X86::SUBR_FPrST0 },
543 { X86::SUB_FrST0 , X86::SUB_FPrST0 },
544
545 { X86::UCOM_FIr , X86::UCOM_FIPr },
546
547 { X86::UCOM_FPr , X86::UCOM_FPPr },
548 { X86::UCOM_Fr , X86::UCOM_FPr },
549 };
550
551 /// popStackAfter - Pop the current value off of the top of the FP stack after
552 /// the specified instruction. This attempts to be sneaky and combine the pop
553 /// into the instruction itself if possible. The iterator is left pointing to
554 /// the last instruction, be it a new pop instruction inserted, or the old
555 /// instruction if it was modified in place.
556 ///
557 void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
558 MachineInstr* MI = I;
559 DebugLoc dl = MI->getDebugLoc();
560 ASSERT_SORTED(PopTable);
561 assert(StackTop > 0 && "Cannot pop empty stack!");
562 RegMap[Stack[--StackTop]] = ~0; // Update state
563
564 // Check to see if there is a popping version of this instruction...
565 int Opcode = Lookup(PopTable, array_lengthof(PopTable), I->getOpcode());
566 if (Opcode != -1) {
567 I->setDesc(TII->get(Opcode));
568 if (Opcode == X86::UCOM_FPPr)
569 I->RemoveOperand(0);
570 } else { // Insert an explicit pop
571 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
572 }
573 }
574
575 /// freeStackSlotAfter - Free the specified register from the register stack, so
576 /// that it is no longer in a register. If the register is currently at the top
577 /// of the stack, we just pop the current instruction, otherwise we store the
578 /// current top-of-stack into the specified slot, then pop the top of stack.
579 void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
580 if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy.
581 popStackAfter(I);
582 return;
583 }
584
585 // Otherwise, store the top of stack into the dead slot, killing the operand
586 // without having to add in an explicit xchg then pop.
587 //
588 unsigned STReg = getSTReg(FPRegNo);
589 unsigned OldSlot = getSlot(FPRegNo);
590 unsigned TopReg = Stack[StackTop-1];
591 Stack[OldSlot] = TopReg;
592 RegMap[TopReg] = OldSlot;
593 RegMap[FPRegNo] = ~0;
594 Stack[--StackTop] = ~0;
595 MachineInstr *MI = I;
596 DebugLoc dl = MI->getDebugLoc();
597 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(STReg);
598 }
599
600
601 //===----------------------------------------------------------------------===//
602 // Instruction transformation implementation
603 //===----------------------------------------------------------------------===//
604
605 /// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
606 ///
607 void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
608 MachineInstr *MI = I;
609 unsigned DestReg = getFPReg(MI->getOperand(0));
610
611 // Change from the pseudo instruction to the concrete instruction.
612 MI->RemoveOperand(0); // Remove the explicit ST(0) operand
613 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
614
615 // Result gets pushed on the stack.
616 pushReg(DestReg);
617 }
618
619 /// handleOneArgFP - fst <mem>, ST(0)
620 ///
621 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
622 MachineInstr *MI = I;
623 unsigned NumOps = MI->getDesc().getNumOperands();
624 assert((NumOps == X86AddrNumOperands + 1 || NumOps == 1) &&
625 "Can only handle fst* & ftst instructions!");
626
627 // Is this the last use of the source register?
628 unsigned Reg = getFPReg(MI->getOperand(NumOps-1));
629 bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
630
631 // FISTP64m is strange because there isn't a non-popping versions.
632 // If we have one _and_ we don't want to pop the operand, duplicate the value
633 // on the stack instead of moving it. This ensure that popping the value is
634 // always ok.
635 // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m.
636 //
637 if (!KillsSrc &&
638 (MI->getOpcode() == X86::IST_Fp64m32 ||
639 MI->getOpcode() == X86::ISTT_Fp16m32 ||
640 MI->getOpcode() == X86::ISTT_Fp32m32 ||
641 MI->getOpcode() == X86::ISTT_Fp64m32 ||
642 MI->getOpcode() == X86::IST_Fp64m64 ||
643 MI->getOpcode() == X86::ISTT_Fp16m64 ||
644 MI->getOpcode() == X86::ISTT_Fp32m64 ||
645 MI->getOpcode() == X86::ISTT_Fp64m64 ||
646 MI->getOpcode() == X86::IST_Fp64m80 ||
647 MI->getOpcode() == X86::ISTT_Fp16m80 ||
648 MI->getOpcode() == X86::ISTT_Fp32m80 ||
649 MI->getOpcode() == X86::ISTT_Fp64m80 ||
650 MI->getOpcode() == X86::ST_FpP80m)) {
651 duplicateToTop(Reg, 7 /*temp register*/, I);
652 } else {
653 moveToTop(Reg, I); // Move to the top of the stack...
654 }
655
656 // Convert from the pseudo instruction to the concrete instruction.
657 MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand
658 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
659
660 if (MI->getOpcode() == X86::IST_FP64m ||
661 MI->getOpcode() == X86::ISTT_FP16m ||
662 MI->getOpcode() == X86::ISTT_FP32m ||
663 MI->getOpcode() == X86::ISTT_FP64m ||
664 MI->getOpcode() == X86::ST_FP80m) {
665 assert(StackTop > 0 && "Stack empty??");
666 --StackTop;
667 } else if (KillsSrc) { // Last use of operand?
668 popStackAfter(I);
669 }
670 }
671
672
673 /// handleOneArgFPRW: Handle instructions that read from the top of stack and
674 /// replace the value with a newly computed value. These instructions may have
675 /// non-fp operands after their FP operands.
676 ///
677 /// Examples:
678 /// R1 = fchs R2
679 /// R1 = fadd R2, [mem]
680 ///
681 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
682 MachineInstr *MI = I;
683 #ifndef NDEBUG
684 unsigned NumOps = MI->getDesc().getNumOperands();
685 assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
686 #endif
687
688 // Is this the last use of the source register?
689 unsigned Reg = getFPReg(MI->getOperand(1));
690 bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
691
692 if (KillsSrc) {
693 // If this is the last use of the source register, just make sure it's on
694 // the top of the stack.
695 moveToTop(Reg, I);
696 assert(StackTop > 0 && "Stack cannot be empty!");
697 --StackTop;
698 pushReg(getFPReg(MI->getOperand(0)));
699 } else {
700 // If this is not the last use of the source register, _copy_ it to the top
701 // of the stack.
702 duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I);
703 }
704
705 // Change from the pseudo instruction to the concrete instruction.
706 MI->RemoveOperand(1); // Drop the source operand.
707 MI->RemoveOperand(0); // Drop the destination operand.
708 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
709 }
710
711
712 //===----------------------------------------------------------------------===//
713 // Define tables of various ways to map pseudo instructions
714 //
715
716 // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i)
717 static const TableEntry ForwardST0Table[] = {
718 { X86::ADD_Fp32 , X86::ADD_FST0r },
719 { X86::ADD_Fp64 , X86::ADD_FST0r },
720 { X86::ADD_Fp80 , X86::ADD_FST0r },
721 { X86::DIV_Fp32 , X86::DIV_FST0r },
722 { X86::DIV_Fp64 , X86::DIV_FST0r },
723 { X86::DIV_Fp80 , X86::DIV_FST0r },
724 { X86::MUL_Fp32 , X86::MUL_FST0r },
725 { X86::MUL_Fp64 , X86::MUL_FST0r },
726 { X86::MUL_Fp80 , X86::MUL_FST0r },
727 { X86::SUB_Fp32 , X86::SUB_FST0r },
728 { X86::SUB_Fp64 , X86::SUB_FST0r },
729 { X86::SUB_Fp80 , X86::SUB_FST0r },
730 };
731
732 // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0)
733 static const TableEntry ReverseST0Table[] = {
734 { X86::ADD_Fp32 , X86::ADD_FST0r }, // commutative
735 { X86::ADD_Fp64 , X86::ADD_FST0r }, // commutative
736 { X86::ADD_Fp80 , X86::ADD_FST0r }, // commutative
737 { X86::DIV_Fp32 , X86::DIVR_FST0r },
738 { X86::DIV_Fp64 , X86::DIVR_FST0r },
739 { X86::DIV_Fp80 , X86::DIVR_FST0r },
740 { X86::MUL_Fp32 , X86::MUL_FST0r }, // commutative
741 { X86::MUL_Fp64 , X86::MUL_FST0r }, // commutative
742 { X86::MUL_Fp80 , X86::MUL_FST0r }, // commutative
743 { X86::SUB_Fp32 , X86::SUBR_FST0r },
744 { X86::SUB_Fp64 , X86::SUBR_FST0r },
745 { X86::SUB_Fp80 , X86::SUBR_FST0r },
746 };
747
748 // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i)
749 static const TableEntry ForwardSTiTable[] = {
750 { X86::ADD_Fp32 , X86::ADD_FrST0 }, // commutative
751 { X86::ADD_Fp64 , X86::ADD_FrST0 }, // commutative
752 { X86::ADD_Fp80 , X86::ADD_FrST0 }, // commutative
753 { X86::DIV_Fp32 , X86::DIVR_FrST0 },
754 { X86::DIV_Fp64 , X86::DIVR_FrST0 },
755 { X86::DIV_Fp80 , X86::DIVR_FrST0 },
756 { X86::MUL_Fp32 , X86::MUL_FrST0 }, // commutative
757 { X86::MUL_Fp64 , X86::MUL_FrST0 }, // commutative
758 { X86::MUL_Fp80 , X86::MUL_FrST0 }, // commutative
759 { X86::SUB_Fp32 , X86::SUBR_FrST0 },
760 { X86::SUB_Fp64 , X86::SUBR_FrST0 },
761 { X86::SUB_Fp80 , X86::SUBR_FrST0 },
762 };
763
764 // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0)
765 static const TableEntry ReverseSTiTable[] = {
766 { X86::ADD_Fp32 , X86::ADD_FrST0 },
767 { X86::ADD_Fp64 , X86::ADD_FrST0 },
768 { X86::ADD_Fp80 , X86::ADD_FrST0 },
769 { X86::DIV_Fp32 , X86::DIV_FrST0 },
770 { X86::DIV_Fp64 , X86::DIV_FrST0 },
771 { X86::DIV_Fp80 , X86::DIV_FrST0 },
772 { X86::MUL_Fp32 , X86::MUL_FrST0 },
773 { X86::MUL_Fp64 , X86::MUL_FrST0 },
774 { X86::MUL_Fp80 , X86::MUL_FrST0 },
775 { X86::SUB_Fp32 , X86::SUB_FrST0 },
776 { X86::SUB_Fp64 , X86::SUB_FrST0 },
777 { X86::SUB_Fp80 , X86::SUB_FrST0 },
778 };
779
780
781 /// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
782 /// instructions which need to be simplified and possibly transformed.
783 ///
784 /// Result: ST(0) = fsub ST(0), ST(i)
785 /// ST(i) = fsub ST(0), ST(i)
786 /// ST(0) = fsubr ST(0), ST(i)
787 /// ST(i) = fsubr ST(0), ST(i)
788 ///
789 void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
790 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
791 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
792 MachineInstr *MI = I;
793
794 unsigned NumOperands = MI->getDesc().getNumOperands();
795 assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
796 unsigned Dest = getFPReg(MI->getOperand(0));
797 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
798 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
799 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
800 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
801 DebugLoc dl = MI->getDebugLoc();
802
803 unsigned TOS = getStackEntry(0);
804
805 // One of our operands must be on the top of the stack. If neither is yet, we
806 // need to move one.
807 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS?
808 // We can choose to move either operand to the top of the stack. If one of
809 // the operands is killed by this instruction, we want that one so that we
810 // can update right on top of the old version.
811 if (KillsOp0) {
812 moveToTop(Op0, I); // Move dead operand to TOS.
813 TOS = Op0;
814 } else if (KillsOp1) {
815 moveToTop(Op1, I);
816 TOS = Op1;
817 } else {
818 // All of the operands are live after this instruction executes, so we
819 // cannot update on top of any operand. Because of this, we must
820 // duplicate one of the stack elements to the top. It doesn't matter
821 // which one we pick.
822 //
823 duplicateToTop(Op0, Dest, I);
824 Op0 = TOS = Dest;
825 KillsOp0 = true;
826 }
827 } else if (!KillsOp0 && !KillsOp1) {
828 // If we DO have one of our operands at the top of the stack, but we don't
829 // have a dead operand, we must duplicate one of the operands to a new slot
830 // on the stack.
831 duplicateToTop(Op0, Dest, I);
832 Op0 = TOS = Dest;
833 KillsOp0 = true;
834 }
835
836 // Now we know that one of our operands is on the top of the stack, and at
837 // least one of our operands is killed by this instruction.
838 assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
839 "Stack conditions not set up right!");
840
841 // We decide which form to use based on what is on the top of the stack, and
842 // which operand is killed by this instruction.
843 const TableEntry *InstTable;
844 bool isForward = TOS == Op0;
845 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
846 if (updateST0) {
847 if (isForward)
848 InstTable = ForwardST0Table;
849 else
850 InstTable = ReverseST0Table;
851 } else {
852 if (isForward)
853 InstTable = ForwardSTiTable;
854 else
855 InstTable = ReverseSTiTable;
856 }
857
858 int Opcode = Lookup(InstTable, array_lengthof(ForwardST0Table),
859 MI->getOpcode());
860 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
861
862 // NotTOS - The register which is not on the top of stack...
863 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
864
865 // Replace the old instruction with a new instruction
866 MBB->remove(I++);
867 I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS));
868
869 // If both operands are killed, pop one off of the stack in addition to
870 // overwriting the other one.
871 if (KillsOp0 && KillsOp1 && Op0 != Op1) {
872 assert(!updateST0 && "Should have updated other operand!");
873 popStackAfter(I); // Pop the top of stack
874 }
875
876 // Update stack information so that we know the destination register is now on
877 // the stack.
878 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
879 assert(UpdatedSlot < StackTop && Dest < 7);
880 Stack[UpdatedSlot] = Dest;
881 RegMap[Dest] = UpdatedSlot;
882 MBB->getParent()->DeleteMachineInstr(MI); // Remove the old instruction
883 }
884
885 /// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
886 /// register arguments and no explicit destinations.
887 ///
888 void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
889 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
890 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
891 MachineInstr *MI = I;
892
893 unsigned NumOperands = MI->getDesc().getNumOperands();
894 assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
895 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
896 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
897 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
898 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
899
900 // Make sure the first operand is on the top of stack, the other one can be
901 // anywhere.
902 moveToTop(Op0, I);
903
904 // Change from the pseudo instruction to the concrete instruction.
905 MI->getOperand(0).setReg(getSTReg(Op1));
906 MI->RemoveOperand(1);
907 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
908
909 // If any of the operands are killed by this instruction, free them.
910 if (KillsOp0) freeStackSlotAfter(I, Op0);
911 if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
912 }
913
914 /// handleCondMovFP - Handle two address conditional move instructions. These
915 /// instructions move a st(i) register to st(0) iff a condition is true. These
916 /// instructions require that the first operand is at the top of the stack, but
917 /// otherwise don't modify the stack at all.
918 void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
919 MachineInstr *MI = I;
920
921 unsigned Op0 = getFPReg(MI->getOperand(0));
922 unsigned Op1 = getFPReg(MI->getOperand(2));
923 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
924
925 // The first operand *must* be on the top of the stack.
926 moveToTop(Op0, I);
927
928 // Change the second operand to the stack register that the operand is in.
929 // Change from the pseudo instruction to the concrete instruction.
930 MI->RemoveOperand(0);
931 MI->RemoveOperand(1);
932 MI->getOperand(0).setReg(getSTReg(Op1));
933 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
934
935 // If we kill the second operand, make sure to pop it from the stack.
936 if (Op0 != Op1 && KillsOp1) {
937 // Get this value off of the register stack.
938 freeStackSlotAfter(I, Op1);
939 }
940 }
941
942
943 /// handleSpecialFP - Handle special instructions which behave unlike other
944 /// floating point instructions. This is primarily intended for use by pseudo
945 /// instructions.
946 ///
947 void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
948 MachineInstr *MI = I;
949 DebugLoc dl = MI->getDebugLoc();
950 switch (MI->getOpcode()) {
951 default: llvm_unreachable("Unknown SpecialFP instruction!");
952 case X86::FpGET_ST0_32:// Appears immediately after a call returning FP type!
953 case X86::FpGET_ST0_64:// Appears immediately after a call returning FP type!
954 case X86::FpGET_ST0_80:// Appears immediately after a call returning FP type!
955 assert(StackTop == 0 && "Stack should be empty after a call!");
956 pushReg(getFPReg(MI->getOperand(0)));
957 break;
958 case X86::FpGET_ST1_32:// Appears immediately after a call returning FP type!
959 case X86::FpGET_ST1_64:// Appears immediately after a call returning FP type!
960 case X86::FpGET_ST1_80:{// Appears immediately after a call returning FP type!
961 // FpGET_ST1 should occur right after a FpGET_ST0 for a call or inline asm.
962 // The pattern we expect is:
963 // CALL
964 // FP1 = FpGET_ST0
965 // FP4 = FpGET_ST1
966 //
967 // At this point, we've pushed FP1 on the top of stack, so it should be
968 // present if it isn't dead. If it was dead, we already emitted a pop to
969 // remove it from the stack and StackTop = 0.
970
971 // Push FP4 as top of stack next.
972 pushReg(getFPReg(MI->getOperand(0)));
973
974 // If StackTop was 0 before we pushed our operand, then ST(0) must have been
975 // dead. In this case, the ST(1) value is the only thing that is live, so
976 // it should be on the TOS (after the pop that was emitted) and is. Just
977 // continue in this case.
978 if (StackTop == 1)
979 break;
980
981 // Because pushReg just pushed ST(1) as TOS, we now have to swap the two top
982 // elements so that our accounting is correct.
983 unsigned RegOnTop = getStackEntry(0);
984 unsigned RegNo = getStackEntry(1);
985
986 // Swap the slots the regs are in.
987 std::swap(RegMap[RegNo], RegMap[RegOnTop]);
988
989 // Swap stack slot contents.
990 assert(RegMap[RegOnTop] < StackTop);
991 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
992 break;
993 }
994 case X86::FpSET_ST0_32:
995 case X86::FpSET_ST0_64:
996 case X86::FpSET_ST0_80: {
997 unsigned Op0 = getFPReg(MI->getOperand(0));
998
999 // FpSET_ST0_80 is generated by copyRegToReg for both function return
1000 // and inline assembly with the "st" constrain. In the latter case,
1001 // it is possible for ST(0) to be alive after this instruction.
1002 if (!MI->killsRegister(X86::FP0 + Op0)) {
1003 // Duplicate Op0
1004 duplicateToTop(0, 7 /*temp register*/, I);
1005 } else {
1006 moveToTop(Op0, I);
1007 }
1008 --StackTop; // "Forget" we have something on the top of stack!
1009 break;
1010 }
1011 case X86::FpSET_ST1_32:
1012 case X86::FpSET_ST1_64:
1013 case X86::FpSET_ST1_80:
1014 // StackTop can be 1 if a FpSET_ST0_* was before this. Exchange them.
1015 if (StackTop == 1) {
1016 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(X86::ST1);
1017 NumFXCH++;
1018 StackTop = 0;
1019 break;
1020 }
1021 assert(StackTop == 2 && "Stack should have two element on it to return!");
1022 --StackTop; // "Forget" we have something on the top of stack!
1023 break;
1024 case X86::MOV_Fp3232:
1025 case X86::MOV_Fp3264:
1026 case X86::MOV_Fp6432:
1027 case X86::MOV_Fp6464:
1028 case X86::MOV_Fp3280:
1029 case X86::MOV_Fp6480:
1030 case X86::MOV_Fp8032:
1031 case X86::MOV_Fp8064:
1032 case X86::MOV_Fp8080: {
1033 const MachineOperand &MO1 = MI->getOperand(1);
1034 unsigned SrcReg = getFPReg(MO1);
1035
1036 const MachineOperand &MO0 = MI->getOperand(0);
1037 // These can be created due to inline asm. Two address pass can introduce
1038 // copies from RFP registers to virtual registers.
1039 if (MO0.getReg() == X86::ST0 && SrcReg == 0) {
1040 assert(MO1.isKill());
1041 // Treat %ST0<def> = MOV_Fp8080 %FP0<kill>
1042 // like FpSET_ST0_80 %FP0<kill>, %ST0<imp-def>
1043 assert((StackTop == 1 || StackTop == 2)
1044 && "Stack should have one or two element on it to return!");
1045 --StackTop; // "Forget" we have something on the top of stack!
1046 break;
1047 } else if (MO0.getReg() == X86::ST1 && SrcReg == 1) {
1048 assert(MO1.isKill());
1049 // Treat %ST1<def> = MOV_Fp8080 %FP1<kill>
1050 // like FpSET_ST1_80 %FP0<kill>, %ST1<imp-def>
1051 // StackTop can be 1 if a FpSET_ST0_* was before this. Exchange them.
1052 if (StackTop == 1) {
1053 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(X86::ST1);
1054 NumFXCH++;
1055 StackTop = 0;
1056 break;
1057 }
1058 assert(StackTop == 2 && "Stack should have two element on it to return!");
1059 --StackTop; // "Forget" we have something on the top of stack!
1060 break;
1061 }
1062
1063 unsigned DestReg = getFPReg(MO0);
1064 if (MI->killsRegister(X86::FP0+SrcReg)) {
1065 // If the input operand is killed, we can just change the owner of the
1066 // incoming stack slot into the result.
1067 unsigned Slot = getSlot(SrcReg);
1068 assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!");
1069 Stack[Slot] = DestReg;
1070 RegMap[DestReg] = Slot;
1071
1072 } else {
1073 // For FMOV we just duplicate the specified value to a new stack slot.
1074 // This could be made better, but would require substantial changes.
1075 duplicateToTop(SrcReg, DestReg, I);
1076 }
1077 }
1078 break;
1079 case TargetInstrInfo::INLINEASM: {
1080 // The inline asm MachineInstr currently only *uses* FP registers for the
1081 // 'f' constraint. These should be turned into the current ST(x) register
1082 // in the machine instr. Also, any kills should be explicitly popped after
1083 // the inline asm.
1084 unsigned Kills[7];
1085 unsigned NumKills = 0;
1086 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1087 MachineOperand &Op = MI->getOperand(i);
1088 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1089 continue;
1090 assert(Op.isUse() && "Only handle inline asm uses right now");
1091
1092 unsigned FPReg = getFPReg(Op);
1093 Op.setReg(getSTReg(FPReg));
1094
1095 // If we kill this operand, make sure to pop it from the stack after the
1096 // asm. We just remember it for now, and pop them all off at the end in
1097 // a batch.
1098 if (Op.isKill())
1099 Kills[NumKills++] = FPReg;
1100 }
1101
1102 // If this asm kills any FP registers (is the last use of them) we must
1103 // explicitly emit pop instructions for them. Do this now after the asm has
1104 // executed so that the ST(x) numbers are not off (which would happen if we
1105 // did this inline with operand rewriting).
1106 //
1107 // Note: this might be a non-optimal pop sequence. We might be able to do
1108 // better by trying to pop in stack order or something.
1109 MachineBasicBlock::iterator InsertPt = MI;
1110 while (NumKills)
1111 freeStackSlotAfter(InsertPt, Kills[--NumKills]);
1112
1113 // Don't delete the inline asm!
1114 return;
1115 }
1116
1117 case X86::RET:
1118 case X86::RETI:
1119 // If RET has an FP register use operand, pass the first one in ST(0) and
1120 // the second one in ST(1).
1121 if (isStackEmpty()) return; // Quick check to see if any are possible.
1122
1123 // Find the register operands.
1124 unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U;
1125
1126 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1127 MachineOperand &Op = MI->getOperand(i);
1128 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1129 continue;
1130 // FP Register uses must be kills unless there are two uses of the same
1131 // register, in which case only one will be a kill.
1132 assert(Op.isUse() &&
1133 (Op.isKill() || // Marked kill.
1134 getFPReg(Op) == FirstFPRegOp || // Second instance.
1135 MI->killsRegister(Op.getReg())) && // Later use is marked kill.
1136 "Ret only defs operands, and values aren't live beyond it");
1137
1138 if (FirstFPRegOp == ~0U)
1139 FirstFPRegOp = getFPReg(Op);
1140 else {
1141 assert(SecondFPRegOp == ~0U && "More than two fp operands!");
1142 SecondFPRegOp = getFPReg(Op);
1143 }
1144
1145 // Remove the operand so that later passes don't see it.
1146 MI->RemoveOperand(i);
1147 --i, --e;
1148 }
1149
1150 // There are only four possibilities here:
1151 // 1) we are returning a single FP value. In this case, it has to be in
1152 // ST(0) already, so just declare success by removing the value from the
1153 // FP Stack.
1154 if (SecondFPRegOp == ~0U) {
1155 // Assert that the top of stack contains the right FP register.
1156 assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) &&
1157 "Top of stack not the right register for RET!");
1158
1159 // Ok, everything is good, mark the value as not being on the stack
1160 // anymore so that our assertion about the stack being empty at end of
1161 // block doesn't fire.
1162 StackTop = 0;
1163 return;
1164 }
1165
1166 // Otherwise, we are returning two values:
1167 // 2) If returning the same value for both, we only have one thing in the FP
1168 // stack. Consider: RET FP1, FP1
1169 if (StackTop == 1) {
1170 assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&&
1171 "Stack misconfiguration for RET!");
1172
1173 // Duplicate the TOS so that we return it twice. Just pick some other FPx
1174 // register to hold it.
1175 unsigned NewReg = (FirstFPRegOp+1)%7;
1176 duplicateToTop(FirstFPRegOp, NewReg, MI);
1177 FirstFPRegOp = NewReg;
1178 }
1179
1180 /// Okay we know we have two different FPx operands now:
1181 assert(StackTop == 2 && "Must have two values live!");
1182
1183 /// 3) If SecondFPRegOp is currently in ST(0) and FirstFPRegOp is currently
1184 /// in ST(1). In this case, emit an fxch.
1185 if (getStackEntry(0) == SecondFPRegOp) {
1186 assert(getStackEntry(1) == FirstFPRegOp && "Unknown regs live");
1187 moveToTop(FirstFPRegOp, MI);
1188 }
1189
1190 /// 4) Finally, FirstFPRegOp must be in ST(0) and SecondFPRegOp must be in
1191 /// ST(1). Just remove both from our understanding of the stack and return.
1192 assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live");
1193 assert(getStackEntry(1) == SecondFPRegOp && "Unknown regs live");
1194 StackTop = 0;
1195 return;
1196 }
1197
1198 I = MBB->erase(I); // Remove the pseudo instruction
1199 --I;
1200 }
AVR Backend for LLVM