lib/Target/MSP430/MSP430ISelLowering.cpp

   1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the MSP430TargetLowering class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #define DEBUG_TYPE "msp430-lower"
  15
  16 #include "MSP430ISelLowering.h"
  17 #include "MSP430.h"
  18 #include "MSP430TargetMachine.h"
  19 #include "MSP430Subtarget.h"
  20 #include "llvm/DerivedTypes.h"
  21 #include "llvm/Function.h"
  22 #include "llvm/Intrinsics.h"
  23 #include "llvm/CallingConv.h"
  24 #include "llvm/GlobalVariable.h"
  25 #include "llvm/GlobalAlias.h"
  26 #include "llvm/CodeGen/CallingConvLower.h"
  27 #include "llvm/CodeGen/MachineFrameInfo.h"
  28 #include "llvm/CodeGen/MachineFunction.h"
  29 #include "llvm/CodeGen/MachineInstrBuilder.h"
  30 #include "llvm/CodeGen/MachineRegisterInfo.h"
  31 #include "llvm/CodeGen/PseudoSourceValue.h"
  32 #include "llvm/CodeGen/SelectionDAGISel.h"
  33 #include "llvm/CodeGen/ValueTypes.h"
  34 #include "llvm/Support/Debug.h"
  35 #include "llvm/ADT/VectorExtras.h"
  36 using namespace llvm;
  37
  38 MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
  39   TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
  40
  41   // Set up the register classes.
  42   addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
  43
  44   // Compute derived properties from the register classes
  45   computeRegisterProperties();
  46
  47   // Provide all sorts of operation actions
  48
  49   // Division is expensive
  50   setIntDivIsCheap(false);
  51
  52   // Even if we have only 1 bit shift here, we can perform
  53   // shifts of the whole bitwidth 1 bit per step.
  54   setShiftAmountType(MVT::i8);
  55
  56   setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
  57   setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
  58   setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
  59   setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
  60   setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
  61
  62   setOperationAction(ISD::SRA, MVT::i16, Custom);
  63   setOperationAction(ISD::RET, MVT::Other, Custom);
  64 }
  65
  66 SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
  67   switch (Op.getOpcode()) {
  68   case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
  69   case ISD::SRA: return LowerShifts(Op, DAG);
  70   case ISD::RET: return LowerRET(Op, DAG);
  71   default:
  72     assert(0 && "unimplemented operand");
  73     return SDValue();
  74   }
  75 }
  76
  77 //===----------------------------------------------------------------------===//
  78 //                      Calling Convention Implementation
  79 //===----------------------------------------------------------------------===//
  80
  81 #include "MSP430GenCallingConv.inc"
  82
  83 SDValue MSP430TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
  84                                                     SelectionDAG &DAG) {
  85   unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
  86   switch (CC) {
  87   default:
  88     assert(0 && "Unsupported calling convention");
  89   case CallingConv::C:
  90   case CallingConv::Fast:
  91     return LowerCCCArguments(Op, DAG);
  92   }
  93 }
  94
  95 /// LowerCCCArguments - transform physical registers into virtual registers and
  96 /// generate load operations for arguments places on the stack.
  97 // FIXME: struct return stuff
  98 // FIXME: varargs
  99 SDValue MSP430TargetLowering::LowerCCCArguments(SDValue Op,
 100                                                 SelectionDAG &DAG) {
 101   MachineFunction &MF = DAG.getMachineFunction();
 102   MachineFrameInfo *MFI = MF.getFrameInfo();
 103   MachineRegisterInfo &RegInfo = MF.getRegInfo();
 104   SDValue Root = Op.getOperand(0);
 105   bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
 106   unsigned CC = MF.getFunction()->getCallingConv();
 107   DebugLoc dl = Op.getDebugLoc();
 108
 109   // Assign locations to all of the incoming arguments.
 110   SmallVector<CCValAssign, 16> ArgLocs;
 111   CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
 112   CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_MSP430);
 113
 114   assert(!isVarArg && "Varargs not supported yet");
 115
 116   SmallVector<SDValue, 16> ArgValues;
 117   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
 118     CCValAssign &VA = ArgLocs[i];
 119     if (VA.isRegLoc()) {
 120       // Arguments passed in registers
 121       MVT RegVT = VA.getLocVT();
 122       switch (RegVT.getSimpleVT()) {
 123       default:
 124         cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
 125              << RegVT.getSimpleVT()
 126              << "\n";
 127         abort();
 128       case MVT::i16:
 129         unsigned VReg =
 130           RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
 131         RegInfo.addLiveIn(VA.getLocReg(), VReg);
 132         SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);
 133
 134         // If this is an 8-bit value, it is really passed promoted to 16
 135         // bits. Insert an assert[sz]ext to capture this, then truncate to the
 136         // right size.
 137         if (VA.getLocInfo() == CCValAssign::SExt)
 138           ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
 139                                  DAG.getValueType(VA.getValVT()));
 140         else if (VA.getLocInfo() == CCValAssign::ZExt)
 141           ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
 142                                  DAG.getValueType(VA.getValVT()));
 143
 144         if (VA.getLocInfo() != CCValAssign::Full)
 145           ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
 146
 147         ArgValues.push_back(ArgValue);
 148       }
 149     } else {
 150       // Sanity check
 151       assert(VA.isMemLoc());
 152       // Load the argument to a virtual register
 153       unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
 154       if (ObjSize > 2) {
 155         cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
 156              << VA.getLocVT().getSimpleVT()
 157              << "\n";
 158       }
 159       // Create the frame index object for this incoming parameter...
 160       int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset());
 161
 162       // Create the SelectionDAG nodes corresponding to a load
 163       //from this parameter
 164       SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
 165       ArgValues.push_back(DAG.getLoad(VA.getLocVT(), dl, Root, FIN,
 166                                       PseudoSourceValue::getFixedStack(FI), 0));
 167     }
 168   }
 169
 170   ArgValues.push_back(Root);
 171
 172   // Return the new list of results.
 173   return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
 174                      &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
 175 }
 176
 177 SDValue MSP430TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
 178   // CCValAssign - represent the assignment of the return value to a location
 179   SmallVector<CCValAssign, 16> RVLocs;
 180   unsigned CC   = DAG.getMachineFunction().getFunction()->getCallingConv();
 181   bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
 182   DebugLoc dl = Op.getDebugLoc();
 183
 184   // CCState - Info about the registers and stack slot.
 185   CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
 186
 187   // Analize return values of ISD::RET
 188   CCInfo.AnalyzeReturn(Op.getNode(), RetCC_MSP430);
 189
 190   // If this is the first return lowered for this function, add the regs to the
 191   // liveout set for the function.
 192   if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
 193     for (unsigned i = 0; i != RVLocs.size(); ++i)
 194       if (RVLocs[i].isRegLoc())
 195         DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
 196   }
 197
 198   // The chain is always operand #0
 199   SDValue Chain = Op.getOperand(0);
 200   SDValue Flag;
 201
 202   // Copy the result values into the output registers.
 203   for (unsigned i = 0; i != RVLocs.size(); ++i) {
 204     CCValAssign &VA = RVLocs[i];
 205     assert(VA.isRegLoc() && "Can only return in registers!");
 206
 207     // ISD::RET => ret chain, (regnum1,val1), ...
 208     // So i*2+1 index only the regnums
 209     Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
 210                              Op.getOperand(i*2+1), Flag);
 211
 212     // Guarantee that all emitted copies are stuck together,
 213     // avoiding something bad.
 214     Flag = Chain.getValue(1);
 215   }
 216
 217   if (Flag.getNode())
 218     return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
 219
 220   // Return Void
 221   return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain);
 222 }
 223
 224 SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
 225                                           SelectionDAG &DAG) {
 226   assert(Op.getOpcode() == ISD::SRA && "Only SRA is currently supported.");
 227   SDNode* N = Op.getNode();
 228   MVT VT = Op.getValueType();
 229   DebugLoc dl = N->getDebugLoc();
 230
 231   // We currently only lower SRA of constant argument.
 232   if (!isa<ConstantSDNode>(N->getOperand(1)))
 233     return SDValue();
 234
 235   uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
 236
 237   // Expand the stuff into sequence of shifts.
 238   // FIXME: for some shift amounts this might be done better!
 239   // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
 240   SDValue Victim = N->getOperand(0);
 241   while (ShiftAmount--)
 242     Victim = DAG.getNode(MSP430ISD::RRA, dl, VT, Victim);
 243
 244   return Victim;
 245 }
 246
 247 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
 248   switch (Opcode) {
 249   default: return NULL;
 250   case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
 251   case MSP430ISD::RRA:                return "MSP430ISD::RRA";
 252   }
 253 }
 254