lib/Target/X86/X86CodeEmitter.cpp

   1 //===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the pass that transforms the X86 machine instructions into
  11 // relocatable machine code.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #define DEBUG_TYPE "x86-emitter"
  16 #include "X86InstrInfo.h"
  17 #include "X86JITInfo.h"
  18 #include "X86Subtarget.h"
  19 #include "X86TargetMachine.h"
  20 #include "X86Relocations.h"
  21 #include "X86.h"
  22 #include "llvm/PassManager.h"
  23 #include "llvm/CodeGen/MachineCodeEmitter.h"
  24 #include "llvm/CodeGen/MachineFunctionPass.h"
  25 #include "llvm/CodeGen/MachineInstr.h"
  26 #include "llvm/CodeGen/MachineModuleInfo.h"
  27 #include "llvm/CodeGen/Passes.h"
  28 #include "llvm/Function.h"
  29 #include "llvm/ADT/Statistic.h"
  30 #include "llvm/Support/Compiler.h"
  31 #include "llvm/Support/Debug.h"
  32 #include "llvm/Target/TargetOptions.h"
  33 using namespace llvm;
  34
  35 STATISTIC(NumEmitted, "Number of machine instructions emitted");
  36
  37 namespace {
  38   class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
  39     const X86InstrInfo  *II;
  40     const TargetData    *TD;
  41     X86TargetMachine    &TM;
  42     MachineCodeEmitter  &MCE;
  43     intptr_t PICBaseOffset;
  44     bool Is64BitMode;
  45     bool IsPIC;
  46   public:
  47     static char ID;
  48     explicit Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce)
  49       : MachineFunctionPass(&ID), II(0), TD(0), TM(tm),
  50       MCE(mce), PICBaseOffset(0), Is64BitMode(false),
  51       IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
  52     Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce,
  53             const X86InstrInfo &ii, const TargetData &td, bool is64)
  54       : MachineFunctionPass(&ID), II(&ii), TD(&td), TM(tm),
  55       MCE(mce), PICBaseOffset(0), Is64BitMode(is64),
  56       IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
  57
  58     bool runOnMachineFunction(MachineFunction &MF);
  59
  60     virtual const char *getPassName() const {
  61       return "X86 Machine Code Emitter";
  62     }
  63
  64     void emitInstruction(const MachineInstr &MI,
  65                          const TargetInstrDesc *Desc);
  66
  67     void getAnalysisUsage(AnalysisUsage &AU) const {
  68       AU.addRequired<MachineModuleInfo>();
  69       MachineFunctionPass::getAnalysisUsage(AU);
  70     }
  71
  72   private:
  73     void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
  74     void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
  75                            intptr_t Disp = 0, intptr_t PCAdj = 0,
  76                            bool NeedStub = false, bool Indirect = false);
  77     void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
  78     void emitConstPoolAddress(unsigned CPI, unsigned Reloc, intptr_t Disp = 0,
  79                               intptr_t PCAdj = 0);
  80     void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
  81                               intptr_t PCAdj = 0);
  82
  83     void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
  84                                intptr_t PCAdj = 0);
  85
  86     void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
  87     void emitRegModRMByte(unsigned RegOpcodeField);
  88     void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
  89     void emitConstant(uint64_t Val, unsigned Size);
  90
  91     void emitMemModRMByte(const MachineInstr &MI,
  92                           unsigned Op, unsigned RegOpcodeField,
  93                           intptr_t PCAdj = 0);
  94
  95     unsigned getX86RegNum(unsigned RegNo) const;
  96
  97     bool gvNeedsNonLazyPtr(const GlobalValue *GV);
  98   };
  99   char Emitter::ID = 0;
 100 }
 101
 102 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
 103 /// to the specified MCE object.
 104 FunctionPass *llvm::createX86CodeEmitterPass(X86TargetMachine &TM,
 105                                              MachineCodeEmitter &MCE) {
 106   return new Emitter(TM, MCE);
 107 }
 108
 109 bool Emitter::runOnMachineFunction(MachineFunction &MF) {
 110
 111   MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
 112
 113   II = TM.getInstrInfo();
 114   TD = TM.getTargetData();
 115   Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit();
 116   IsPIC = TM.getRelocationModel() == Reloc::PIC_;
 117
 118   do {
 119     DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
 120     MCE.startFunction(MF);
 121     for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
 122          MBB != E; ++MBB) {
 123       MCE.StartMachineBasicBlock(MBB);
 124       for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
 125            I != E; ++I) {
 126         const TargetInstrDesc &Desc = I->getDesc();
 127         emitInstruction(*I, &Desc);
 128         // MOVPC32r is basically a call plus a pop instruction.
 129         if (Desc.getOpcode() == X86::MOVPC32r)
 130           emitInstruction(*I, &II->get(X86::POP32r));
 131         NumEmitted++;  // Keep track of the # of mi's emitted
 132       }
 133     }
 134   } while (MCE.finishFunction(MF));
 135
 136   return false;
 137 }
 138
 139 /// emitPCRelativeBlockAddress - This method keeps track of the information
 140 /// necessary to resolve the address of this block later and emits a dummy
 141 /// value.
 142 ///
 143 void Emitter::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
 144   // Remember where this reference was and where it is to so we can
 145   // deal with it later.
 146   MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
 147                                              X86::reloc_pcrel_word, MBB));
 148   MCE.emitWordLE(0);
 149 }
 150
 151 /// emitGlobalAddress - Emit the specified address to the code stream assuming
 152 /// this is part of a "take the address of a global" instruction.
 153 ///
 154 void Emitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
 155                                 intptr_t Disp /* = 0 */,
 156                                 intptr_t PCAdj /* = 0 */,
 157                                 bool NeedStub /* = false */,
 158                                 bool Indirect /* = false */) {
 159   intptr_t RelocCST = 0;
 160   if (Reloc == X86::reloc_picrel_word)
 161     RelocCST = PICBaseOffset;
 162   else if (Reloc == X86::reloc_pcrel_word)
 163     RelocCST = PCAdj;
 164   MachineRelocation MR = Indirect
 165     ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
 166                                            GV, RelocCST, NeedStub)
 167     : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
 168                                GV, RelocCST, NeedStub);
 169   MCE.addRelocation(MR);
 170   // The relocated value will be added to the displacement
 171   if (Reloc == X86::reloc_absolute_dword)
 172     MCE.emitDWordLE(Disp);
 173   else
 174     MCE.emitWordLE((int32_t)Disp);
 175 }
 176
 177 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
 178 /// be emitted to the current location in the function, and allow it to be PC
 179 /// relative.
 180 void Emitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
 181   intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0;
 182   MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
 183                                                  Reloc, ES, RelocCST));
 184   if (Reloc == X86::reloc_absolute_dword)
 185     MCE.emitDWordLE(0);
 186   else
 187     MCE.emitWordLE(0);
 188 }
 189
 190 /// emitConstPoolAddress - Arrange for the address of an constant pool
 191 /// to be emitted to the current location in the function, and allow it to be PC
 192 /// relative.
 193 void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
 194                                    intptr_t Disp /* = 0 */,
 195                                    intptr_t PCAdj /* = 0 */) {
 196   intptr_t RelocCST = 0;
 197   if (Reloc == X86::reloc_picrel_word)
 198     RelocCST = PICBaseOffset;
 199   else if (Reloc == X86::reloc_pcrel_word)
 200     RelocCST = PCAdj;
 201   MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
 202                                                     Reloc, CPI, RelocCST));
 203   // The relocated value will be added to the displacement
 204   if (Reloc == X86::reloc_absolute_dword)
 205     MCE.emitDWordLE(Disp);
 206   else
 207     MCE.emitWordLE((int32_t)Disp);
 208 }
 209
 210 /// emitJumpTableAddress - Arrange for the address of a jump table to
 211 /// be emitted to the current location in the function, and allow it to be PC
 212 /// relative.
 213 void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
 214                                    intptr_t PCAdj /* = 0 */) {
 215   intptr_t RelocCST = 0;
 216   if (Reloc == X86::reloc_picrel_word)
 217     RelocCST = PICBaseOffset;
 218   else if (Reloc == X86::reloc_pcrel_word)
 219     RelocCST = PCAdj;
 220   MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
 221                                                     Reloc, JTI, RelocCST));
 222   // The relocated value will be added to the displacement
 223   if (Reloc == X86::reloc_absolute_dword)
 224     MCE.emitDWordLE(0);
 225   else
 226     MCE.emitWordLE(0);
 227 }
 228
 229 unsigned Emitter::getX86RegNum(unsigned RegNo) const {
 230   return II->getRegisterInfo().getX86RegNum(RegNo);
 231 }
 232
 233 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
 234                                       unsigned RM) {
 235   assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
 236   return RM | (RegOpcode << 3) | (Mod << 6);
 237 }
 238
 239 void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){
 240   MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
 241 }
 242
 243 void Emitter::emitRegModRMByte(unsigned RegOpcodeFld) {
 244   MCE.emitByte(ModRMByte(3, RegOpcodeFld, 0));
 245 }
 246
 247 void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) {
 248   // SIB byte is in the same format as the ModRMByte...
 249   MCE.emitByte(ModRMByte(SS, Index, Base));
 250 }
 251
 252 void Emitter::emitConstant(uint64_t Val, unsigned Size) {
 253   // Output the constant in little endian byte order...
 254   for (unsigned i = 0; i != Size; ++i) {
 255     MCE.emitByte(Val & 255);
 256     Val >>= 8;
 257   }
 258 }
 259
 260 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
 261 /// sign-extended field.
 262 static bool isDisp8(int Value) {
 263   return Value == (signed char)Value;
 264 }
 265
 266 bool Emitter::gvNeedsNonLazyPtr(const GlobalValue *GV) {
 267   // For Darwin, simulate the linktime GOT by using the same non-lazy-pointer
 268   // mechanism as 32-bit mode.
 269   return (!Is64BitMode || TM.getSubtarget<X86Subtarget>().isTargetDarwin()) &&
 270     TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(GV, TM, false);
 271 }
 272
 273 void Emitter::emitDisplacementField(const MachineOperand *RelocOp,
 274                                     int DispVal, intptr_t PCAdj) {
 275   // If this is a simple integer displacement that doesn't require a relocation,
 276   // emit it now.
 277   if (!RelocOp) {
 278     emitConstant(DispVal, 4);
 279     return;
 280   }
 281
 282   // Otherwise, this is something that requires a relocation.  Emit it as such
 283   // now.
 284   if (RelocOp->isGlobal()) {
 285     // In 64-bit static small code model, we could potentially emit absolute.
 286     // But it's probably not beneficial.
 287     //  89 05 00 00 00 00     mov    %eax,0(%rip)  # PC-relative
 288     //  89 04 25 00 00 00 00  mov    %eax,0x0      # Absolute
 289     unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
 290       : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
 291     bool NeedStub = isa<Function>(RelocOp->getGlobal());
 292     bool Indirect = gvNeedsNonLazyPtr(RelocOp->getGlobal());
 293     emitGlobalAddress(RelocOp->getGlobal(), rt, RelocOp->getOffset(),
 294                       PCAdj, NeedStub, Indirect);
 295   } else if (RelocOp->isCPI()) {
 296     unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
 297     emitConstPoolAddress(RelocOp->getIndex(), rt,
 298                          RelocOp->getOffset(), PCAdj);
 299   } else if (RelocOp->isJTI()) {
 300     unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
 301     emitJumpTableAddress(RelocOp->getIndex(), rt, PCAdj);
 302   } else {
 303     assert(0 && "Unknown value to relocate!");
 304   }
 305 }
 306
 307 void Emitter::emitMemModRMByte(const MachineInstr &MI,
 308                                unsigned Op, unsigned RegOpcodeField,
 309                                intptr_t PCAdj) {
 310   const MachineOperand &Op3 = MI.getOperand(Op+3);
 311   int DispVal = 0;
 312   const MachineOperand *DispForReloc = 0;
 313
 314   // Figure out what sort of displacement we have to handle here.
 315   if (Op3.isGlobal()) {
 316     DispForReloc = &Op3;
 317   } else if (Op3.isCPI()) {
 318     if (Is64BitMode || IsPIC) {
 319       DispForReloc = &Op3;
 320     } else {
 321       DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
 322       DispVal += Op3.getOffset();
 323     }
 324   } else if (Op3.isJTI()) {
 325     if (Is64BitMode || IsPIC) {
 326       DispForReloc = &Op3;
 327     } else {
 328       DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex());
 329     }
 330   } else {
 331     DispVal = Op3.getImm();
 332   }
 333
 334   const MachineOperand &Base     = MI.getOperand(Op);
 335   const MachineOperand &Scale    = MI.getOperand(Op+1);
 336   const MachineOperand &IndexReg = MI.getOperand(Op+2);
 337
 338   unsigned BaseReg = Base.getReg();
 339
 340   // Is a SIB byte needed?
 341   if ((!Is64BitMode || DispForReloc) && IndexReg.getReg() == 0 &&
 342       (BaseReg == 0 || getX86RegNum(BaseReg) != N86::ESP)) {
 343     if (BaseReg == 0) {  // Just a displacement?
 344       // Emit special case [disp32] encoding
 345       MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
 346
 347       emitDisplacementField(DispForReloc, DispVal, PCAdj);
 348     } else {
 349       unsigned BaseRegNo = getX86RegNum(BaseReg);
 350       if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
 351         // Emit simple indirect register encoding... [EAX] f.e.
 352         MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
 353       } else if (!DispForReloc && isDisp8(DispVal)) {
 354         // Emit the disp8 encoding... [REG+disp8]
 355         MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
 356         emitConstant(DispVal, 1);
 357       } else {
 358         // Emit the most general non-SIB encoding: [REG+disp32]
 359         MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
 360         emitDisplacementField(DispForReloc, DispVal, PCAdj);
 361       }
 362     }
 363
 364   } else {  // We need a SIB byte, so start by outputting the ModR/M byte first
 365     assert(IndexReg.getReg() != X86::ESP &&
 366            IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
 367
 368     bool ForceDisp32 = false;
 369     bool ForceDisp8  = false;
 370     if (BaseReg == 0) {
 371       // If there is no base register, we emit the special case SIB byte with
 372       // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
 373       MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
 374       ForceDisp32 = true;
 375     } else if (DispForReloc) {
 376       // Emit the normal disp32 encoding.
 377       MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
 378       ForceDisp32 = true;
 379     } else if (DispVal == 0 && getX86RegNum(BaseReg) != N86::EBP) {
 380       // Emit no displacement ModR/M byte
 381       MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
 382     } else if (isDisp8(DispVal)) {
 383       // Emit the disp8 encoding...
 384       MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
 385       ForceDisp8 = true;           // Make sure to force 8 bit disp if Base=EBP
 386     } else {
 387       // Emit the normal disp32 encoding...
 388       MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
 389     }
 390
 391     // Calculate what the SS field value should be...
 392     static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
 393     unsigned SS = SSTable[Scale.getImm()];
 394
 395     if (BaseReg == 0) {
 396       // Handle the SIB byte for the case where there is no base.  The
 397       // displacement has already been output.
 398       unsigned IndexRegNo;
 399       if (IndexReg.getReg())
 400         IndexRegNo = getX86RegNum(IndexReg.getReg());
 401       else
 402         IndexRegNo = 4;   // For example [ESP+1*<noreg>+4]
 403       emitSIBByte(SS, IndexRegNo, 5);
 404     } else {
 405       unsigned BaseRegNo = getX86RegNum(BaseReg);
 406       unsigned IndexRegNo;
 407       if (IndexReg.getReg())
 408         IndexRegNo = getX86RegNum(IndexReg.getReg());
 409       else
 410         IndexRegNo = 4;   // For example [ESP+1*<noreg>+4]
 411       emitSIBByte(SS, IndexRegNo, BaseRegNo);
 412     }
 413
 414     // Do we need to output a displacement?
 415     if (ForceDisp8) {
 416       emitConstant(DispVal, 1);
 417     } else if (DispVal != 0 || ForceDisp32) {
 418       emitDisplacementField(DispForReloc, DispVal, PCAdj);
 419     }
 420   }
 421 }
 422
 423 void Emitter::emitInstruction(const MachineInstr &MI,
 424                               const TargetInstrDesc *Desc) {
 425   DOUT << MI;
 426
 427   unsigned Opcode = Desc->Opcode;
 428
 429   // Emit the lock opcode prefix as needed.
 430   if (Desc->TSFlags & X86II::LOCK) MCE.emitByte(0xF0);
 431
 432   // Emit segment override opcode prefix as needed.
 433   switch (Desc->TSFlags & X86II::SegOvrMask) {
 434   case X86II::FS:
 435     MCE.emitByte(0x64);
 436     break;
 437   case X86II::GS:
 438     MCE.emitByte(0x65);
 439     break;
 440   default: assert(0 && "Invalid segment!");
 441   case 0: break;  // No segment override!
 442   }
 443
 444   // Emit the repeat opcode prefix as needed.
 445   if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
 446
 447   // Emit the operand size opcode prefix as needed.
 448   if (Desc->TSFlags & X86II::OpSize) MCE.emitByte(0x66);
 449
 450   // Emit the address size opcode prefix as needed.
 451   if (Desc->TSFlags & X86II::AdSize) MCE.emitByte(0x67);
 452
 453   bool Need0FPrefix = false;
 454   switch (Desc->TSFlags & X86II::Op0Mask) {
 455   case X86II::TB:  // Two-byte opcode prefix
 456   case X86II::T8:  // 0F 38
 457   case X86II::TA:  // 0F 3A
 458     Need0FPrefix = true;
 459     break;
 460   case X86II::REP: break; // already handled.
 461   case X86II::XS:   // F3 0F
 462     MCE.emitByte(0xF3);
 463     Need0FPrefix = true;
 464     break;
 465   case X86II::XD:   // F2 0F
 466     MCE.emitByte(0xF2);
 467     Need0FPrefix = true;
 468     break;
 469   case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
 470   case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
 471     MCE.emitByte(0xD8+
 472                  (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
 473                                    >> X86II::Op0Shift));
 474     break; // Two-byte opcode prefix
 475   default: assert(0 && "Invalid prefix!");
 476   case 0: break;  // No prefix!
 477   }
 478
 479   if (Is64BitMode) {
 480     // REX prefix
 481     unsigned REX = X86InstrInfo::determineREX(MI);
 482     if (REX)
 483       MCE.emitByte(0x40 | REX);
 484   }
 485
 486   // 0x0F escape code must be emitted just before the opcode.
 487   if (Need0FPrefix)
 488     MCE.emitByte(0x0F);
 489
 490   switch (Desc->TSFlags & X86II::Op0Mask) {
 491   case X86II::T8:  // 0F 38
 492     MCE.emitByte(0x38);
 493     break;
 494   case X86II::TA:    // 0F 3A
 495     MCE.emitByte(0x3A);
 496     break;
 497   }
 498
 499   // If this is a two-address instruction, skip one of the register operands.
 500   unsigned NumOps = Desc->getNumOperands();
 501   unsigned CurOp = 0;
 502   if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
 503     ++CurOp;
 504   else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
 505     // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
 506     --NumOps;
 507
 508   unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc);
 509   switch (Desc->TSFlags & X86II::FormMask) {
 510   default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
 511   case X86II::Pseudo:
 512     // Remember the current PC offset, this is the PIC relocation
 513     // base address.
 514     switch (Opcode) {
 515     default:
 516       assert(0 && "psuedo instructions should be removed before code emission");
 517       break;
 518     case TargetInstrInfo::INLINEASM: {
 519       // We allow inline assembler nodes with empty bodies - they can
 520       // implicitly define registers, which is ok for JIT.
 521       if (MI.getOperand(0).getSymbolName()[0]) {
 522         assert(0 && "JIT does not support inline asm!\n");
 523         abort();
 524       }
 525       break;
 526     }
 527     case TargetInstrInfo::DBG_LABEL:
 528     case TargetInstrInfo::EH_LABEL:
 529       MCE.emitLabel(MI.getOperand(0).getImm());
 530       break;
 531     case TargetInstrInfo::IMPLICIT_DEF:
 532     case TargetInstrInfo::DECLARE:
 533     case X86::DWARF_LOC:
 534     case X86::FP_REG_KILL:
 535       break;
 536     case X86::MOVPC32r: {
 537       // This emits the "call" portion of this pseudo instruction.
 538       MCE.emitByte(BaseOpcode);
 539       emitConstant(0, X86InstrInfo::sizeOfImm(Desc));
 540       // Remember PIC base.
 541       PICBaseOffset = (intptr_t) MCE.getCurrentPCOffset();
 542       X86JITInfo *JTI = TM.getJITInfo();
 543       JTI->setPICBase(MCE.getCurrentPCValue());
 544       break;
 545     }
 546     }
 547     CurOp = NumOps;
 548     break;
 549   case X86II::RawFrm:
 550     MCE.emitByte(BaseOpcode);
 551
 552     if (CurOp != NumOps) {
 553       const MachineOperand &MO = MI.getOperand(CurOp++);
 554
 555       DOUT << "RawFrm CurOp " << CurOp << "\n";
 556       DOUT << "isMBB " << MO.isMBB() << "\n";
 557       DOUT << "isGlobal " << MO.isGlobal() << "\n";
 558       DOUT << "isSymbol " << MO.isSymbol() << "\n";
 559       DOUT << "isImm " << MO.isImm() << "\n";
 560
 561       if (MO.isMBB()) {
 562         emitPCRelativeBlockAddress(MO.getMBB());
 563       } else if (MO.isGlobal()) {
 564         // Assume undefined functions may be outside the Small codespace.
 565         bool NeedStub =
 566           (Is64BitMode &&
 567               (TM.getCodeModel() == CodeModel::Large ||
 568                TM.getSubtarget<X86Subtarget>().isTargetDarwin())) ||
 569           Opcode == X86::TAILJMPd;
 570         emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
 571                           MO.getOffset(), 0, NeedStub);
 572       } else if (MO.isSymbol()) {
 573         emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
 574       } else if (MO.isImm()) {
 575         if (Opcode == X86::CALLpcrel32 || Opcode == X86::CALL64pcrel32) {
 576           // Fix up immediate operand for pc relative calls.
 577           intptr_t Imm = (intptr_t)MO.getImm();
 578           Imm = Imm - MCE.getCurrentPCValue() - 4;
 579           emitConstant(Imm, X86InstrInfo::sizeOfImm(Desc));
 580         } else
 581           emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc));
 582       } else {
 583         assert(0 && "Unknown RawFrm operand!");
 584       }
 585     }
 586     break;
 587
 588   case X86II::AddRegFrm:
 589     MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
 590
 591     if (CurOp != NumOps) {
 592       const MachineOperand &MO1 = MI.getOperand(CurOp++);
 593       unsigned Size = X86InstrInfo::sizeOfImm(Desc);
 594       if (MO1.isImm())
 595         emitConstant(MO1.getImm(), Size);
 596       else {
 597         unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
 598           : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
 599         // This should not occur on Darwin for relocatable objects.
 600         if (Opcode == X86::MOV64ri)
 601           rt = X86::reloc_absolute_dword;  // FIXME: add X86II flag?
 602         if (MO1.isGlobal()) {
 603           bool NeedStub = isa<Function>(MO1.getGlobal());
 604           bool Indirect = gvNeedsNonLazyPtr(MO1.getGlobal());
 605           emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
 606                             NeedStub, Indirect);
 607         } else if (MO1.isSymbol())
 608           emitExternalSymbolAddress(MO1.getSymbolName(), rt);
 609         else if (MO1.isCPI())
 610           emitConstPoolAddress(MO1.getIndex(), rt);
 611         else if (MO1.isJTI())
 612           emitJumpTableAddress(MO1.getIndex(), rt);
 613       }
 614     }
 615     break;
 616
 617   case X86II::MRMDestReg: {
 618     MCE.emitByte(BaseOpcode);
 619     emitRegModRMByte(MI.getOperand(CurOp).getReg(),
 620                      getX86RegNum(MI.getOperand(CurOp+1).getReg()));
 621     CurOp += 2;
 622     if (CurOp != NumOps)
 623       emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
 624     break;
 625   }
 626   case X86II::MRMDestMem: {
 627     MCE.emitByte(BaseOpcode);
 628     emitMemModRMByte(MI, CurOp,
 629                      getX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)
 630                                   .getReg()));
 631     CurOp +=  X86AddrNumOperands + 1;
 632     if (CurOp != NumOps)
 633       emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
 634     break;
 635   }
 636
 637   case X86II::MRMSrcReg:
 638     MCE.emitByte(BaseOpcode);
 639     emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
 640                      getX86RegNum(MI.getOperand(CurOp).getReg()));
 641     CurOp += 2;
 642     if (CurOp != NumOps)
 643       emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
 644     break;
 645
 646   case X86II::MRMSrcMem: {
 647     // FIXME: Maybe lea should have its own form?
 648     int AddrOperands;
 649     if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
 650         Opcode == X86::LEA16r || Opcode == X86::LEA32r)
 651       AddrOperands = X86AddrNumOperands - 1; // No segment register
 652     else
 653       AddrOperands = X86AddrNumOperands;
 654
 655     intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ?
 656       X86InstrInfo::sizeOfImm(Desc) : 0;
 657
 658     MCE.emitByte(BaseOpcode);
 659     emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
 660                      PCAdj);
 661     CurOp += AddrOperands + 1;
 662     if (CurOp != NumOps)
 663       emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
 664     break;
 665   }
 666
 667   case X86II::MRM0r: case X86II::MRM1r:
 668   case X86II::MRM2r: case X86II::MRM3r:
 669   case X86II::MRM4r: case X86II::MRM5r:
 670   case X86II::MRM6r: case X86II::MRM7r: {
 671     MCE.emitByte(BaseOpcode);
 672
 673     // Special handling of lfence and mfence.
 674     if (Desc->getOpcode() == X86::LFENCE ||
 675         Desc->getOpcode() == X86::MFENCE)
 676       emitRegModRMByte((Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
 677     else
 678       emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
 679                        (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
 680
 681     if (CurOp != NumOps) {
 682       const MachineOperand &MO1 = MI.getOperand(CurOp++);
 683       unsigned Size = X86InstrInfo::sizeOfImm(Desc);
 684       if (MO1.isImm())
 685         emitConstant(MO1.getImm(), Size);
 686       else {
 687         unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
 688           : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
 689         if (Opcode == X86::MOV64ri32)
 690           rt = X86::reloc_absolute_word;  // FIXME: add X86II flag?
 691         if (MO1.isGlobal()) {
 692           bool NeedStub = isa<Function>(MO1.getGlobal());
 693           bool Indirect = gvNeedsNonLazyPtr(MO1.getGlobal());
 694           emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
 695                             NeedStub, Indirect);
 696         } else if (MO1.isSymbol())
 697           emitExternalSymbolAddress(MO1.getSymbolName(), rt);
 698         else if (MO1.isCPI())
 699           emitConstPoolAddress(MO1.getIndex(), rt);
 700         else if (MO1.isJTI())
 701           emitJumpTableAddress(MO1.getIndex(), rt);
 702       }
 703     }
 704     break;
 705   }
 706
 707   case X86II::MRM0m: case X86II::MRM1m:
 708   case X86II::MRM2m: case X86II::MRM3m:
 709   case X86II::MRM4m: case X86II::MRM5m:
 710   case X86II::MRM6m: case X86II::MRM7m: {
 711     intptr_t PCAdj = (CurOp + X86AddrNumOperands != NumOps) ?
 712       (MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm(Desc) : 4) : 0;
 713
 714     MCE.emitByte(BaseOpcode);
 715     emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
 716                      PCAdj);
 717     CurOp += X86AddrNumOperands;
 718
 719     if (CurOp != NumOps) {
 720       const MachineOperand &MO = MI.getOperand(CurOp++);
 721       unsigned Size = X86InstrInfo::sizeOfImm(Desc);
 722       if (MO.isImm())
 723         emitConstant(MO.getImm(), Size);
 724       else {
 725         unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
 726           : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
 727         if (Opcode == X86::MOV64mi32)
 728           rt = X86::reloc_absolute_word;  // FIXME: add X86II flag?
 729         if (MO.isGlobal()) {
 730           bool NeedStub = isa<Function>(MO.getGlobal());
 731           bool Indirect = gvNeedsNonLazyPtr(MO.getGlobal());
 732           emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
 733                             NeedStub, Indirect);
 734         } else if (MO.isSymbol())
 735           emitExternalSymbolAddress(MO.getSymbolName(), rt);
 736         else if (MO.isCPI())
 737           emitConstPoolAddress(MO.getIndex(), rt);
 738         else if (MO.isJTI())
 739           emitJumpTableAddress(MO.getIndex(), rt);
 740       }
 741     }
 742     break;
 743   }
 744
 745   case X86II::MRMInitReg:
 746     MCE.emitByte(BaseOpcode);
 747     // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
 748     emitRegModRMByte(MI.getOperand(CurOp).getReg(),
 749                      getX86RegNum(MI.getOperand(CurOp).getReg()));
 750     ++CurOp;
 751     break;
 752   }
 753
 754   if (!Desc->isVariadic() && CurOp != NumOps) {
 755     cerr << "Cannot encode: ";
 756     MI.dump();
 757     cerr << '\n';
 758     abort();
 759   }
 760 }