lib/Target/MSP430/MSP430ISelLowering.cpp

   1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the MSP430TargetLowering class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #define DEBUG_TYPE "msp430-lower"
  15
  16 #include "MSP430ISelLowering.h"
  17 #include "MSP430.h"
  18 #include "MSP430TargetMachine.h"
  19 #include "MSP430Subtarget.h"
  20 #include "llvm/DerivedTypes.h"
  21 #include "llvm/Function.h"
  22 #include "llvm/Intrinsics.h"
  23 #include "llvm/CallingConv.h"
  24 #include "llvm/GlobalVariable.h"
  25 #include "llvm/GlobalAlias.h"
  26 #include "llvm/CodeGen/CallingConvLower.h"
  27 #include "llvm/CodeGen/MachineFrameInfo.h"
  28 #include "llvm/CodeGen/MachineFunction.h"
  29 #include "llvm/CodeGen/MachineInstrBuilder.h"
  30 #include "llvm/CodeGen/MachineRegisterInfo.h"
  31 #include "llvm/CodeGen/PseudoSourceValue.h"
  32 #include "llvm/CodeGen/SelectionDAGISel.h"
  33 #include "llvm/CodeGen/ValueTypes.h"
  34 #include "llvm/Support/Debug.h"
  35 #include "llvm/ADT/VectorExtras.h"
  36 using namespace llvm;
  37
  38 MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
  39   TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
  40
  41   // Set up the register classes.
  42   addRegisterClass(MVT::i8,  MSP430::GR8RegisterClass);
  43   addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
  44
  45   // Compute derived properties from the register classes
  46   computeRegisterProperties();
  47
  48   // Provide all sorts of operation actions
  49
  50   // Division is expensive
  51   setIntDivIsCheap(false);
  52
  53   // Even if we have only 1 bit shift here, we can perform
  54   // shifts of the whole bitwidth 1 bit per step.
  55   setShiftAmountType(MVT::i8);
  56
  57   setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
  58   setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
  59   setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
  60   setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
  61   setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
  62
  63   // We don't have any truncstores
  64   setTruncStoreAction(MVT::i16, MVT::i8, Expand);
  65
  66   setOperationAction(ISD::SRA, MVT::i16, Custom);
  67   setOperationAction(ISD::RET, MVT::Other, Custom);
  68   setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
  69 }
  70
  71 SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
  72   switch (Op.getOpcode()) {
  73   case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
  74   case ISD::SRA:              return LowerShifts(Op, DAG);
  75   case ISD::RET:              return LowerRET(Op, DAG);
  76   case ISD::CALL:             return LowerCALL(Op, DAG);
  77   case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
  78   default:
  79     assert(0 && "unimplemented operand");
  80     return SDValue();
  81   }
  82 }
  83
  84 //===----------------------------------------------------------------------===//
  85 //                      Calling Convention Implementation
  86 //===----------------------------------------------------------------------===//
  87
  88 #include "MSP430GenCallingConv.inc"
  89
  90 SDValue MSP430TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
  91                                                     SelectionDAG &DAG) {
  92   unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
  93   switch (CC) {
  94   default:
  95     assert(0 && "Unsupported calling convention");
  96   case CallingConv::C:
  97   case CallingConv::Fast:
  98     return LowerCCCArguments(Op, DAG);
  99   }
 100 }
 101
 102 SDValue MSP430TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
 103   CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
 104   unsigned CallingConv = TheCall->getCallingConv();
 105   switch (CallingConv) {
 106   default:
 107     assert(0 && "Unsupported calling convention");
 108   case CallingConv::Fast:
 109   case CallingConv::C:
 110     return LowerCCCCallTo(Op, DAG, CallingConv);
 111   }
 112 }
 113
 114 /// LowerCCCArguments - transform physical registers into virtual registers and
 115 /// generate load operations for arguments places on the stack.
 116 // FIXME: struct return stuff
 117 // FIXME: varargs
 118 SDValue MSP430TargetLowering::LowerCCCArguments(SDValue Op,
 119                                                 SelectionDAG &DAG) {
 120   MachineFunction &MF = DAG.getMachineFunction();
 121   MachineFrameInfo *MFI = MF.getFrameInfo();
 122   MachineRegisterInfo &RegInfo = MF.getRegInfo();
 123   SDValue Root = Op.getOperand(0);
 124   bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
 125   unsigned CC = MF.getFunction()->getCallingConv();
 126   DebugLoc dl = Op.getDebugLoc();
 127
 128   // Assign locations to all of the incoming arguments.
 129   SmallVector<CCValAssign, 16> ArgLocs;
 130   CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
 131   CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_MSP430);
 132
 133   assert(!isVarArg && "Varargs not supported yet");
 134
 135   SmallVector<SDValue, 16> ArgValues;
 136   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
 137     CCValAssign &VA = ArgLocs[i];
 138     if (VA.isRegLoc()) {
 139       // Arguments passed in registers
 140       MVT RegVT = VA.getLocVT();
 141       switch (RegVT.getSimpleVT()) {
 142       default:
 143         cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
 144              << RegVT.getSimpleVT()
 145              << "\n";
 146         abort();
 147       case MVT::i16:
 148         unsigned VReg =
 149           RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
 150         RegInfo.addLiveIn(VA.getLocReg(), VReg);
 151         SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);
 152
 153         // If this is an 8-bit value, it is really passed promoted to 16
 154         // bits. Insert an assert[sz]ext to capture this, then truncate to the
 155         // right size.
 156         if (VA.getLocInfo() == CCValAssign::SExt)
 157           ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
 158                                  DAG.getValueType(VA.getValVT()));
 159         else if (VA.getLocInfo() == CCValAssign::ZExt)
 160           ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
 161                                  DAG.getValueType(VA.getValVT()));
 162
 163         if (VA.getLocInfo() != CCValAssign::Full)
 164           ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
 165
 166         ArgValues.push_back(ArgValue);
 167       }
 168     } else {
 169       // Sanity check
 170       assert(VA.isMemLoc());
 171       // Load the argument to a virtual register
 172       unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
 173       if (ObjSize > 2) {
 174         cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
 175              << VA.getLocVT().getSimpleVT()
 176              << "\n";
 177       }
 178       // Create the frame index object for this incoming parameter...
 179       int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset());
 180
 181       // Create the SelectionDAG nodes corresponding to a load
 182       //from this parameter
 183       SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
 184       ArgValues.push_back(DAG.getLoad(VA.getLocVT(), dl, Root, FIN,
 185                                       PseudoSourceValue::getFixedStack(FI), 0));
 186     }
 187   }
 188
 189   ArgValues.push_back(Root);
 190
 191   // Return the new list of results.
 192   return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
 193                      &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
 194 }
 195
 196 SDValue MSP430TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
 197   // CCValAssign - represent the assignment of the return value to a location
 198   SmallVector<CCValAssign, 16> RVLocs;
 199   unsigned CC   = DAG.getMachineFunction().getFunction()->getCallingConv();
 200   bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
 201   DebugLoc dl = Op.getDebugLoc();
 202
 203   // CCState - Info about the registers and stack slot.
 204   CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
 205
 206   // Analize return values of ISD::RET
 207   CCInfo.AnalyzeReturn(Op.getNode(), RetCC_MSP430);
 208
 209   // If this is the first return lowered for this function, add the regs to the
 210   // liveout set for the function.
 211   if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
 212     for (unsigned i = 0; i != RVLocs.size(); ++i)
 213       if (RVLocs[i].isRegLoc())
 214         DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
 215   }
 216
 217   // The chain is always operand #0
 218   SDValue Chain = Op.getOperand(0);
 219   SDValue Flag;
 220
 221   // Copy the result values into the output registers.
 222   for (unsigned i = 0; i != RVLocs.size(); ++i) {
 223     CCValAssign &VA = RVLocs[i];
 224     assert(VA.isRegLoc() && "Can only return in registers!");
 225
 226     // ISD::RET => ret chain, (regnum1,val1), ...
 227     // So i*2+1 index only the regnums
 228     Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
 229                              Op.getOperand(i*2+1), Flag);
 230
 231     // Guarantee that all emitted copies are stuck together,
 232     // avoiding something bad.
 233     Flag = Chain.getValue(1);
 234   }
 235
 236   if (Flag.getNode())
 237     return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
 238
 239   // Return Void
 240   return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain);
 241 }
 242
 243 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
 244 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
 245 /// TODO: sret.
 246 SDValue MSP430TargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
 247                                              unsigned CC) {
 248   CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
 249   SDValue Chain  = TheCall->getChain();
 250   SDValue Callee = TheCall->getCallee();
 251   bool isVarArg  = TheCall->isVarArg();
 252   DebugLoc dl = Op.getDebugLoc();
 253
 254   // Analyze operands of the call, assigning locations to each operand.
 255   SmallVector<CCValAssign, 16> ArgLocs;
 256   CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
 257
 258   CCInfo.AnalyzeCallOperands(TheCall, CC_MSP430);
 259
 260   // Get a count of how many bytes are to be pushed on the stack.
 261   unsigned NumBytes = CCInfo.getNextStackOffset();
 262
 263   Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
 264                                                       getPointerTy(), true));
 265
 266   SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
 267   SmallVector<SDValue, 12> MemOpChains;
 268   SDValue StackPtr;
 269
 270   // Walk the register/memloc assignments, inserting copies/loads.
 271   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
 272     CCValAssign &VA = ArgLocs[i];
 273
 274     // Arguments start after the 5 first operands of ISD::CALL
 275     SDValue Arg = TheCall->getArg(i);
 276
 277     // Promote the value if needed.
 278     switch (VA.getLocInfo()) {
 279       default: assert(0 && "Unknown loc info!");
 280       case CCValAssign::Full: break;
 281       case CCValAssign::SExt:
 282         Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
 283         break;
 284       case CCValAssign::ZExt:
 285         Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
 286         break;
 287       case CCValAssign::AExt:
 288         Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
 289         break;
 290     }
 291
 292     // Arguments that can be passed on register must be kept at RegsToPass
 293     // vector
 294     if (VA.isRegLoc()) {
 295       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
 296     } else {
 297       assert(VA.isMemLoc());
 298
 299       if (StackPtr.getNode() == 0)
 300         StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
 301
 302       SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
 303                                    StackPtr,
 304                                    DAG.getIntPtrConstant(VA.getLocMemOffset()));
 305
 306
 307       MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
 308                                          PseudoSourceValue::getStack(),
 309                                          VA.getLocMemOffset()));
 310     }
 311   }
 312
 313   // Transform all store nodes into one single node because all store nodes are
 314   // independent of each other.
 315   if (!MemOpChains.empty())
 316     Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
 317                         &MemOpChains[0], MemOpChains.size());
 318
 319   // Build a sequence of copy-to-reg nodes chained together with token chain and
 320   // flag operands which copy the outgoing args into registers.  The InFlag in
 321   // necessary since all emited instructions must be stuck together.
 322   SDValue InFlag;
 323   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
 324     Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
 325                              RegsToPass[i].second, InFlag);
 326     InFlag = Chain.getValue(1);
 327   }
 328
 329   // If the callee is a GlobalAddress node (quite common, every direct call is)
 330   // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
 331   // Likewise ExternalSymbol -> TargetExternalSymbol.
 332   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
 333     Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16);
 334   else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
 335     Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
 336
 337   // Returns a chain & a flag for retval copy to use.
 338   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
 339   SmallVector<SDValue, 8> Ops;
 340   Ops.push_back(Chain);
 341   Ops.push_back(Callee);
 342
 343   // Add argument registers to the end of the list so that they are
 344   // known live into the call.
 345   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
 346     Ops.push_back(DAG.getRegister(RegsToPass[i].first,
 347                                   RegsToPass[i].second.getValueType()));
 348
 349   if (InFlag.getNode())
 350     Ops.push_back(InFlag);
 351
 352   Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
 353   InFlag = Chain.getValue(1);
 354
 355   // Create the CALLSEQ_END node.
 356   Chain = DAG.getCALLSEQ_END(Chain,
 357                              DAG.getConstant(NumBytes, getPointerTy(), true),
 358                              DAG.getConstant(0, getPointerTy(), true),
 359                              InFlag);
 360   InFlag = Chain.getValue(1);
 361
 362   // Handle result values, copying them out of physregs into vregs that we
 363   // return.
 364   return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
 365                  Op.getResNo());
 366 }
 367
 368 /// LowerCallResult - Lower the result values of an ISD::CALL into the
 369 /// appropriate copies out of appropriate physical registers.  This assumes that
 370 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
 371 /// being lowered. Returns a SDNode with the same number of values as the
 372 /// ISD::CALL.
 373 SDNode*
 374 MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
 375                                       CallSDNode *TheCall,
 376                                       unsigned CallingConv,
 377                                       SelectionDAG &DAG) {
 378   bool isVarArg = TheCall->isVarArg();
 379   DebugLoc dl = TheCall->getDebugLoc();
 380
 381   // Assign locations to each value returned by this call.
 382   SmallVector<CCValAssign, 16> RVLocs;
 383   CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
 384
 385   CCInfo.AnalyzeCallResult(TheCall, RetCC_MSP430);
 386   SmallVector<SDValue, 8> ResultVals;
 387
 388   // Copy all of the result registers out of their specified physreg.
 389   for (unsigned i = 0; i != RVLocs.size(); ++i) {
 390     Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
 391                                RVLocs[i].getValVT(), InFlag).getValue(1);
 392     InFlag = Chain.getValue(2);
 393     ResultVals.push_back(Chain.getValue(0));
 394   }
 395
 396   ResultVals.push_back(Chain);
 397
 398   // Merge everything together with a MERGE_VALUES node.
 399   return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
 400                      &ResultVals[0], ResultVals.size()).getNode();
 401 }
 402
 403 SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
 404                                           SelectionDAG &DAG) {
 405   assert(Op.getOpcode() == ISD::SRA && "Only SRA is currently supported.");
 406   SDNode* N = Op.getNode();
 407   MVT VT = Op.getValueType();
 408   DebugLoc dl = N->getDebugLoc();
 409
 410   // We currently only lower SRA of constant argument.
 411   if (!isa<ConstantSDNode>(N->getOperand(1)))
 412     return SDValue();
 413
 414   uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
 415
 416   // Expand the stuff into sequence of shifts.
 417   // FIXME: for some shift amounts this might be done better!
 418   // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
 419   SDValue Victim = N->getOperand(0);
 420   while (ShiftAmount--)
 421     Victim = DAG.getNode(MSP430ISD::RRA, dl, VT, Victim);
 422
 423   return Victim;
 424 }
 425
 426 SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
 427   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
 428   int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
 429
 430   // Create the TargetGlobalAddress node, folding in the constant offset.
 431   SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
 432   return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
 433                      getPointerTy(), Result);
 434 }
 435
 436 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
 437   switch (Opcode) {
 438   default: return NULL;
 439   case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
 440   case MSP430ISD::RRA:                return "MSP430ISD::RRA";
 441   case MSP430ISD::CALL:               return "MSP430ISD::CALL";
 442   case MSP430ISD::Wrapper:            return "MSP430ISD::Wrapper";
 443   }
 444 }