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Proper name 16 bit libcalls
[llvm/msp430.git] / lib / Target / ARM / ARMISelLowering.cpp
blob7704209190f7c06038e923a6cd3a49ad01fc79bf
1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "ARM.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMISelLowering.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Function.h"
26 #include "llvm/Instruction.h"
27 #include "llvm/Intrinsics.h"
28 #include "llvm/GlobalValue.h"
29 #include "llvm/CodeGen/CallingConvLower.h"
30 #include "llvm/CodeGen/MachineBasicBlock.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/PseudoSourceValue.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/VectorExtras.h"
39 #include "llvm/Support/MathExtras.h"
40 using namespace llvm;
41
42 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
43 CCValAssign::LocInfo &LocInfo,
44 ISD::ArgFlagsTy &ArgFlags,
45 CCState &State);
46 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
47 CCValAssign::LocInfo &LocInfo,
48 ISD::ArgFlagsTy &ArgFlags,
49 CCState &State);
50 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
51 CCValAssign::LocInfo &LocInfo,
52 ISD::ArgFlagsTy &ArgFlags,
53 CCState &State);
54 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
55 CCValAssign::LocInfo &LocInfo,
56 ISD::ArgFlagsTy &ArgFlags,
57 CCState &State);
58
59 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
60 : TargetLowering(TM), ARMPCLabelIndex(0) {
61 Subtarget = &TM.getSubtarget<ARMSubtarget>();
62
63 if (Subtarget->isTargetDarwin()) {
64 // Uses VFP for Thumb libfuncs if available.
65 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
66 // Single-precision floating-point arithmetic.
67 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
68 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
69 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
70 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
71
72 // Double-precision floating-point arithmetic.
73 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
74 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
75 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
76 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
77
78 // Single-precision comparisons.
79 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
80 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
81 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
82 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
83 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
84 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
85 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
86 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
87
88 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
89 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
90 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
91 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
92 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
93 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
94 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
95 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
96
97 // Double-precision comparisons.
98 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
99 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
100 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
101 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
102 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
103 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
104 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
105 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
106
107 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
108 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
109 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
110 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
111 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
112 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
113 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
114 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
115
116 // Floating-point to integer conversions.
117 // i64 conversions are done via library routines even when generating VFP
118 // instructions, so use the same ones.
119 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
120 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
121 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
122 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
123
124 // Conversions between floating types.
125 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
126 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
127
128 // Integer to floating-point conversions.
129 // i64 conversions are done via library routines even when generating VFP
130 // instructions, so use the same ones.
131 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
132 // e.g., __floatunsidf vs. __floatunssidfvfp.
133 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
134 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
135 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
136 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
137 }
138 }
139
140 if (Subtarget->isThumb())
141 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
142 else
143 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
144 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
145 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
146 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
147
148 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
149 }
150 computeRegisterProperties();
151
152 // ARM does not have f32 extending load.
153 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
154
155 // ARM does not have i1 sign extending load.
156 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
157
158 // ARM supports all 4 flavors of integer indexed load / store.
159 for (unsigned im = (unsigned)ISD::PRE_INC;
160 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
161 setIndexedLoadAction(im, MVT::i1, Legal);
162 setIndexedLoadAction(im, MVT::i8, Legal);
163 setIndexedLoadAction(im, MVT::i16, Legal);
164 setIndexedLoadAction(im, MVT::i32, Legal);
165 setIndexedStoreAction(im, MVT::i1, Legal);
166 setIndexedStoreAction(im, MVT::i8, Legal);
167 setIndexedStoreAction(im, MVT::i16, Legal);
168 setIndexedStoreAction(im, MVT::i32, Legal);
169 }
170
171 // i64 operation support.
172 if (Subtarget->isThumb()) {
173 setOperationAction(ISD::MUL, MVT::i64, Expand);
174 setOperationAction(ISD::MULHU, MVT::i32, Expand);
175 setOperationAction(ISD::MULHS, MVT::i32, Expand);
176 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
177 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
178 } else {
179 setOperationAction(ISD::MUL, MVT::i64, Expand);
180 setOperationAction(ISD::MULHU, MVT::i32, Expand);
181 if (!Subtarget->hasV6Ops())
182 setOperationAction(ISD::MULHS, MVT::i32, Expand);
183 }
184 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
185 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
186 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
187 setOperationAction(ISD::SRL, MVT::i64, Custom);
188 setOperationAction(ISD::SRA, MVT::i64, Custom);
189
190 // ARM does not have ROTL.
191 setOperationAction(ISD::ROTL, MVT::i32, Expand);
192 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
193 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
194 if (!Subtarget->hasV5TOps() || Subtarget->isThumb())
195 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
196
197 // Only ARMv6 has BSWAP.
198 if (!Subtarget->hasV6Ops())
199 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
200
201 // These are expanded into libcalls.
202 setOperationAction(ISD::SDIV, MVT::i32, Expand);
203 setOperationAction(ISD::UDIV, MVT::i32, Expand);
204 setOperationAction(ISD::SREM, MVT::i32, Expand);
205 setOperationAction(ISD::UREM, MVT::i32, Expand);
206 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
207 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
208
209 // Support label based line numbers.
210 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
211 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
212
213 setOperationAction(ISD::RET, MVT::Other, Custom);
214 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
215 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
216 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
217 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
218
219 // Use the default implementation.
220 setOperationAction(ISD::VASTART, MVT::Other, Custom);
221 setOperationAction(ISD::VAARG, MVT::Other, Expand);
222 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
223 setOperationAction(ISD::VAEND, MVT::Other, Expand);
224 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
225 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
226 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
227 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
228
229 if (!Subtarget->hasV6Ops()) {
230 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
231 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
232 }
233 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
234
235 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb())
236 // Turn f64->i64 into FMRRD, i64 -> f64 to FMDRR iff target supports vfp2.
237 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
238
239 // We want to custom lower some of our intrinsics.
240 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
241
242 setOperationAction(ISD::SETCC, MVT::i32, Expand);
243 setOperationAction(ISD::SETCC, MVT::f32, Expand);
244 setOperationAction(ISD::SETCC, MVT::f64, Expand);
245 setOperationAction(ISD::SELECT, MVT::i32, Expand);
246 setOperationAction(ISD::SELECT, MVT::f32, Expand);
247 setOperationAction(ISD::SELECT, MVT::f64, Expand);
248 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
249 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
250 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
251
252 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
253 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
254 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
255 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
256 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
257
258 // We don't support sin/cos/fmod/copysign/pow
259 setOperationAction(ISD::FSIN, MVT::f64, Expand);
260 setOperationAction(ISD::FSIN, MVT::f32, Expand);
261 setOperationAction(ISD::FCOS, MVT::f32, Expand);
262 setOperationAction(ISD::FCOS, MVT::f64, Expand);
263 setOperationAction(ISD::FREM, MVT::f64, Expand);
264 setOperationAction(ISD::FREM, MVT::f32, Expand);
265 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
266 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
267 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
268 }
269 setOperationAction(ISD::FPOW, MVT::f64, Expand);
270 setOperationAction(ISD::FPOW, MVT::f32, Expand);
271
272 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
273 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
274 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
275 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
276 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
277 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
278 }
279
280 // We have target-specific dag combine patterns for the following nodes:
281 // ARMISD::FMRRD - No need to call setTargetDAGCombine
282 setTargetDAGCombine(ISD::ADD);
283 setTargetDAGCombine(ISD::SUB);
284
285 setStackPointerRegisterToSaveRestore(ARM::SP);
286 setSchedulingPreference(SchedulingForRegPressure);
287 setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
288 setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2);
289
290 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
291 }
292
293 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
294 switch (Opcode) {
295 default: return 0;
296 case ARMISD::Wrapper: return "ARMISD::Wrapper";
297 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
298 case ARMISD::CALL: return "ARMISD::CALL";
299 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
300 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
301 case ARMISD::tCALL: return "ARMISD::tCALL";
302 case ARMISD::BRCOND: return "ARMISD::BRCOND";
303 case ARMISD::BR_JT: return "ARMISD::BR_JT";
304 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
305 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
306 case ARMISD::CMP: return "ARMISD::CMP";
307 case ARMISD::CMPNZ: return "ARMISD::CMPNZ";
308 case ARMISD::CMPFP: return "ARMISD::CMPFP";
309 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
310 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
311 case ARMISD::CMOV: return "ARMISD::CMOV";
312 case ARMISD::CNEG: return "ARMISD::CNEG";
313
314 case ARMISD::FTOSI: return "ARMISD::FTOSI";
315 case ARMISD::FTOUI: return "ARMISD::FTOUI";
316 case ARMISD::SITOF: return "ARMISD::SITOF";
317 case ARMISD::UITOF: return "ARMISD::UITOF";
318
319 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
320 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
321 case ARMISD::RRX: return "ARMISD::RRX";
322
323 case ARMISD::FMRRD: return "ARMISD::FMRRD";
324 case ARMISD::FMDRR: return "ARMISD::FMDRR";
325
326 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
327 }
328 }
329
330 //===----------------------------------------------------------------------===//
331 // Lowering Code
332 //===----------------------------------------------------------------------===//
333
334 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
335 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
336 switch (CC) {
337 default: assert(0 && "Unknown condition code!");
338 case ISD::SETNE: return ARMCC::NE;
339 case ISD::SETEQ: return ARMCC::EQ;
340 case ISD::SETGT: return ARMCC::GT;
341 case ISD::SETGE: return ARMCC::GE;
342 case ISD::SETLT: return ARMCC::LT;
343 case ISD::SETLE: return ARMCC::LE;
344 case ISD::SETUGT: return ARMCC::HI;
345 case ISD::SETUGE: return ARMCC::HS;
346 case ISD::SETULT: return ARMCC::LO;
347 case ISD::SETULE: return ARMCC::LS;
348 }
349 }
350
351 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
352 /// returns true if the operands should be inverted to form the proper
353 /// comparison.
354 static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
355 ARMCC::CondCodes &CondCode2) {
356 bool Invert = false;
357 CondCode2 = ARMCC::AL;
358 switch (CC) {
359 default: assert(0 && "Unknown FP condition!");
360 case ISD::SETEQ:
361 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
362 case ISD::SETGT:
363 case ISD::SETOGT: CondCode = ARMCC::GT; break;
364 case ISD::SETGE:
365 case ISD::SETOGE: CondCode = ARMCC::GE; break;
366 case ISD::SETOLT: CondCode = ARMCC::MI; break;
367 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
368 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
369 case ISD::SETO: CondCode = ARMCC::VC; break;
370 case ISD::SETUO: CondCode = ARMCC::VS; break;
371 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
372 case ISD::SETUGT: CondCode = ARMCC::HI; break;
373 case ISD::SETUGE: CondCode = ARMCC::PL; break;
374 case ISD::SETLT:
375 case ISD::SETULT: CondCode = ARMCC::LT; break;
376 case ISD::SETLE:
377 case ISD::SETULE: CondCode = ARMCC::LE; break;
378 case ISD::SETNE:
379 case ISD::SETUNE: CondCode = ARMCC::NE; break;
380 }
381 return Invert;
382 }
383
384 //===----------------------------------------------------------------------===//
385 // Calling Convention Implementation
386 //
387 // The lower operations present on calling convention works on this order:
388 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
389 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
390 // LowerRET (virt regs --> phys regs)
391 // LowerCALL (phys regs --> virt regs)
392 //
393 //===----------------------------------------------------------------------===//
394
395 #include "ARMGenCallingConv.inc"
396
397 // APCS f64 is in register pairs, possibly split to stack
398 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
399 CCValAssign::LocInfo &LocInfo,
400 ISD::ArgFlagsTy &ArgFlags,
401 CCState &State) {
402 static const unsigned HiRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
403 static const unsigned LoRegList[] = { ARM::R1,
404 ARM::R2,
405 ARM::R3,
406 ARM::NoRegister };
407
408 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 4);
409 if (Reg == 0)
410 return false; // we didn't handle it
411
412 unsigned i;
413 for (i = 0; i < 4; ++i)
414 if (HiRegList[i] == Reg)
415 break;
416
417 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, MVT::i32, LocInfo));
418 if (LoRegList[i] != ARM::NoRegister)
419 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
420 MVT::i32, LocInfo));
421 else
422 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
423 State.AllocateStack(4, 4),
424 MVT::i32, LocInfo));
425 return true; // we handled it
426 }
427
428 // AAPCS f64 is in aligned register pairs
429 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
430 CCValAssign::LocInfo &LocInfo,
431 ISD::ArgFlagsTy &ArgFlags,
432 CCState &State) {
433 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
434 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
435
436 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
437 if (Reg == 0)
438 return false; // we didn't handle it
439
440 unsigned i;
441 for (i = 0; i < 2; ++i)
442 if (HiRegList[i] == Reg)
443 break;
444
445 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, MVT::i32, LocInfo));
446 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
447 MVT::i32, LocInfo));
448 return true; // we handled it
449 }
450
451 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
452 CCValAssign::LocInfo &LocInfo,
453 ISD::ArgFlagsTy &ArgFlags,
454 CCState &State) {
455 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
456 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
457
458 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
459 if (Reg == 0)
460 return false; // we didn't handle it
461
462 unsigned i;
463 for (i = 0; i < 2; ++i)
464 if (HiRegList[i] == Reg)
465 break;
466
467 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, MVT::i32, LocInfo));
468 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
469 MVT::i32, LocInfo));
470 return true; // we handled it
471 }
472
473 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
474 CCValAssign::LocInfo &LocInfo,
475 ISD::ArgFlagsTy &ArgFlags,
476 CCState &State) {
477 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
478 State);
479 }
480
481 /// LowerCallResult - Lower the result values of an ISD::CALL into the
482 /// appropriate copies out of appropriate physical registers. This assumes that
483 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
484 /// being lowered. The returns a SDNode with the same number of values as the
485 /// ISD::CALL.
486 SDNode *ARMTargetLowering::
487 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
488 unsigned CallingConv, SelectionDAG &DAG) {
489
490 DebugLoc dl = TheCall->getDebugLoc();
491 // Assign locations to each value returned by this call.
492 SmallVector<CCValAssign, 16> RVLocs;
493 bool isVarArg = TheCall->isVarArg();
494 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
495 CCInfo.AnalyzeCallResult(TheCall, RetCC_ARM);
496
497 SmallVector<SDValue, 8> ResultVals;
498
499 // Copy all of the result registers out of their specified physreg.
500 for (unsigned i = 0; i != RVLocs.size(); ++i) {
501 CCValAssign VA = RVLocs[i];
502
503 SDValue Val;
504 if (VA.needsCustom()) {
505 // Handle f64 as custom.
506 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
507 InFlag);
508 Chain = Lo.getValue(1);
509 InFlag = Lo.getValue(2);
510 VA = RVLocs[++i]; // skip ahead to next loc
511 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
512 InFlag);
513 Chain = Hi.getValue(1);
514 InFlag = Hi.getValue(2);
515 Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
516 } else {
517 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
518 InFlag);
519 Chain = Val.getValue(1);
520 InFlag = Val.getValue(2);
521 }
522
523 switch (VA.getLocInfo()) {
524 default: assert(0 && "Unknown loc info!");
525 case CCValAssign::Full: break;
526 case CCValAssign::BCvt:
527 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
528 break;
529 }
530
531 ResultVals.push_back(Val);
532 }
533
534 // Merge everything together with a MERGE_VALUES node.
535 ResultVals.push_back(Chain);
536 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
537 &ResultVals[0], ResultVals.size()).getNode();
538 }
539
540 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
541 /// by "Src" to address "Dst" of size "Size". Alignment information is
542 /// specified by the specific parameter attribute. The copy will be passed as
543 /// a byval function parameter.
544 /// Sometimes what we are copying is the end of a larger object, the part that
545 /// does not fit in registers.
546 static SDValue
547 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
548 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
549 DebugLoc dl) {
550 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
551 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
552 /*AlwaysInline=*/false, NULL, 0, NULL, 0);
553 }
554
555 /// LowerMemOpCallTo - Store the argument to the stack.
556 SDValue
557 ARMTargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
558 const SDValue &StackPtr,
559 const CCValAssign &VA, SDValue Chain,
560 SDValue Arg, ISD::ArgFlagsTy Flags) {
561 DebugLoc dl = TheCall->getDebugLoc();
562 unsigned LocMemOffset = VA.getLocMemOffset();
563 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
564 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
565 if (Flags.isByVal()) {
566 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
567 }
568 return DAG.getStore(Chain, dl, Arg, PtrOff,
569 PseudoSourceValue::getStack(), LocMemOffset);
570 }
571
572 /// LowerCALL - Lowering a ISD::CALL node into a callseq_start <-
573 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
574 /// nodes.
575 SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
576 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
577 MVT RetVT = TheCall->getRetValType(0);
578 SDValue Chain = TheCall->getChain();
579 unsigned CC = TheCall->getCallingConv();
580 assert((CC == CallingConv::C ||
581 CC == CallingConv::Fast) && "unknown calling convention");
582 bool isVarArg = TheCall->isVarArg();
583 SDValue Callee = TheCall->getCallee();
584 DebugLoc dl = TheCall->getDebugLoc();
585
586 // Analyze operands of the call, assigning locations to each operand.
587 SmallVector<CCValAssign, 16> ArgLocs;
588 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
589 CCInfo.AnalyzeCallOperands(TheCall, CC_ARM);
590
591 // Get a count of how many bytes are to be pushed on the stack.
592 unsigned NumBytes = CCInfo.getNextStackOffset();
593
594 // Adjust the stack pointer for the new arguments...
595 // These operations are automatically eliminated by the prolog/epilog pass
596 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
597
598 SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
599
600 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
601 SmallVector<SDValue, 8> MemOpChains;
602
603 // Walk the register/memloc assignments, inserting copies/loads. In the case
604 // of tail call optimization, arguments are handled later.
605 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
606 i != e;
607 ++i, ++realArgIdx) {
608 CCValAssign &VA = ArgLocs[i];
609 SDValue Arg = TheCall->getArg(realArgIdx);
610 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(realArgIdx);
611
612 // Promote the value if needed.
613 switch (VA.getLocInfo()) {
614 default: assert(0 && "Unknown loc info!");
615 case CCValAssign::Full: break;
616 case CCValAssign::SExt:
617 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
618 break;
619 case CCValAssign::ZExt:
620 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
621 break;
622 case CCValAssign::AExt:
623 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
624 break;
625 case CCValAssign::BCvt:
626 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
627 break;
628 }
629
630 // f64 is passed in i32 pairs and must be combined
631 if (VA.needsCustom()) {
632 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
633 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
634 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
635 VA = ArgLocs[++i]; // skip ahead to next loc
636 if (VA.isRegLoc())
637 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(1)));
638 else {
639 assert(VA.isMemLoc());
640 if (StackPtr.getNode() == 0)
641 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
642
643 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
644 Chain, fmrrd.getValue(1),
645 Flags));
646 }
647 } else if (VA.isRegLoc()) {
648 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
649 } else {
650 assert(VA.isMemLoc());
651 if (StackPtr.getNode() == 0)
652 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
653
654 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
655 Chain, Arg, Flags));
656 }
657 }
658
659 if (!MemOpChains.empty())
660 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
661 &MemOpChains[0], MemOpChains.size());
662
663 // Build a sequence of copy-to-reg nodes chained together with token chain
664 // and flag operands which copy the outgoing args into the appropriate regs.
665 SDValue InFlag;
666 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
667 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
668 RegsToPass[i].second, InFlag);
669 InFlag = Chain.getValue(1);
670 }
671
672 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
673 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
674 // node so that legalize doesn't hack it.
675 bool isDirect = false;
676 bool isARMFunc = false;
677 bool isLocalARMFunc = false;
678 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
679 GlobalValue *GV = G->getGlobal();
680 isDirect = true;
681 bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() ||
682 GV->hasLinkOnceLinkage());
683 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
684 getTargetMachine().getRelocationModel() != Reloc::Static;
685 isARMFunc = !Subtarget->isThumb() || isStub;
686 // ARM call to a local ARM function is predicable.
687 isLocalARMFunc = !Subtarget->isThumb() && !isExt;
688 // tBX takes a register source operand.
689 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
690 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
691 ARMCP::CPStub, 4);
692 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
693 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
694 Callee = DAG.getLoad(getPointerTy(), dl,
695 DAG.getEntryNode(), CPAddr, NULL, 0);
696 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
697 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
698 getPointerTy(), Callee, PICLabel);
699 } else
700 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
701 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
702 isDirect = true;
703 bool isStub = Subtarget->isTargetDarwin() &&
704 getTargetMachine().getRelocationModel() != Reloc::Static;
705 isARMFunc = !Subtarget->isThumb() || isStub;
706 // tBX takes a register source operand.
707 const char *Sym = S->getSymbol();
708 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
709 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
710 ARMCP::CPStub, 4);
711 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
712 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
713 Callee = DAG.getLoad(getPointerTy(), dl,
714 DAG.getEntryNode(), CPAddr, NULL, 0);
715 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
716 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
717 getPointerTy(), Callee, PICLabel);
718 } else
719 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
720 }
721
722 // FIXME: handle tail calls differently.
723 unsigned CallOpc;
724 if (Subtarget->isThumb()) {
725 if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc))
726 CallOpc = ARMISD::CALL_NOLINK;
727 else
728 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
729 } else {
730 CallOpc = (isDirect || Subtarget->hasV5TOps())
731 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
732 : ARMISD::CALL_NOLINK;
733 }
734 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) {
735 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
736 Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
737 InFlag = Chain.getValue(1);
738 }
739
740 std::vector<SDValue> Ops;
741 Ops.push_back(Chain);
742 Ops.push_back(Callee);
743
744 // Add argument registers to the end of the list so that they are known live
745 // into the call.
746 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
747 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
748 RegsToPass[i].second.getValueType()));
749
750 if (InFlag.getNode())
751 Ops.push_back(InFlag);
752 // Returns a chain and a flag for retval copy to use.
753 Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
754 &Ops[0], Ops.size());
755 InFlag = Chain.getValue(1);
756
757 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
758 DAG.getIntPtrConstant(0, true), InFlag);
759 if (RetVT != MVT::Other)
760 InFlag = Chain.getValue(1);
761
762 // Handle result values, copying them out of physregs into vregs that we
763 // return.
764 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
765 Op.getResNo());
766 }
767
768 SDValue ARMTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
769 // The chain is always operand #0
770 SDValue Chain = Op.getOperand(0);
771 DebugLoc dl = Op.getDebugLoc();
772
773 // CCValAssign - represent the assignment of the return value to a location.
774 SmallVector<CCValAssign, 16> RVLocs;
775 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
776 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
777
778 // CCState - Info about the registers and stack slots.
779 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
780
781 // Analyze return values of ISD::RET.
782 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_ARM);
783
784 // If this is the first return lowered for this function, add
785 // the regs to the liveout set for the function.
786 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
787 for (unsigned i = 0; i != RVLocs.size(); ++i)
788 if (RVLocs[i].isRegLoc())
789 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
790 }
791
792 SDValue Flag;
793
794 // Copy the result values into the output registers.
795 for (unsigned i = 0, realRVLocIdx = 0;
796 i != RVLocs.size();
797 ++i, ++realRVLocIdx) {
798 CCValAssign &VA = RVLocs[i];
799 assert(VA.isRegLoc() && "Can only return in registers!");
800
801 // ISD::RET => ret chain, (regnum1,val1), ...
802 // So i*2+1 index only the regnums
803 SDValue Arg = Op.getOperand(realRVLocIdx*2+1);
804
805 switch (VA.getLocInfo()) {
806 default: assert(0 && "Unknown loc info!");
807 case CCValAssign::Full: break;
808 case CCValAssign::BCvt:
809 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
810 break;
811 }
812
813 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
814 // available.
815 if (VA.needsCustom()) {
816 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
817 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
818 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
819 Flag = Chain.getValue(1);
820 VA = RVLocs[++i]; // skip ahead to next loc
821 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
822 Flag);
823 } else
824 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
825
826 // Guarantee that all emitted copies are
827 // stuck together, avoiding something bad.
828 Flag = Chain.getValue(1);
829 }
830
831 SDValue result;
832 if (Flag.getNode())
833 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
834 else // Return Void
835 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
836
837 return result;
838 }
839
840 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
841 // their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is
842 // one of the above mentioned nodes. It has to be wrapped because otherwise
843 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
844 // be used to form addressing mode. These wrapped nodes will be selected
845 // into MOVi.
846 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
847 MVT PtrVT = Op.getValueType();
848 // FIXME there is no actual debug info here
849 DebugLoc dl = Op.getDebugLoc();
850 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
851 SDValue Res;
852 if (CP->isMachineConstantPoolEntry())
853 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
854 CP->getAlignment());
855 else
856 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
857 CP->getAlignment());
858 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
859 }
860
861 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
862 SDValue
863 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
864 SelectionDAG &DAG) {
865 DebugLoc dl = GA->getDebugLoc();
866 MVT PtrVT = getPointerTy();
867 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
868 ARMConstantPoolValue *CPV =
869 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
870 PCAdj, "tlsgd", true);
871 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
872 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
873 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0);
874 SDValue Chain = Argument.getValue(1);
875
876 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
877 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
878
879 // call __tls_get_addr.
880 ArgListTy Args;
881 ArgListEntry Entry;
882 Entry.Node = Argument;
883 Entry.Ty = (const Type *) Type::Int32Ty;
884 Args.push_back(Entry);
885 // FIXME: is there useful debug info available here?
886 std::pair<SDValue, SDValue> CallResult =
887 LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false, false,
888 CallingConv::C, false,
889 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
890 return CallResult.first;
891 }
892
893 // Lower ISD::GlobalTLSAddress using the "initial exec" or
894 // "local exec" model.
895 SDValue
896 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
897 SelectionDAG &DAG) {
898 GlobalValue *GV = GA->getGlobal();
899 DebugLoc dl = GA->getDebugLoc();
900 SDValue Offset;
901 SDValue Chain = DAG.getEntryNode();
902 MVT PtrVT = getPointerTy();
903 // Get the Thread Pointer
904 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
905
906 if (GV->isDeclaration()){
907 // initial exec model
908 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
909 ARMConstantPoolValue *CPV =
910 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
911 PCAdj, "gottpoff", true);
912 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
913 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
914 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
915 Chain = Offset.getValue(1);
916
917 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
918 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
919
920 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
921 } else {
922 // local exec model
923 ARMConstantPoolValue *CPV =
924 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
925 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
926 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
927 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
928 }
929
930 // The address of the thread local variable is the add of the thread
931 // pointer with the offset of the variable.
932 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
933 }
934
935 SDValue
936 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
937 // TODO: implement the "local dynamic" model
938 assert(Subtarget->isTargetELF() &&
939 "TLS not implemented for non-ELF targets");
940 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
941 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
942 // otherwise use the "Local Exec" TLS Model
943 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
944 return LowerToTLSGeneralDynamicModel(GA, DAG);
945 else
946 return LowerToTLSExecModels(GA, DAG);
947 }
948
949 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
950 SelectionDAG &DAG) {
951 MVT PtrVT = getPointerTy();
952 DebugLoc dl = Op.getDebugLoc();
953 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
954 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
955 if (RelocM == Reloc::PIC_) {
956 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
957 ARMConstantPoolValue *CPV =
958 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
959 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
960 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
961 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
962 CPAddr, NULL, 0);
963 SDValue Chain = Result.getValue(1);
964 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
965 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
966 if (!UseGOTOFF)
967 Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
968 return Result;
969 } else {
970 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
971 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
972 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
973 }
974 }
975
976 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
977 /// even in non-static mode.
978 static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) {
979 // If symbol visibility is hidden, the extra load is not needed if
980 // the symbol is definitely defined in the current translation unit.
981 bool isDecl = GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode();
982 if (GV->hasHiddenVisibility() && (!isDecl && !GV->hasCommonLinkage()))
983 return false;
984 return RelocM != Reloc::Static && (isDecl || GV->isWeakForLinker());
985 }
986
987 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
988 SelectionDAG &DAG) {
989 MVT PtrVT = getPointerTy();
990 DebugLoc dl = Op.getDebugLoc();
991 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
992 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
993 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
994 SDValue CPAddr;
995 if (RelocM == Reloc::Static)
996 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
997 else {
998 unsigned PCAdj = (RelocM != Reloc::PIC_)
999 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1000 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr
1001 : ARMCP::CPValue;
1002 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
1003 Kind, PCAdj);
1004 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1005 }
1006 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1007
1008 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1009 SDValue Chain = Result.getValue(1);
1010
1011 if (RelocM == Reloc::PIC_) {
1012 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1013 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1014 }
1015 if (IsIndirect)
1016 Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
1017
1018 return Result;
1019 }
1020
1021 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1022 SelectionDAG &DAG){
1023 assert(Subtarget->isTargetELF() &&
1024 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1025 MVT PtrVT = getPointerTy();
1026 DebugLoc dl = Op.getDebugLoc();
1027 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1028 ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_",
1029 ARMPCLabelIndex,
1030 ARMCP::CPValue, PCAdj);
1031 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1032 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1033 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1034 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1035 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1036 }
1037
1038 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
1039 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1040 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1041 switch (IntNo) {
1042 default: return SDValue(); // Don't custom lower most intrinsics.
1043 case Intrinsic::arm_thread_pointer:
1044 return DAG.getNode(ARMISD::THREAD_POINTER, DebugLoc::getUnknownLoc(),
1045 PtrVT);
1046 }
1047 }
1048
1049 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
1050 unsigned VarArgsFrameIndex) {
1051 // vastart just stores the address of the VarArgsFrameIndex slot into the
1052 // memory location argument.
1053 DebugLoc dl = Op.getDebugLoc();
1054 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1055 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1056 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1057 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
1058 }
1059
1060 SDValue
1061 ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
1062 MachineFunction &MF = DAG.getMachineFunction();
1063 MachineFrameInfo *MFI = MF.getFrameInfo();
1064
1065 SDValue Root = Op.getOperand(0);
1066 DebugLoc dl = Op.getDebugLoc();
1067 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1068 unsigned CC = MF.getFunction()->getCallingConv();
1069 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1070
1071 // Assign locations to all of the incoming arguments.
1072 SmallVector<CCValAssign, 16> ArgLocs;
1073 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1074 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_ARM);
1075
1076 SmallVector<SDValue, 16> ArgValues;
1077
1078 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1079 CCValAssign &VA = ArgLocs[i];
1080
1081 // Arguments stored in registers.
1082 if (VA.isRegLoc()) {
1083 MVT RegVT = VA.getLocVT();
1084 TargetRegisterClass *RC;
1085 if (AFI->isThumbFunction())
1086 RC = ARM::tGPRRegisterClass;
1087 else
1088 RC = ARM::GPRRegisterClass;
1089
1090 if (RegVT == MVT::f64) {
1091 // f64 is passed in pairs of GPRs and must be combined.
1092 RegVT = MVT::i32;
1093 } else if (!((RegVT == MVT::i32) || (RegVT == MVT::f32)))
1094 assert(0 && "RegVT not supported by FORMAL_ARGUMENTS Lowering");
1095
1096 // Transform the arguments stored in physical registers into virtual ones.
1097 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1098 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
1099
1100 // f64 is passed in i32 pairs and must be combined.
1101 if (VA.needsCustom()) {
1102 SDValue ArgValue2;
1103
1104 VA = ArgLocs[++i]; // skip ahead to next loc
1105 if (VA.isMemLoc()) {
1106 // must be APCS to split like this
1107 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1108 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset());
1109
1110 // Create load node to retrieve arguments from the stack.
1111 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1112 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0);
1113 } else {
1114 Reg = MF.addLiveIn(VA.getLocReg(), RC);
1115 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1116 }
1117
1118 ArgValue = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64,
1119 ArgValue, ArgValue2);
1120 }
1121
1122 // If this is an 8 or 16-bit value, it is really passed promoted
1123 // to 32 bits. Insert an assert[sz]ext to capture this, then
1124 // truncate to the right size.
1125 switch (VA.getLocInfo()) {
1126 default: assert(0 && "Unknown loc info!");
1127 case CCValAssign::Full: break;
1128 case CCValAssign::BCvt:
1129 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1130 break;
1131 case CCValAssign::SExt:
1132 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1133 DAG.getValueType(VA.getValVT()));
1134 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1135 break;
1136 case CCValAssign::ZExt:
1137 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1138 DAG.getValueType(VA.getValVT()));
1139 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1140 break;
1141 }
1142
1143 ArgValues.push_back(ArgValue);
1144
1145 } else { // VA.isRegLoc()
1146
1147 // sanity check
1148 assert(VA.isMemLoc());
1149 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
1150
1151 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1152 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset());
1153
1154 // Create load nodes to retrieve arguments from the stack.
1155 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1156 ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN, NULL, 0));
1157 }
1158 }
1159
1160 // varargs
1161 if (isVarArg) {
1162 static const unsigned GPRArgRegs[] = {
1163 ARM::R0, ARM::R1, ARM::R2, ARM::R3
1164 };
1165
1166 unsigned NumGPRs = CCInfo.getFirstUnallocated
1167 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
1168
1169 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1170 unsigned VARegSize = (4 - NumGPRs) * 4;
1171 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
1172 unsigned ArgOffset = 0;
1173 if (VARegSaveSize) {
1174 // If this function is vararg, store any remaining integer argument regs
1175 // to their spots on the stack so that they may be loaded by deferencing
1176 // the result of va_next.
1177 AFI->setVarArgsRegSaveSize(VARegSaveSize);
1178 ArgOffset = CCInfo.getNextStackOffset();
1179 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
1180 VARegSaveSize - VARegSize);
1181 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
1182
1183 SmallVector<SDValue, 4> MemOps;
1184 for (; NumGPRs < 4; ++NumGPRs) {
1185 TargetRegisterClass *RC;
1186 if (AFI->isThumbFunction())
1187 RC = ARM::tGPRRegisterClass;
1188 else
1189 RC = ARM::GPRRegisterClass;
1190
1191 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
1192 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
1193 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1194 MemOps.push_back(Store);
1195 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1196 DAG.getConstant(4, getPointerTy()));
1197 }
1198 if (!MemOps.empty())
1199 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1200 &MemOps[0], MemOps.size());
1201 } else
1202 // This will point to the next argument passed via stack.
1203 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
1204 }
1205
1206 ArgValues.push_back(Root);
1207
1208 // Return the new list of results.
1209 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1210 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1211 }
1212
1213 /// isFloatingPointZero - Return true if this is +0.0.
1214 static bool isFloatingPointZero(SDValue Op) {
1215 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1216 return CFP->getValueAPF().isPosZero();
1217 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1218 // Maybe this has already been legalized into the constant pool?
1219 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1220 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
1221 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1222 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1223 return CFP->getValueAPF().isPosZero();
1224 }
1225 }
1226 return false;
1227 }
1228
1229 static bool isLegalCmpImmediate(unsigned C, bool isThumb) {
1230 return ( isThumb && (C & ~255U) == 0) ||
1231 (!isThumb && ARM_AM::getSOImmVal(C) != -1);
1232 }
1233
1234 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1235 /// the given operands.
1236 static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1237 SDValue &ARMCC, SelectionDAG &DAG, bool isThumb,
1238 DebugLoc dl) {
1239 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1240 unsigned C = RHSC->getZExtValue();
1241 if (!isLegalCmpImmediate(C, isThumb)) {
1242 // Constant does not fit, try adjusting it by one?
1243 switch (CC) {
1244 default: break;
1245 case ISD::SETLT:
1246 case ISD::SETGE:
1247 if (isLegalCmpImmediate(C-1, isThumb)) {
1248 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1249 RHS = DAG.getConstant(C-1, MVT::i32);
1250 }
1251 break;
1252 case ISD::SETULT:
1253 case ISD::SETUGE:
1254 if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) {
1255 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1256 RHS = DAG.getConstant(C-1, MVT::i32);
1257 }
1258 break;
1259 case ISD::SETLE:
1260 case ISD::SETGT:
1261 if (isLegalCmpImmediate(C+1, isThumb)) {
1262 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1263 RHS = DAG.getConstant(C+1, MVT::i32);
1264 }
1265 break;
1266 case ISD::SETULE:
1267 case ISD::SETUGT:
1268 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) {
1269 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1270 RHS = DAG.getConstant(C+1, MVT::i32);
1271 }
1272 break;
1273 }
1274 }
1275 }
1276
1277 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1278 ARMISD::NodeType CompareType;
1279 switch (CondCode) {
1280 default:
1281 CompareType = ARMISD::CMP;
1282 break;
1283 case ARMCC::EQ:
1284 case ARMCC::NE:
1285 case ARMCC::MI:
1286 case ARMCC::PL:
1287 // Uses only N and Z Flags
1288 CompareType = ARMISD::CMPNZ;
1289 break;
1290 }
1291 ARMCC = DAG.getConstant(CondCode, MVT::i32);
1292 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
1293 }
1294
1295 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1296 static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
1297 DebugLoc dl) {
1298 SDValue Cmp;
1299 if (!isFloatingPointZero(RHS))
1300 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
1301 else
1302 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
1303 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
1304 }
1305
1306 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
1307 const ARMSubtarget *ST) {
1308 MVT VT = Op.getValueType();
1309 SDValue LHS = Op.getOperand(0);
1310 SDValue RHS = Op.getOperand(1);
1311 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1312 SDValue TrueVal = Op.getOperand(2);
1313 SDValue FalseVal = Op.getOperand(3);
1314 DebugLoc dl = Op.getDebugLoc();
1315
1316 if (LHS.getValueType() == MVT::i32) {
1317 SDValue ARMCC;
1318 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1319 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb(), dl);
1320 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
1321 }
1322
1323 ARMCC::CondCodes CondCode, CondCode2;
1324 if (FPCCToARMCC(CC, CondCode, CondCode2))
1325 std::swap(TrueVal, FalseVal);
1326
1327 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1328 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1329 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1330 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
1331 ARMCC, CCR, Cmp);
1332 if (CondCode2 != ARMCC::AL) {
1333 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1334 // FIXME: Needs another CMP because flag can have but one use.
1335 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
1336 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
1337 Result, TrueVal, ARMCC2, CCR, Cmp2);
1338 }
1339 return Result;
1340 }
1341
1342 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
1343 const ARMSubtarget *ST) {
1344 SDValue Chain = Op.getOperand(0);
1345 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1346 SDValue LHS = Op.getOperand(2);
1347 SDValue RHS = Op.getOperand(3);
1348 SDValue Dest = Op.getOperand(4);
1349 DebugLoc dl = Op.getDebugLoc();
1350
1351 if (LHS.getValueType() == MVT::i32) {
1352 SDValue ARMCC;
1353 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1354 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb(), dl);
1355 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
1356 Chain, Dest, ARMCC, CCR,Cmp);
1357 }
1358
1359 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1360 ARMCC::CondCodes CondCode, CondCode2;
1361 if (FPCCToARMCC(CC, CondCode, CondCode2))
1362 // Swap the LHS/RHS of the comparison if needed.
1363 std::swap(LHS, RHS);
1364
1365 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1366 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1367 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1368 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1369 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
1370 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1371 if (CondCode2 != ARMCC::AL) {
1372 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1373 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
1374 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1375 }
1376 return Res;
1377 }
1378
1379 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) {
1380 SDValue Chain = Op.getOperand(0);
1381 SDValue Table = Op.getOperand(1);
1382 SDValue Index = Op.getOperand(2);
1383 DebugLoc dl = Op.getDebugLoc();
1384
1385 MVT PTy = getPointerTy();
1386 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1387 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1388 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
1389 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1390 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
1391 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
1392 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
1393 bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1394 Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy, dl,
1395 Chain, Addr, NULL, 0);
1396 Chain = Addr.getValue(1);
1397 if (isPIC)
1398 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
1399 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1400 }
1401
1402 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1403 DebugLoc dl = Op.getDebugLoc();
1404 unsigned Opc =
1405 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1406 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
1407 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
1408 }
1409
1410 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1411 MVT VT = Op.getValueType();
1412 DebugLoc dl = Op.getDebugLoc();
1413 unsigned Opc =
1414 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1415
1416 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
1417 return DAG.getNode(Opc, dl, VT, Op);
1418 }
1419
1420 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
1421 // Implement fcopysign with a fabs and a conditional fneg.
1422 SDValue Tmp0 = Op.getOperand(0);
1423 SDValue Tmp1 = Op.getOperand(1);
1424 DebugLoc dl = Op.getDebugLoc();
1425 MVT VT = Op.getValueType();
1426 MVT SrcVT = Tmp1.getValueType();
1427 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
1428 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
1429 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1430 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1431 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
1432 }
1433
1434 SDValue
1435 ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1436 SDValue Chain,
1437 SDValue Dst, SDValue Src,
1438 SDValue Size, unsigned Align,
1439 bool AlwaysInline,
1440 const Value *DstSV, uint64_t DstSVOff,
1441 const Value *SrcSV, uint64_t SrcSVOff){
1442 // Do repeated 4-byte loads and stores. To be improved.
1443 // This requires 4-byte alignment.
1444 if ((Align & 3) != 0)
1445 return SDValue();
1446 // This requires the copy size to be a constant, preferrably
1447 // within a subtarget-specific limit.
1448 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
1449 if (!ConstantSize)
1450 return SDValue();
1451 uint64_t SizeVal = ConstantSize->getZExtValue();
1452 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
1453 return SDValue();
1454
1455 unsigned BytesLeft = SizeVal & 3;
1456 unsigned NumMemOps = SizeVal >> 2;
1457 unsigned EmittedNumMemOps = 0;
1458 MVT VT = MVT::i32;
1459 unsigned VTSize = 4;
1460 unsigned i = 0;
1461 const unsigned MAX_LOADS_IN_LDM = 6;
1462 SDValue TFOps[MAX_LOADS_IN_LDM];
1463 SDValue Loads[MAX_LOADS_IN_LDM];
1464 uint64_t SrcOff = 0, DstOff = 0;
1465
1466 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
1467 // same number of stores. The loads and stores will get combined into
1468 // ldm/stm later on.
1469 while (EmittedNumMemOps < NumMemOps) {
1470 for (i = 0;
1471 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1472 Loads[i] = DAG.getLoad(VT, dl, Chain,
1473 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
1474 DAG.getConstant(SrcOff, MVT::i32)),
1475 SrcSV, SrcSVOff + SrcOff);
1476 TFOps[i] = Loads[i].getValue(1);
1477 SrcOff += VTSize;
1478 }
1479 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1480
1481 for (i = 0;
1482 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1483 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
1484 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
1485 DAG.getConstant(DstOff, MVT::i32)),
1486 DstSV, DstSVOff + DstOff);
1487 DstOff += VTSize;
1488 }
1489 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1490
1491 EmittedNumMemOps += i;
1492 }
1493
1494 if (BytesLeft == 0)
1495 return Chain;
1496
1497 // Issue loads / stores for the trailing (1 - 3) bytes.
1498 unsigned BytesLeftSave = BytesLeft;
1499 i = 0;
1500 while (BytesLeft) {
1501 if (BytesLeft >= 2) {
1502 VT = MVT::i16;
1503 VTSize = 2;
1504 } else {
1505 VT = MVT::i8;
1506 VTSize = 1;
1507 }
1508
1509 Loads[i] = DAG.getLoad(VT, dl, Chain,
1510 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
1511 DAG.getConstant(SrcOff, MVT::i32)),
1512 SrcSV, SrcSVOff + SrcOff);
1513 TFOps[i] = Loads[i].getValue(1);
1514 ++i;
1515 SrcOff += VTSize;
1516 BytesLeft -= VTSize;
1517 }
1518 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1519
1520 i = 0;
1521 BytesLeft = BytesLeftSave;
1522 while (BytesLeft) {
1523 if (BytesLeft >= 2) {
1524 VT = MVT::i16;
1525 VTSize = 2;
1526 } else {
1527 VT = MVT::i8;
1528 VTSize = 1;
1529 }
1530
1531 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
1532 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
1533 DAG.getConstant(DstOff, MVT::i32)),
1534 DstSV, DstSVOff + DstOff);
1535 ++i;
1536 DstOff += VTSize;
1537 BytesLeft -= VTSize;
1538 }
1539 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1540 }
1541
1542 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
1543 SDValue Op = N->getOperand(0);
1544 DebugLoc dl = N->getDebugLoc();
1545 if (N->getValueType(0) == MVT::f64) {
1546 // Turn i64->f64 into FMDRR.
1547 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
1548 DAG.getConstant(0, MVT::i32));
1549 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
1550 DAG.getConstant(1, MVT::i32));
1551 return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
1552 }
1553
1554 // Turn f64->i64 into FMRRD.
1555 SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl,
1556 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
1557
1558 // Merge the pieces into a single i64 value.
1559 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
1560 }
1561
1562 static SDValue ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) {
1563 assert(N->getValueType(0) == MVT::i64 &&
1564 (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
1565 "Unknown shift to lower!");
1566
1567 // We only lower SRA, SRL of 1 here, all others use generic lowering.
1568 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
1569 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
1570 return SDValue();
1571
1572 // If we are in thumb mode, we don't have RRX.
1573 if (ST->isThumb()) return SDValue();
1574
1575 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
1576 DebugLoc dl = N->getDebugLoc();
1577 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
1578 DAG.getConstant(0, MVT::i32));
1579 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
1580 DAG.getConstant(1, MVT::i32));
1581
1582 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
1583 // captures the result into a carry flag.
1584 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
1585 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
1586
1587 // The low part is an ARMISD::RRX operand, which shifts the carry in.
1588 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
1589
1590 // Merge the pieces into a single i64 value.
1591 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
1592 }
1593
1594 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
1595 switch (Op.getOpcode()) {
1596 default: assert(0 && "Don't know how to custom lower this!"); abort();
1597 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1598 case ISD::GlobalAddress:
1599 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
1600 LowerGlobalAddressELF(Op, DAG);
1601 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
1602 case ISD::CALL: return LowerCALL(Op, DAG);
1603 case ISD::RET: return LowerRET(Op, DAG);
1604 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget);
1605 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget);
1606 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
1607 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
1608 case ISD::SINT_TO_FP:
1609 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
1610 case ISD::FP_TO_SINT:
1611 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
1612 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
1613 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
1614 case ISD::RETURNADDR: break;
1615 case ISD::FRAMEADDR: break;
1616 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
1617 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1618 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
1619 case ISD::SRL:
1620 case ISD::SRA: return ExpandSRx(Op.getNode(), DAG,Subtarget);
1621 }
1622 return SDValue();
1623 }
1624
1625 /// ReplaceNodeResults - Replace the results of node with an illegal result
1626 /// type with new values built out of custom code.
1627 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
1628 SmallVectorImpl<SDValue>&Results,
1629 SelectionDAG &DAG) {
1630 switch (N->getOpcode()) {
1631 default:
1632 assert(0 && "Don't know how to custom expand this!");
1633 return;
1634 case ISD::BIT_CONVERT:
1635 Results.push_back(ExpandBIT_CONVERT(N, DAG));
1636 return;
1637 case ISD::SRL:
1638 case ISD::SRA: {
1639 SDValue Res = ExpandSRx(N, DAG, Subtarget);
1640 if (Res.getNode())
1641 Results.push_back(Res);
1642 return;
1643 }
1644 }
1645 }
1646
1647 //===----------------------------------------------------------------------===//
1648 // ARM Scheduler Hooks
1649 //===----------------------------------------------------------------------===//
1650
1651 MachineBasicBlock *
1652 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1653 MachineBasicBlock *BB) const {
1654 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1655 DebugLoc dl = MI->getDebugLoc();
1656 switch (MI->getOpcode()) {
1657 default: assert(false && "Unexpected instr type to insert");
1658 case ARM::tMOVCCr: {
1659 // To "insert" a SELECT_CC instruction, we actually have to insert the
1660 // diamond control-flow pattern. The incoming instruction knows the
1661 // destination vreg to set, the condition code register to branch on, the
1662 // true/false values to select between, and a branch opcode to use.
1663 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1664 MachineFunction::iterator It = BB;
1665 ++It;
1666
1667 // thisMBB:
1668 // ...
1669 // TrueVal = ...
1670 // cmpTY ccX, r1, r2
1671 // bCC copy1MBB
1672 // fallthrough --> copy0MBB
1673 MachineBasicBlock *thisMBB = BB;
1674 MachineFunction *F = BB->getParent();
1675 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1676 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1677 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
1678 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
1679 F->insert(It, copy0MBB);
1680 F->insert(It, sinkMBB);
1681 // Update machine-CFG edges by first adding all successors of the current
1682 // block to the new block which will contain the Phi node for the select.
1683 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
1684 e = BB->succ_end(); i != e; ++i)
1685 sinkMBB->addSuccessor(*i);
1686 // Next, remove all successors of the current block, and add the true
1687 // and fallthrough blocks as its successors.
1688 while(!BB->succ_empty())
1689 BB->removeSuccessor(BB->succ_begin());
1690 BB->addSuccessor(copy0MBB);
1691 BB->addSuccessor(sinkMBB);
1692
1693 // copy0MBB:
1694 // %FalseValue = ...
1695 // # fallthrough to sinkMBB
1696 BB = copy0MBB;
1697
1698 // Update machine-CFG edges
1699 BB->addSuccessor(sinkMBB);
1700
1701 // sinkMBB:
1702 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1703 // ...
1704 BB = sinkMBB;
1705 BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
1706 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
1707 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1708
1709 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
1710 return BB;
1711 }
1712 }
1713 }
1714
1715 //===----------------------------------------------------------------------===//
1716 // ARM Optimization Hooks
1717 //===----------------------------------------------------------------------===//
1718
1719 static
1720 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
1721 TargetLowering::DAGCombinerInfo &DCI) {
1722 SelectionDAG &DAG = DCI.DAG;
1723 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1724 MVT VT = N->getValueType(0);
1725 unsigned Opc = N->getOpcode();
1726 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
1727 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
1728 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
1729 ISD::CondCode CC = ISD::SETCC_INVALID;
1730
1731 if (isSlctCC) {
1732 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
1733 } else {
1734 SDValue CCOp = Slct.getOperand(0);
1735 if (CCOp.getOpcode() == ISD::SETCC)
1736 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
1737 }
1738
1739 bool DoXform = false;
1740 bool InvCC = false;
1741 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
1742 "Bad input!");
1743
1744 if (LHS.getOpcode() == ISD::Constant &&
1745 cast<ConstantSDNode>(LHS)->isNullValue()) {
1746 DoXform = true;
1747 } else if (CC != ISD::SETCC_INVALID &&
1748 RHS.getOpcode() == ISD::Constant &&
1749 cast<ConstantSDNode>(RHS)->isNullValue()) {
1750 std::swap(LHS, RHS);
1751 SDValue Op0 = Slct.getOperand(0);
1752 MVT OpVT = isSlctCC ? Op0.getValueType() :
1753 Op0.getOperand(0).getValueType();
1754 bool isInt = OpVT.isInteger();
1755 CC = ISD::getSetCCInverse(CC, isInt);
1756
1757 if (!TLI.isCondCodeLegal(CC, OpVT))
1758 return SDValue(); // Inverse operator isn't legal.
1759
1760 DoXform = true;
1761 InvCC = true;
1762 }
1763
1764 if (DoXform) {
1765 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
1766 if (isSlctCC)
1767 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
1768 Slct.getOperand(0), Slct.getOperand(1), CC);
1769 SDValue CCOp = Slct.getOperand(0);
1770 if (InvCC)
1771 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
1772 CCOp.getOperand(0), CCOp.getOperand(1), CC);
1773 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
1774 CCOp, OtherOp, Result);
1775 }
1776 return SDValue();
1777 }
1778
1779 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
1780 static SDValue PerformADDCombine(SDNode *N,
1781 TargetLowering::DAGCombinerInfo &DCI) {
1782 // added by evan in r37685 with no testcase.
1783 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
1784
1785 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
1786 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
1787 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
1788 if (Result.getNode()) return Result;
1789 }
1790 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
1791 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
1792 if (Result.getNode()) return Result;
1793 }
1794
1795 return SDValue();
1796 }
1797
1798 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
1799 static SDValue PerformSUBCombine(SDNode *N,
1800 TargetLowering::DAGCombinerInfo &DCI) {
1801 // added by evan in r37685 with no testcase.
1802 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
1803
1804 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1805 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
1806 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
1807 if (Result.getNode()) return Result;
1808 }
1809
1810 return SDValue();
1811 }
1812
1813
1814 /// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
1815 static SDValue PerformFMRRDCombine(SDNode *N,
1816 TargetLowering::DAGCombinerInfo &DCI) {
1817 // fmrrd(fmdrr x, y) -> x,y
1818 SDValue InDouble = N->getOperand(0);
1819 if (InDouble.getOpcode() == ARMISD::FMDRR)
1820 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
1821 return SDValue();
1822 }
1823
1824 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
1825 DAGCombinerInfo &DCI) const {
1826 switch (N->getOpcode()) {
1827 default: break;
1828 case ISD::ADD: return PerformADDCombine(N, DCI);
1829 case ISD::SUB: return PerformSUBCombine(N, DCI);
1830 case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
1831 }
1832
1833 return SDValue();
1834 }
1835
1836 /// isLegalAddressImmediate - Return true if the integer value can be used
1837 /// as the offset of the target addressing mode for load / store of the
1838 /// given type.
1839 static bool isLegalAddressImmediate(int64_t V, MVT VT,
1840 const ARMSubtarget *Subtarget) {
1841 if (V == 0)
1842 return true;
1843
1844 if (!VT.isSimple())
1845 return false;
1846
1847 if (Subtarget->isThumb()) {
1848 if (V < 0)
1849 return false;
1850
1851 unsigned Scale = 1;
1852 switch (VT.getSimpleVT()) {
1853 default: return false;
1854 case MVT::i1:
1855 case MVT::i8:
1856 // Scale == 1;
1857 break;
1858 case MVT::i16:
1859 // Scale == 2;
1860 Scale = 2;
1861 break;
1862 case MVT::i32:
1863 // Scale == 4;
1864 Scale = 4;
1865 break;
1866 }
1867
1868 if ((V & (Scale - 1)) != 0)
1869 return false;
1870 V /= Scale;
1871 return V == (V & ((1LL << 5) - 1));
1872 }
1873
1874 if (V < 0)
1875 V = - V;
1876 switch (VT.getSimpleVT()) {
1877 default: return false;
1878 case MVT::i1:
1879 case MVT::i8:
1880 case MVT::i32:
1881 // +- imm12
1882 return V == (V & ((1LL << 12) - 1));
1883 case MVT::i16:
1884 // +- imm8
1885 return V == (V & ((1LL << 8) - 1));
1886 case MVT::f32:
1887 case MVT::f64:
1888 if (!Subtarget->hasVFP2())
1889 return false;
1890 if ((V & 3) != 0)
1891 return false;
1892 V >>= 2;
1893 return V == (V & ((1LL << 8) - 1));
1894 }
1895 }
1896
1897 /// isLegalAddressingMode - Return true if the addressing mode represented
1898 /// by AM is legal for this target, for a load/store of the specified type.
1899 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
1900 const Type *Ty) const {
1901 MVT VT = getValueType(Ty, true);
1902 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
1903 return false;
1904
1905 // Can never fold addr of global into load/store.
1906 if (AM.BaseGV)
1907 return false;
1908
1909 switch (AM.Scale) {
1910 case 0: // no scale reg, must be "r+i" or "r", or "i".
1911 break;
1912 case 1:
1913 if (Subtarget->isThumb())
1914 return false;
1915 // FALL THROUGH.
1916 default:
1917 // ARM doesn't support any R+R*scale+imm addr modes.
1918 if (AM.BaseOffs)
1919 return false;
1920
1921 if (!VT.isSimple())
1922 return false;
1923
1924 int Scale = AM.Scale;
1925 switch (VT.getSimpleVT()) {
1926 default: return false;
1927 case MVT::i1:
1928 case MVT::i8:
1929 case MVT::i32:
1930 case MVT::i64:
1931 // This assumes i64 is legalized to a pair of i32. If not (i.e.
1932 // ldrd / strd are used, then its address mode is same as i16.
1933 // r + r
1934 if (Scale < 0) Scale = -Scale;
1935 if (Scale == 1)
1936 return true;
1937 // r + r << imm
1938 return isPowerOf2_32(Scale & ~1);
1939 case MVT::i16:
1940 // r + r
1941 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
1942 return true;
1943 return false;
1944
1945 case MVT::isVoid:
1946 // Note, we allow "void" uses (basically, uses that aren't loads or
1947 // stores), because arm allows folding a scale into many arithmetic
1948 // operations. This should be made more precise and revisited later.
1949
1950 // Allow r << imm, but the imm has to be a multiple of two.
1951 if (AM.Scale & 1) return false;
1952 return isPowerOf2_32(AM.Scale);
1953 }
1954 break;
1955 }
1956 return true;
1957 }
1958
1959 static bool getIndexedAddressParts(SDNode *Ptr, MVT VT,
1960 bool isSEXTLoad, SDValue &Base,
1961 SDValue &Offset, bool &isInc,
1962 SelectionDAG &DAG) {
1963 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
1964 return false;
1965
1966 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
1967 // AddressingMode 3
1968 Base = Ptr->getOperand(0);
1969 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1970 int RHSC = (int)RHS->getZExtValue();
1971 if (RHSC < 0 && RHSC > -256) {
1972 isInc = false;
1973 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1974 return true;
1975 }
1976 }
1977 isInc = (Ptr->getOpcode() == ISD::ADD);
1978 Offset = Ptr->getOperand(1);
1979 return true;
1980 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
1981 // AddressingMode 2
1982 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1983 int RHSC = (int)RHS->getZExtValue();
1984 if (RHSC < 0 && RHSC > -0x1000) {
1985 isInc = false;
1986 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1987 Base = Ptr->getOperand(0);
1988 return true;
1989 }
1990 }
1991
1992 if (Ptr->getOpcode() == ISD::ADD) {
1993 isInc = true;
1994 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
1995 if (ShOpcVal != ARM_AM::no_shift) {
1996 Base = Ptr->getOperand(1);
1997 Offset = Ptr->getOperand(0);
1998 } else {
1999 Base = Ptr->getOperand(0);
2000 Offset = Ptr->getOperand(1);
2001 }
2002 return true;
2003 }
2004
2005 isInc = (Ptr->getOpcode() == ISD::ADD);
2006 Base = Ptr->getOperand(0);
2007 Offset = Ptr->getOperand(1);
2008 return true;
2009 }
2010
2011 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
2012 return false;
2013 }
2014
2015 /// getPreIndexedAddressParts - returns true by value, base pointer and
2016 /// offset pointer and addressing mode by reference if the node's address
2017 /// can be legally represented as pre-indexed load / store address.
2018 bool
2019 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
2020 SDValue &Offset,
2021 ISD::MemIndexedMode &AM,
2022 SelectionDAG &DAG) const {
2023 if (Subtarget->isThumb())
2024 return false;
2025
2026 MVT VT;
2027 SDValue Ptr;
2028 bool isSEXTLoad = false;
2029 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2030 Ptr = LD->getBasePtr();
2031 VT = LD->getMemoryVT();
2032 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
2033 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2034 Ptr = ST->getBasePtr();
2035 VT = ST->getMemoryVT();
2036 } else
2037 return false;
2038
2039 bool isInc;
2040 bool isLegal = getIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, Offset,
2041 isInc, DAG);
2042 if (isLegal) {
2043 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
2044 return true;
2045 }
2046 return false;
2047 }
2048
2049 /// getPostIndexedAddressParts - returns true by value, base pointer and
2050 /// offset pointer and addressing mode by reference if this node can be
2051 /// combined with a load / store to form a post-indexed load / store.
2052 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
2053 SDValue &Base,
2054 SDValue &Offset,
2055 ISD::MemIndexedMode &AM,
2056 SelectionDAG &DAG) const {
2057 if (Subtarget->isThumb())
2058 return false;
2059
2060 MVT VT;
2061 SDValue Ptr;
2062 bool isSEXTLoad = false;
2063 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2064 VT = LD->getMemoryVT();
2065 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
2066 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2067 VT = ST->getMemoryVT();
2068 } else
2069 return false;
2070
2071 bool isInc;
2072 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
2073 isInc, DAG);
2074 if (isLegal) {
2075 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
2076 return true;
2077 }
2078 return false;
2079 }
2080
2081 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
2082 const APInt &Mask,
2083 APInt &KnownZero,
2084 APInt &KnownOne,
2085 const SelectionDAG &DAG,
2086 unsigned Depth) const {
2087 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
2088 switch (Op.getOpcode()) {
2089 default: break;
2090 case ARMISD::CMOV: {
2091 // Bits are known zero/one if known on the LHS and RHS.
2092 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
2093 if (KnownZero == 0 && KnownOne == 0) return;
2094
2095 APInt KnownZeroRHS, KnownOneRHS;
2096 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
2097 KnownZeroRHS, KnownOneRHS, Depth+1);
2098 KnownZero &= KnownZeroRHS;
2099 KnownOne &= KnownOneRHS;
2100 return;
2101 }
2102 }
2103 }
2104
2105 //===----------------------------------------------------------------------===//
2106 // ARM Inline Assembly Support
2107 //===----------------------------------------------------------------------===//
2108
2109 /// getConstraintType - Given a constraint letter, return the type of
2110 /// constraint it is for this target.
2111 ARMTargetLowering::ConstraintType
2112 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
2113 if (Constraint.size() == 1) {
2114 switch (Constraint[0]) {
2115 default: break;
2116 case 'l': return C_RegisterClass;
2117 case 'w': return C_RegisterClass;
2118 }
2119 }
2120 return TargetLowering::getConstraintType(Constraint);
2121 }
2122
2123 std::pair<unsigned, const TargetRegisterClass*>
2124 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
2125 MVT VT) const {
2126 if (Constraint.size() == 1) {
2127 // GCC RS6000 Constraint Letters
2128 switch (Constraint[0]) {
2129 case 'l':
2130 if (Subtarget->isThumb())
2131 return std::make_pair(0U, ARM::tGPRRegisterClass);
2132 else
2133 return std::make_pair(0U, ARM::GPRRegisterClass);
2134 case 'r':
2135 return std::make_pair(0U, ARM::GPRRegisterClass);
2136 case 'w':
2137 if (VT == MVT::f32)
2138 return std::make_pair(0U, ARM::SPRRegisterClass);
2139 if (VT == MVT::f64)
2140 return std::make_pair(0U, ARM::DPRRegisterClass);
2141 break;
2142 }
2143 }
2144 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
2145 }
2146
2147 std::vector<unsigned> ARMTargetLowering::
2148 getRegClassForInlineAsmConstraint(const std::string &Constraint,
2149 MVT VT) const {
2150 if (Constraint.size() != 1)
2151 return std::vector<unsigned>();
2152
2153 switch (Constraint[0]) { // GCC ARM Constraint Letters
2154 default: break;
2155 case 'l':
2156 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
2157 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
2158 0);
2159 case 'r':
2160 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
2161 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
2162 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
2163 ARM::R12, ARM::LR, 0);
2164 case 'w':
2165 if (VT == MVT::f32)
2166 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
2167 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
2168 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
2169 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
2170 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
2171 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
2172 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
2173 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
2174 if (VT == MVT::f64)
2175 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
2176 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
2177 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
2178 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
2179 break;
2180 }
2181
2182 return std::vector<unsigned>();
2183 }
2184
2185 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2186 /// vector. If it is invalid, don't add anything to Ops.
2187 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2188 char Constraint,
2189 bool hasMemory,
2190 std::vector<SDValue>&Ops,
2191 SelectionDAG &DAG) const {
2192 SDValue Result(0, 0);
2193
2194 switch (Constraint) {
2195 default: break;
2196 case 'I': case 'J': case 'K': case 'L':
2197 case 'M': case 'N': case 'O':
2198 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2199 if (!C)
2200 return;
2201
2202 int64_t CVal64 = C->getSExtValue();
2203 int CVal = (int) CVal64;
2204 // None of these constraints allow values larger than 32 bits. Check
2205 // that the value fits in an int.
2206 if (CVal != CVal64)
2207 return;
2208
2209 switch (Constraint) {
2210 case 'I':
2211 if (Subtarget->isThumb()) {
2212 // This must be a constant between 0 and 255, for ADD immediates.
2213 if (CVal >= 0 && CVal <= 255)
2214 break;
2215 } else {
2216 // A constant that can be used as an immediate value in a
2217 // data-processing instruction.
2218 if (ARM_AM::getSOImmVal(CVal) != -1)
2219 break;
2220 }
2221 return;
2222
2223 case 'J':
2224 if (Subtarget->isThumb()) {
2225 // This must be a constant between -255 and -1, for negated ADD
2226 // immediates. This can be used in GCC with an "n" modifier that
2227 // prints the negated value, for use with SUB instructions. It is
2228 // not useful otherwise but is implemented for compatibility.
2229 if (CVal >= -255 && CVal <= -1)
2230 break;
2231 } else {
2232 // This must be a constant between -4095 and 4095. It is not clear
2233 // what this constraint is intended for. Implemented for
2234 // compatibility with GCC.
2235 if (CVal >= -4095 && CVal <= 4095)
2236 break;
2237 }
2238 return;
2239
2240 case 'K':
2241 if (Subtarget->isThumb()) {
2242 // A 32-bit value where only one byte has a nonzero value. Exclude
2243 // zero to match GCC. This constraint is used by GCC internally for
2244 // constants that can be loaded with a move/shift combination.
2245 // It is not useful otherwise but is implemented for compatibility.
2246 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
2247 break;
2248 } else {
2249 // A constant whose bitwise inverse can be used as an immediate
2250 // value in a data-processing instruction. This can be used in GCC
2251 // with a "B" modifier that prints the inverted value, for use with
2252 // BIC and MVN instructions. It is not useful otherwise but is
2253 // implemented for compatibility.
2254 if (ARM_AM::getSOImmVal(~CVal) != -1)
2255 break;
2256 }
2257 return;
2258
2259 case 'L':
2260 if (Subtarget->isThumb()) {
2261 // This must be a constant between -7 and 7,
2262 // for 3-operand ADD/SUB immediate instructions.
2263 if (CVal >= -7 && CVal < 7)
2264 break;
2265 } else {
2266 // A constant whose negation can be used as an immediate value in a
2267 // data-processing instruction. This can be used in GCC with an "n"
2268 // modifier that prints the negated value, for use with SUB
2269 // instructions. It is not useful otherwise but is implemented for
2270 // compatibility.
2271 if (ARM_AM::getSOImmVal(-CVal) != -1)
2272 break;
2273 }
2274 return;
2275
2276 case 'M':
2277 if (Subtarget->isThumb()) {
2278 // This must be a multiple of 4 between 0 and 1020, for
2279 // ADD sp + immediate.
2280 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
2281 break;
2282 } else {
2283 // A power of two or a constant between 0 and 32. This is used in
2284 // GCC for the shift amount on shifted register operands, but it is
2285 // useful in general for any shift amounts.
2286 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
2287 break;
2288 }
2289 return;
2290
2291 case 'N':
2292 if (Subtarget->isThumb()) {
2293 // This must be a constant between 0 and 31, for shift amounts.
2294 if (CVal >= 0 && CVal <= 31)
2295 break;
2296 }
2297 return;
2298
2299 case 'O':
2300 if (Subtarget->isThumb()) {
2301 // This must be a multiple of 4 between -508 and 508, for
2302 // ADD/SUB sp = sp + immediate.
2303 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
2304 break;
2305 }
2306 return;
2307 }
2308 Result = DAG.getTargetConstant(CVal, Op.getValueType());
2309 break;
2310 }
2311
2312 if (Result.getNode()) {
2313 Ops.push_back(Result);
2314 return;
2315 }
2316 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
2317 Ops, DAG);
2318 }
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