lib/Target/Blackfin/BlackfinISelLowering.cpp

   1 //===- BlackfinISelLowering.cpp - Blackfin DAG Lowering Implementation ----===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the interfaces that Blackfin uses to lower LLVM code
  11 // into a selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "BlackfinISelLowering.h"
  16 #include "BlackfinTargetMachine.h"
  17 #include "llvm/Function.h"
  18 #include "llvm/Type.h"
  19 #include "llvm/CodeGen/CallingConvLower.h"
  20 #include "llvm/CodeGen/MachineFrameInfo.h"
  21 #include "llvm/CodeGen/MachineFunction.h"
  22 #include "llvm/CodeGen/MachineInstrBuilder.h"
  23 #include "llvm/CodeGen/MachineRegisterInfo.h"
  24 #include "llvm/CodeGen/PseudoSourceValue.h"
  25 #include "llvm/CodeGen/SelectionDAG.h"
  26 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
  27 #include "llvm/ADT/VectorExtras.h"
  28 #include "llvm/Support/Debug.h"
  29 #include "llvm/Support/ErrorHandling.h"
  30 using namespace llvm;
  31
  32 //===----------------------------------------------------------------------===//
  33 // Calling Convention Implementation
  34 //===----------------------------------------------------------------------===//
  35
  36 #include "BlackfinGenCallingConv.inc"
  37
  38 //===----------------------------------------------------------------------===//
  39 // TargetLowering Implementation
  40 //===----------------------------------------------------------------------===//
  41
  42 BlackfinTargetLowering::BlackfinTargetLowering(TargetMachine &TM)
  43   : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
  44   setBooleanContents(ZeroOrOneBooleanContent);
  45   setStackPointerRegisterToSaveRestore(BF::SP);
  46   setIntDivIsCheap(false);
  47
  48   // Set up the legal register classes.
  49   addRegisterClass(MVT::i32, BF::DRegisterClass);
  50   addRegisterClass(MVT::i16, BF::D16RegisterClass);
  51
  52   computeRegisterProperties();
  53
  54   // Blackfin doesn't have i1 loads or stores
  55   setLoadExtAction(ISD::EXTLOAD,  MVT::i1, Promote);
  56   setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
  57   setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
  58
  59   setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
  60   setOperationAction(ISD::JumpTable,     MVT::i32, Custom);
  61
  62   setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
  63   setOperationAction(ISD::BR_JT,     MVT::Other, Expand);
  64   setOperationAction(ISD::BR_CC,     MVT::Other, Expand);
  65
  66   // i16 registers don't do much
  67   setOperationAction(ISD::AND,   MVT::i16, Promote);
  68   setOperationAction(ISD::OR,    MVT::i16, Promote);
  69   setOperationAction(ISD::XOR,   MVT::i16, Promote);
  70   setOperationAction(ISD::CTPOP, MVT::i16, Promote);
  71   // The expansion of CTLZ/CTTZ uses AND/OR, so we might as well promote
  72   // immediately.
  73   setOperationAction(ISD::CTLZ,  MVT::i16, Promote);
  74   setOperationAction(ISD::CTTZ,  MVT::i16, Promote);
  75   setOperationAction(ISD::SETCC, MVT::i16, Promote);
  76
  77   // Blackfin has no division
  78   setOperationAction(ISD::SDIV,    MVT::i16, Expand);
  79   setOperationAction(ISD::SDIV,    MVT::i32, Expand);
  80   setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
  81   setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
  82   setOperationAction(ISD::SREM,    MVT::i16, Expand);
  83   setOperationAction(ISD::SREM,    MVT::i32, Expand);
  84   setOperationAction(ISD::UDIV,    MVT::i16, Expand);
  85   setOperationAction(ISD::UDIV,    MVT::i32, Expand);
  86   setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
  87   setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
  88   setOperationAction(ISD::UREM,    MVT::i16, Expand);
  89   setOperationAction(ISD::UREM,    MVT::i32, Expand);
  90
  91   setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
  92   setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
  93   setOperationAction(ISD::MULHU,     MVT::i32, Expand);
  94   setOperationAction(ISD::MULHS,     MVT::i32, Expand);
  95
  96   // No carry-in operations.
  97   setOperationAction(ISD::ADDE, MVT::i32, Custom);
  98   setOperationAction(ISD::SUBE, MVT::i32, Custom);
  99
 100   // Blackfin has no intrinsics for these particular operations.
 101   setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
 102   setOperationAction(ISD::BSWAP, MVT::i32, Expand);
 103
 104   setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
 105   setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
 106   setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
 107
 108   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
 109
 110   // i32 has native CTPOP, but not CTLZ/CTTZ
 111   setOperationAction(ISD::CTLZ, MVT::i32, Expand);
 112   setOperationAction(ISD::CTTZ, MVT::i32, Expand);
 113
 114   // READCYCLECOUNTER needs special type legalization.
 115   setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
 116
 117   setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
 118
 119   // Use the default implementation.
 120   setOperationAction(ISD::VACOPY, MVT::Other, Expand);
 121   setOperationAction(ISD::VAEND, MVT::Other, Expand);
 122   setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
 123   setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
 124 }
 125
 126 const char *BlackfinTargetLowering::getTargetNodeName(unsigned Opcode) const {
 127   switch (Opcode) {
 128   default: return 0;
 129   case BFISD::CALL:     return "BFISD::CALL";
 130   case BFISD::RET_FLAG: return "BFISD::RET_FLAG";
 131   case BFISD::Wrapper:  return "BFISD::Wrapper";
 132   }
 133 }
 134
 135 MVT::SimpleValueType BlackfinTargetLowering::getSetCCResultType(EVT VT) const {
 136   // SETCC always sets the CC register. Technically that is an i1 register, but
 137   // that type is not legal, so we treat it as an i32 register.
 138   return MVT::i32;
 139 }
 140
 141 SDValue BlackfinTargetLowering::LowerGlobalAddress(SDValue Op,
 142                                                    SelectionDAG &DAG) const {
 143   DebugLoc DL = Op.getDebugLoc();
 144   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
 145
 146   Op = DAG.getTargetGlobalAddress(GV, DL, MVT::i32);
 147   return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op);
 148 }
 149
 150 SDValue BlackfinTargetLowering::LowerJumpTable(SDValue Op,
 151                                                SelectionDAG &DAG) const {
 152   DebugLoc DL = Op.getDebugLoc();
 153   int JTI = cast<JumpTableSDNode>(Op)->getIndex();
 154
 155   Op = DAG.getTargetJumpTable(JTI, MVT::i32);
 156   return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op);
 157 }
 158
 159 SDValue
 160 BlackfinTargetLowering::LowerFormalArguments(SDValue Chain,
 161                                              CallingConv::ID CallConv, bool isVarArg,
 162                                             const SmallVectorImpl<ISD::InputArg>
 163                                                &Ins,
 164                                              DebugLoc dl, SelectionDAG &DAG,
 165                                              SmallVectorImpl<SDValue> &InVals)
 166                                                const {
 167
 168   MachineFunction &MF = DAG.getMachineFunction();
 169   MachineFrameInfo *MFI = MF.getFrameInfo();
 170
 171   SmallVector<CCValAssign, 16> ArgLocs;
 172   CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
 173                  ArgLocs, *DAG.getContext());
 174   CCInfo.AllocateStack(12, 4);  // ABI requires 12 bytes stack space
 175   CCInfo.AnalyzeFormalArguments(Ins, CC_Blackfin);
 176
 177   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
 178     CCValAssign &VA = ArgLocs[i];
 179
 180     if (VA.isRegLoc()) {
 181       EVT RegVT = VA.getLocVT();
 182       TargetRegisterClass *RC = VA.getLocReg() == BF::P0 ?
 183         BF::PRegisterClass : BF::DRegisterClass;
 184       assert(RC->contains(VA.getLocReg()) && "Unexpected regclass in CCState");
 185       assert(RC->hasType(RegVT) && "Unexpected regclass in CCState");
 186
 187       unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
 188       MF.getRegInfo().addLiveIn(VA.getLocReg(), Reg);
 189       SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
 190
 191       // If this is an 8 or 16-bit value, it is really passed promoted to 32
 192       // bits.  Insert an assert[sz]ext to capture this, then truncate to the
 193       // right size.
 194       if (VA.getLocInfo() == CCValAssign::SExt)
 195         ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
 196                                DAG.getValueType(VA.getValVT()));
 197       else if (VA.getLocInfo() == CCValAssign::ZExt)
 198         ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
 199                                DAG.getValueType(VA.getValVT()));
 200
 201       if (VA.getLocInfo() != CCValAssign::Full)
 202         ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
 203
 204       InVals.push_back(ArgValue);
 205     } else {
 206       assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
 207       unsigned ObjSize = VA.getLocVT().getStoreSize();
 208       int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
 209       SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
 210       InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
 211                                    MachinePointerInfo(),
 212                                    false, false, 0));
 213     }
 214   }
 215
 216   return Chain;
 217 }
 218
 219 SDValue
 220 BlackfinTargetLowering::LowerReturn(SDValue Chain,
 221                                     CallingConv::ID CallConv, bool isVarArg,
 222                                     const SmallVectorImpl<ISD::OutputArg> &Outs,
 223                                     const SmallVectorImpl<SDValue> &OutVals,
 224                                     DebugLoc dl, SelectionDAG &DAG) const {
 225
 226   // CCValAssign - represent the assignment of the return value to locations.
 227   SmallVector<CCValAssign, 16> RVLocs;
 228
 229   // CCState - Info about the registers and stack slot.
 230   CCState CCInfo(CallConv, isVarArg, DAG.getTarget(),
 231                  RVLocs, *DAG.getContext());
 232
 233   // Analize return values.
 234   CCInfo.AnalyzeReturn(Outs, RetCC_Blackfin);
 235
 236   // If this is the first return lowered for this function, add the regs to the
 237   // liveout set for the function.
 238   if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
 239     for (unsigned i = 0; i != RVLocs.size(); ++i)
 240       DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
 241   }
 242
 243   SDValue Flag;
 244
 245   // Copy the result values into the output registers.
 246   for (unsigned i = 0; i != RVLocs.size(); ++i) {
 247     CCValAssign &VA = RVLocs[i];
 248     assert(VA.isRegLoc() && "Can only return in registers!");
 249     SDValue Opi = OutVals[i];
 250
 251     // Expand to i32 if necessary
 252     switch (VA.getLocInfo()) {
 253     default: llvm_unreachable("Unknown loc info!");
 254     case CCValAssign::Full: break;
 255     case CCValAssign::SExt:
 256       Opi = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Opi);
 257       break;
 258     case CCValAssign::ZExt:
 259       Opi = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Opi);
 260       break;
 261     case CCValAssign::AExt:
 262       Opi = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Opi);
 263       break;
 264     }
 265     Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Opi, SDValue());
 266     // Guarantee that all emitted copies are stuck together with flags.
 267     Flag = Chain.getValue(1);
 268   }
 269
 270   if (Flag.getNode()) {
 271     return DAG.getNode(BFISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
 272   } else {
 273     return DAG.getNode(BFISD::RET_FLAG, dl, MVT::Other, Chain);
 274   }
 275 }
 276
 277 SDValue
 278 BlackfinTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
 279                                   CallingConv::ID CallConv, bool isVarArg,
 280                                   bool &isTailCall,
 281                                   const SmallVectorImpl<ISD::OutputArg> &Outs,
 282                                   const SmallVectorImpl<SDValue> &OutVals,
 283                                   const SmallVectorImpl<ISD::InputArg> &Ins,
 284                                   DebugLoc dl, SelectionDAG &DAG,
 285                                   SmallVectorImpl<SDValue> &InVals) const {
 286   // Blackfin target does not yet support tail call optimization.
 287   isTailCall = false;
 288
 289   // Analyze operands of the call, assigning locations to each operand.
 290   SmallVector<CCValAssign, 16> ArgLocs;
 291   CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), ArgLocs,
 292                  *DAG.getContext());
 293   CCInfo.AllocateStack(12, 4);  // ABI requires 12 bytes stack space
 294   CCInfo.AnalyzeCallOperands(Outs, CC_Blackfin);
 295
 296   // Get the size of the outgoing arguments stack space requirement.
 297   unsigned ArgsSize = CCInfo.getNextStackOffset();
 298
 299   Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true));
 300   SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
 301   SmallVector<SDValue, 8> MemOpChains;
 302
 303   // Walk the register/memloc assignments, inserting copies/loads.
 304   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
 305     CCValAssign &VA = ArgLocs[i];
 306     SDValue Arg = OutVals[i];
 307
 308     // Promote the value if needed.
 309     switch (VA.getLocInfo()) {
 310     default: llvm_unreachable("Unknown loc info!");
 311     case CCValAssign::Full: break;
 312     case CCValAssign::SExt:
 313       Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
 314       break;
 315     case CCValAssign::ZExt:
 316       Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
 317       break;
 318     case CCValAssign::AExt:
 319       Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
 320       break;
 321     }
 322
 323     // Arguments that can be passed on register must be kept at
 324     // RegsToPass vector
 325     if (VA.isRegLoc()) {
 326       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
 327     } else {
 328       assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
 329       int Offset = VA.getLocMemOffset();
 330       assert(Offset%4 == 0 && "Unaligned LocMemOffset");
 331       assert(VA.getLocVT()==MVT::i32 && "Illegal CCValAssign type");
 332       SDValue SPN = DAG.getCopyFromReg(Chain, dl, BF::SP, MVT::i32);
 333       SDValue OffsetN = DAG.getIntPtrConstant(Offset);
 334       OffsetN = DAG.getNode(ISD::ADD, dl, MVT::i32, SPN, OffsetN);
 335       MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, OffsetN,
 336                                          MachinePointerInfo(),false, false, 0));
 337     }
 338   }
 339
 340   // Transform all store nodes into one single node because
 341   // all store nodes are independent of each other.
 342   if (!MemOpChains.empty())
 343     Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
 344                         &MemOpChains[0], MemOpChains.size());
 345
 346   // Build a sequence of copy-to-reg nodes chained together with token
 347   // chain and flag operands which copy the outgoing args into registers.
 348   // The InFlag in necessary since all emited instructions must be
 349   // stuck together.
 350   SDValue InFlag;
 351   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
 352     Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
 353                              RegsToPass[i].second, InFlag);
 354     InFlag = Chain.getValue(1);
 355   }
 356
 357   // If the callee is a GlobalAddress node (quite common, every direct call is)
 358   // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
 359   // Likewise ExternalSymbol -> TargetExternalSymbol.
 360   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
 361     Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
 362   else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
 363     Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
 364
 365   std::vector<EVT> NodeTys;
 366   NodeTys.push_back(MVT::Other);   // Returns a chain
 367   NodeTys.push_back(MVT::Glue);    // Returns a flag for retval copy to use.
 368   SDValue Ops[] = { Chain, Callee, InFlag };
 369   Chain = DAG.getNode(BFISD::CALL, dl, NodeTys, Ops,
 370                       InFlag.getNode() ? 3 : 2);
 371   InFlag = Chain.getValue(1);
 372
 373   Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
 374                              DAG.getIntPtrConstant(0, true), InFlag);
 375   InFlag = Chain.getValue(1);
 376
 377   // Assign locations to each value returned by this call.
 378   SmallVector<CCValAssign, 16> RVLocs;
 379   CCState RVInfo(CallConv, isVarArg, DAG.getTarget(), RVLocs,
 380                  *DAG.getContext());
 381
 382   RVInfo.AnalyzeCallResult(Ins, RetCC_Blackfin);
 383
 384   // Copy all of the result registers out of their specified physreg.
 385   for (unsigned i = 0; i != RVLocs.size(); ++i) {
 386     CCValAssign &RV = RVLocs[i];
 387     unsigned Reg = RV.getLocReg();
 388
 389     Chain = DAG.getCopyFromReg(Chain, dl, Reg,
 390                                RVLocs[i].getLocVT(), InFlag);
 391     SDValue Val = Chain.getValue(0);
 392     InFlag = Chain.getValue(2);
 393     Chain = Chain.getValue(1);
 394
 395     // Callee is responsible for extending any i16 return values.
 396     switch (RV.getLocInfo()) {
 397     case CCValAssign::SExt:
 398       Val = DAG.getNode(ISD::AssertSext, dl, RV.getLocVT(), Val,
 399                         DAG.getValueType(RV.getValVT()));
 400       break;
 401     case CCValAssign::ZExt:
 402       Val = DAG.getNode(ISD::AssertZext, dl, RV.getLocVT(), Val,
 403                         DAG.getValueType(RV.getValVT()));
 404       break;
 405     default:
 406       break;
 407     }
 408
 409     // Truncate to valtype
 410     if (RV.getLocInfo() != CCValAssign::Full)
 411       Val = DAG.getNode(ISD::TRUNCATE, dl, RV.getValVT(), Val);
 412     InVals.push_back(Val);
 413   }
 414
 415   return Chain;
 416 }
 417
 418 // Expansion of ADDE / SUBE. This is a bit involved since blackfin doesn't have
 419 // add-with-carry instructions.
 420 SDValue BlackfinTargetLowering::LowerADDE(SDValue Op, SelectionDAG &DAG) const {
 421   // Operands: lhs, rhs, carry-in (AC0 flag)
 422   // Results: sum, carry-out (AC0 flag)
 423   DebugLoc dl = Op.getDebugLoc();
 424
 425   unsigned Opcode = Op.getOpcode()==ISD::ADDE ? BF::ADD : BF::SUB;
 426
 427   // zext incoming carry flag in AC0 to 32 bits
 428   SDNode* CarryIn = DAG.getMachineNode(BF::MOVE_cc_ac0, dl, MVT::i32,
 429                                        /* flag= */ Op.getOperand(2));
 430   CarryIn = DAG.getMachineNode(BF::MOVECC_zext, dl, MVT::i32,
 431                                SDValue(CarryIn, 0));
 432
 433   // Add operands, produce sum and carry flag
 434   SDNode *Sum = DAG.getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
 435                                    Op.getOperand(0), Op.getOperand(1));
 436
 437   // Store intermediate carry from Sum
 438   SDNode* Carry1 = DAG.getMachineNode(BF::MOVE_cc_ac0, dl, MVT::i32,
 439                                       /* flag= */ SDValue(Sum, 1));
 440
 441   // Add incoming carry, again producing an output flag
 442   Sum = DAG.getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
 443                            SDValue(Sum, 0), SDValue(CarryIn, 0));
 444
 445   // Update AC0 with the intermediate carry, producing a flag.
 446   SDNode *CarryOut = DAG.getMachineNode(BF::OR_ac0_cc, dl, MVT::Glue,
 447                                         SDValue(Carry1, 0));
 448
 449   // Compose (i32, flag) pair
 450   SDValue ops[2] = { SDValue(Sum, 0), SDValue(CarryOut, 0) };
 451   return DAG.getMergeValues(ops, 2, dl);
 452 }
 453
 454 SDValue BlackfinTargetLowering::LowerOperation(SDValue Op,
 455                                                SelectionDAG &DAG) const {
 456   switch (Op.getOpcode()) {
 457   default:
 458     Op.getNode()->dump();
 459     llvm_unreachable("Should not custom lower this!");
 460   case ISD::GlobalAddress:      return LowerGlobalAddress(Op, DAG);
 461   case ISD::GlobalTLSAddress:
 462     llvm_unreachable("TLS not implemented for Blackfin.");
 463   case ISD::JumpTable:          return LowerJumpTable(Op, DAG);
 464     // Frame & Return address.  Currently unimplemented
 465   case ISD::FRAMEADDR:          return SDValue();
 466   case ISD::RETURNADDR:         return SDValue();
 467   case ISD::ADDE:
 468   case ISD::SUBE:               return LowerADDE(Op, DAG);
 469   }
 470 }
 471
 472 void
 473 BlackfinTargetLowering::ReplaceNodeResults(SDNode *N,
 474                                            SmallVectorImpl<SDValue> &Results,
 475                                            SelectionDAG &DAG) const {
 476   DebugLoc dl = N->getDebugLoc();
 477   switch (N->getOpcode()) {
 478   default:
 479     llvm_unreachable("Do not know how to custom type legalize this operation!");
 480     return;
 481   case ISD::READCYCLECOUNTER: {
 482     // The low part of the cycle counter is in CYCLES, the high part in
 483     // CYCLES2. Reading CYCLES will latch the value of CYCLES2, so we must read
 484     // CYCLES2 last.
 485     SDValue TheChain = N->getOperand(0);
 486     SDValue lo = DAG.getCopyFromReg(TheChain, dl, BF::CYCLES, MVT::i32);
 487     SDValue hi = DAG.getCopyFromReg(lo.getValue(1), dl, BF::CYCLES2, MVT::i32);
 488     // Use a buildpair to merge the two 32-bit values into a 64-bit one.
 489     Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, lo, hi));
 490     // Outgoing chain. If we were to use the chain from lo instead, it would be
 491     // possible to entirely eliminate the CYCLES2 read in (i32 (trunc
 492     // readcyclecounter)). Unfortunately this could possibly delay the CYCLES2
 493     // read beyond the next CYCLES read, leading to invalid results.
 494     Results.push_back(hi.getValue(1));
 495     return;
 496   }
 497   }
 498 }
 499
 500 /// getFunctionAlignment - Return the Log2 alignment of this function.
 501 unsigned BlackfinTargetLowering::getFunctionAlignment(const Function *F) const {
 502   return 2;
 503 }
 504
 505 //===----------------------------------------------------------------------===//
 506 //                         Blackfin Inline Assembly Support
 507 //===----------------------------------------------------------------------===//
 508
 509 /// getConstraintType - Given a constraint letter, return the type of
 510 /// constraint it is for this target.
 511 BlackfinTargetLowering::ConstraintType
 512 BlackfinTargetLowering::getConstraintType(const std::string &Constraint) const {
 513   if (Constraint.size() != 1)
 514     return TargetLowering::getConstraintType(Constraint);
 515
 516   switch (Constraint[0]) {
 517     // Standard constraints
 518   case 'r':
 519     return C_RegisterClass;
 520
 521     // Blackfin-specific constraints
 522   case 'a':
 523   case 'd':
 524   case 'z':
 525   case 'D':
 526   case 'W':
 527   case 'e':
 528   case 'b':
 529   case 'v':
 530   case 'f':
 531   case 'c':
 532   case 't':
 533   case 'u':
 534   case 'k':
 535   case 'x':
 536   case 'y':
 537   case 'w':
 538     return C_RegisterClass;
 539   case 'A':
 540   case 'B':
 541   case 'C':
 542   case 'Z':
 543   case 'Y':
 544     return C_Register;
 545   }
 546
 547   // Not implemented: q0-q7, qA. Use {R2} etc instead
 548
 549   return TargetLowering::getConstraintType(Constraint);
 550 }
 551
 552 /// Examine constraint type and operand type and determine a weight value.
 553 /// This object must already have been set up with the operand type
 554 /// and the current alternative constraint selected.
 555 TargetLowering::ConstraintWeight
 556 BlackfinTargetLowering::getSingleConstraintMatchWeight(
 557     AsmOperandInfo &info, const char *constraint) const {
 558   ConstraintWeight weight = CW_Invalid;
 559   Value *CallOperandVal = info.CallOperandVal;
 560     // If we don't have a value, we can't do a match,
 561     // but allow it at the lowest weight.
 562   if (CallOperandVal == NULL)
 563     return CW_Default;
 564   // Look at the constraint type.
 565   switch (*constraint) {
 566   default:
 567     weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
 568     break;
 569
 570     // Blackfin-specific constraints
 571   case 'a':
 572   case 'd':
 573   case 'z':
 574   case 'D':
 575   case 'W':
 576   case 'e':
 577   case 'b':
 578   case 'v':
 579   case 'f':
 580   case 'c':
 581   case 't':
 582   case 'u':
 583   case 'k':
 584   case 'x':
 585   case 'y':
 586   case 'w':
 587     return CW_Register;
 588   case 'A':
 589   case 'B':
 590   case 'C':
 591   case 'Z':
 592   case 'Y':
 593     return CW_SpecificReg;
 594   }
 595   return weight;
 596 }
 597
 598 /// getRegForInlineAsmConstraint - Return register no and class for a C_Register
 599 /// constraint.
 600 std::pair<unsigned, const TargetRegisterClass*> BlackfinTargetLowering::
 601 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {
 602   typedef std::pair<unsigned, const TargetRegisterClass*> Pair;
 603   using namespace BF;
 604
 605   if (Constraint.size() != 1)
 606     return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
 607
 608   switch (Constraint[0]) {
 609     // Standard constraints
 610   case 'r':
 611     return Pair(0U, VT == MVT::i16 ? D16RegisterClass : DPRegisterClass);
 612
 613     // Blackfin-specific constraints
 614   case 'a': return Pair(0U, PRegisterClass);
 615   case 'd': return Pair(0U, DRegisterClass);
 616   case 'e': return Pair(0U, AccuRegisterClass);
 617   case 'A': return Pair(A0, AccuRegisterClass);
 618   case 'B': return Pair(A1, AccuRegisterClass);
 619   case 'b': return Pair(0U, IRegisterClass);
 620   case 'v': return Pair(0U, BRegisterClass);
 621   case 'f': return Pair(0U, MRegisterClass);
 622   case 'C': return Pair(CC, JustCCRegisterClass);
 623   case 'x': return Pair(0U, GRRegisterClass);
 624   case 'w': return Pair(0U, ALLRegisterClass);
 625   case 'Z': return Pair(P3, PRegisterClass);
 626   case 'Y': return Pair(P1, PRegisterClass);
 627   }
 628
 629   // Not implemented: q0-q7, qA. Use {R2} etc instead.
 630   // Constraints z, D, W, c, t, u, k, and y use non-existing classes, defer to
 631   // getRegClassForInlineAsmConstraint()
 632
 633   return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
 634 }
 635
 636 std::vector<unsigned> BlackfinTargetLowering::
 637 getRegClassForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {
 638   using namespace BF;
 639
 640   if (Constraint.size() != 1)
 641     return std::vector<unsigned>();
 642
 643   switch (Constraint[0]) {
 644   case 'z': return make_vector<unsigned>(P0, P1, P2, 0);
 645   case 'D': return make_vector<unsigned>(R0, R2, R4, R6, 0);
 646   case 'W': return make_vector<unsigned>(R1, R3, R5, R7, 0);
 647   case 'c': return make_vector<unsigned>(I0, I1, I2, I3,
 648                                          B0, B1, B2, B3,
 649                                          L0, L1, L2, L3, 0);
 650   case 't': return make_vector<unsigned>(LT0, LT1, 0);
 651   case 'u': return make_vector<unsigned>(LB0, LB1, 0);
 652   case 'k': return make_vector<unsigned>(LC0, LC1, 0);
 653   case 'y': return make_vector<unsigned>(RETS, RETN, RETI, RETX, RETE,
 654                                          ASTAT, SEQSTAT, USP, 0);
 655   }
 656
 657   return std::vector<unsigned>();
 658 }
 659
 660 bool BlackfinTargetLowering::
 661 isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
 662   // The Blackfin target isn't yet aware of offsets.
 663   return false;
 664 }