lib/Target/SystemZ/SystemZInstrInfo.h

   1 //===- SystemZInstrInfo.h - SystemZ Instruction Information -------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_TARGET_SYSTEMZINSTRINFO_H
  15 #define LLVM_TARGET_SYSTEMZINSTRINFO_H
  16
  17 #include "SystemZ.h"
  18 #include "SystemZRegisterInfo.h"
  19 #include "llvm/ADT/IndexedMap.h"
  20 #include "llvm/Target/TargetInstrInfo.h"
  21
  22 namespace llvm {
  23
  24 class SystemZTargetMachine;
  25
  26 /// SystemZII - This namespace holds all of the target specific flags that
  27 /// instruction info tracks.
  28 ///
  29 namespace SystemZII {
  30   enum {
  31     //===------------------------------------------------------------------===//
  32     // SystemZ Specific MachineOperand flags.
  33
  34     MO_NO_FLAG = 0,
  35
  36     /// MO_GOTENT - On a symbol operand this indicates that the immediate is
  37     /// the offset to the location of the symbol name from the base of the GOT.
  38     ///
  39     ///    SYMBOL_LABEL @GOTENT
  40     MO_GOTENT = 1,
  41
  42     /// MO_PLT - On a symbol operand this indicates that the immediate is
  43     /// offset to the PLT entry of symbol name from the current code location.
  44     ///
  45     ///    SYMBOL_LABEL @PLT
  46     MO_PLT = 2
  47   };
  48 }
  49
  50 class SystemZInstrInfo : public TargetInstrInfoImpl {
  51   const SystemZRegisterInfo RI;
  52   SystemZTargetMachine &TM;
  53 public:
  54   explicit SystemZInstrInfo(SystemZTargetMachine &TM);
  55
  56   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  57   /// such, whenever a client has an instance of instruction info, it should
  58   /// always be able to get register info as well (through this method).
  59   ///
  60   virtual const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
  61
  62   virtual void copyPhysReg(MachineBasicBlock &MBB,
  63                            MachineBasicBlock::iterator I, DebugLoc DL,
  64                            unsigned DestReg, unsigned SrcReg,
  65                            bool KillSrc) const;
  66
  67   unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
  68   unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
  69
  70   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
  71                                    MachineBasicBlock::iterator MI,
  72                                    unsigned SrcReg, bool isKill,
  73                                    int FrameIndex,
  74                                    const TargetRegisterClass *RC,
  75                                    const TargetRegisterInfo *TRI) const;
  76   virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
  77                                     MachineBasicBlock::iterator MI,
  78                                     unsigned DestReg, int FrameIdx,
  79                                     const TargetRegisterClass *RC,
  80                                     const TargetRegisterInfo *TRI) const;
  81
  82   bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
  83   virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
  84   virtual bool AnalyzeBranch(MachineBasicBlock &MBB,
  85                              MachineBasicBlock *&TBB,
  86                              MachineBasicBlock *&FBB,
  87                              SmallVectorImpl<MachineOperand> &Cond,
  88                              bool AllowModify) const;
  89   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
  90                                 MachineBasicBlock *FBB,
  91                                 const SmallVectorImpl<MachineOperand> &Cond,
  92                                 DebugLoc DL) const;
  93   virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
  94
  95   SystemZCC::CondCodes getOppositeCondition(SystemZCC::CondCodes CC) const;
  96   SystemZCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
  97   const TargetInstrDesc& getBrCond(SystemZCC::CondCodes CC) const;
  98   const TargetInstrDesc& getLongDispOpc(unsigned Opc) const;
  99
 100   const TargetInstrDesc& getMemoryInstr(unsigned Opc, int64_t Offset = 0) const {
 101     if (Offset < 0 || Offset >= 4096)
 102       return getLongDispOpc(Opc);
 103     else
 104       return get(Opc);
 105   }
 106 };
 107
 108 }
 109
 110 #endif