lib/Target/X86/X86ISelLowering.h

   1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the interfaces that X86 uses to lower LLVM code into a
  11 // selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef X86ISELLOWERING_H
  16 #define X86ISELLOWERING_H
  17
  18 #include "X86Subtarget.h"
  19 #include "X86RegisterInfo.h"
  20 #include "X86MachineFunctionInfo.h"
  21 #include "llvm/Target/TargetLowering.h"
  22 #include "llvm/Target/TargetOptions.h"
  23 #include "llvm/CodeGen/FastISel.h"
  24 #include "llvm/CodeGen/SelectionDAG.h"
  25 #include "llvm/CodeGen/CallingConvLower.h"
  26
  27 namespace llvm {
  28   namespace X86ISD {
  29     // X86 Specific DAG Nodes
  30     enum NodeType {
  31       // Start the numbering where the builtin ops leave off.
  32       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  33
  34       /// BSF - Bit scan forward.
  35       /// BSR - Bit scan reverse.
  36       BSF,
  37       BSR,
  38
  39       /// SHLD, SHRD - Double shift instructions. These correspond to
  40       /// X86::SHLDxx and X86::SHRDxx instructions.
  41       SHLD,
  42       SHRD,
  43
  44       /// FAND - Bitwise logical AND of floating point values. This corresponds
  45       /// to X86::ANDPS or X86::ANDPD.
  46       FAND,
  47
  48       /// FOR - Bitwise logical OR of floating point values. This corresponds
  49       /// to X86::ORPS or X86::ORPD.
  50       FOR,
  51
  52       /// FXOR - Bitwise logical XOR of floating point values. This corresponds
  53       /// to X86::XORPS or X86::XORPD.
  54       FXOR,
  55
  56       /// FSRL - Bitwise logical right shift of floating point values. These
  57       /// corresponds to X86::PSRLDQ.
  58       FSRL,
  59
  60       /// CALL - These operations represent an abstract X86 call
  61       /// instruction, which includes a bunch of information.  In particular the
  62       /// operands of these node are:
  63       ///
  64       ///     #0 - The incoming token chain
  65       ///     #1 - The callee
  66       ///     #2 - The number of arg bytes the caller pushes on the stack.
  67       ///     #3 - The number of arg bytes the callee pops off the stack.
  68       ///     #4 - The value to pass in AL/AX/EAX (optional)
  69       ///     #5 - The value to pass in DL/DX/EDX (optional)
  70       ///
  71       /// The result values of these nodes are:
  72       ///
  73       ///     #0 - The outgoing token chain
  74       ///     #1 - The first register result value (optional)
  75       ///     #2 - The second register result value (optional)
  76       ///
  77       CALL,
  78
  79       /// RDTSC_DAG - This operation implements the lowering for
  80       /// readcyclecounter
  81       RDTSC_DAG,
  82
  83       /// X86 compare and logical compare instructions.
  84       CMP, COMI, UCOMI,
  85
  86       /// X86 bit-test instructions.
  87       BT,
  88
  89       /// X86 SetCC. Operand 0 is condition code, and operand 1 is the flag
  90       /// operand produced by a CMP instruction.
  91       SETCC,
  92
  93       // Same as SETCC except it's materialized with a sbb and the value is all
  94       // one's or all zero's.
  95       SETCC_CARRY,
  96
  97       /// X86 conditional moves. Operand 0 and operand 1 are the two values
  98       /// to select from. Operand 2 is the condition code, and operand 3 is the
  99       /// flag operand produced by a CMP or TEST instruction. It also writes a
 100       /// flag result.
 101       CMOV,
 102
 103       /// X86 conditional branches. Operand 0 is the chain operand, operand 1
 104       /// is the block to branch if condition is true, operand 2 is the
 105       /// condition code, and operand 3 is the flag operand produced by a CMP
 106       /// or TEST instruction.
 107       BRCOND,
 108
 109       /// Return with a flag operand. Operand 0 is the chain operand, operand
 110       /// 1 is the number of bytes of stack to pop.
 111       RET_FLAG,
 112
 113       /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
 114       REP_STOS,
 115
 116       /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
 117       REP_MOVS,
 118
 119       /// GlobalBaseReg - On Darwin, this node represents the result of the popl
 120       /// at function entry, used for PIC code.
 121       GlobalBaseReg,
 122
 123       /// Wrapper - A wrapper node for TargetConstantPool,
 124       /// TargetExternalSymbol, and TargetGlobalAddress.
 125       Wrapper,
 126
 127       /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
 128       /// relative displacements.
 129       WrapperRIP,
 130
 131       /// MOVQ2DQ - Copies a 64-bit value from an MMX vector to the low word
 132       /// of an XMM vector, with the high word zero filled.
 133       MOVQ2DQ,
 134
 135       /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector
 136       /// to an MMX vector.  If you think this is too close to the previous
 137       /// mnemonic, so do I; blame Intel.
 138       MOVDQ2Q,
 139
 140       /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
 141       /// i32, corresponds to X86::PEXTRB.
 142       PEXTRB,
 143
 144       /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
 145       /// i32, corresponds to X86::PEXTRW.
 146       PEXTRW,
 147
 148       /// INSERTPS - Insert any element of a 4 x float vector into any element
 149       /// of a destination 4 x floatvector.
 150       INSERTPS,
 151
 152       /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
 153       /// corresponds to X86::PINSRB.
 154       PINSRB,
 155
 156       /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
 157       /// corresponds to X86::PINSRW.
 158       PINSRW, MMX_PINSRW,
 159
 160       /// PSHUFB - Shuffle 16 8-bit values within a vector.
 161       PSHUFB,
 162
 163       /// FMAX, FMIN - Floating point max and min.
 164       ///
 165       FMAX, FMIN,
 166
 167       /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
 168       /// approximation.  Note that these typically require refinement
 169       /// in order to obtain suitable precision.
 170       FRSQRT, FRCP,
 171
 172       // TLSADDR - Thread Local Storage.
 173       TLSADDR,
 174
 175       // TLSCALL - Thread Local Storage.  When calling to an OS provided
 176       // thunk at the address from an earlier relocation.
 177       TLSCALL,
 178
 179       // EH_RETURN - Exception Handling helpers.
 180       EH_RETURN,
 181
 182       /// TC_RETURN - Tail call return.
 183       ///   operand #0 chain
 184       ///   operand #1 callee (register or absolute)
 185       ///   operand #2 stack adjustment
 186       ///   operand #3 optional in flag
 187       TC_RETURN,
 188
 189       // VZEXT_MOVL - Vector move low and zero extend.
 190       VZEXT_MOVL,
 191
 192       // VSHL, VSRL - Vector logical left / right shift.
 193       VSHL, VSRL,
 194
 195       // CMPPD, CMPPS - Vector double/float comparison.
 196       // CMPPD, CMPPS - Vector double/float comparison.
 197       CMPPD, CMPPS,
 198
 199       // PCMP* - Vector integer comparisons.
 200       PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ,
 201       PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ,
 202
 203       // ADD, SUB, SMUL, UMUL, etc. - Arithmetic operations with FLAGS results.
 204       ADD, SUB, SMUL, UMUL,
 205       INC, DEC, OR, XOR, AND,
 206
 207       // MUL_IMM - X86 specific multiply by immediate.
 208       MUL_IMM,
 209
 210       // PTEST - Vector bitwise comparisons
 211       PTEST,
 212
 213       // TESTP - Vector packed fp sign bitwise comparisons
 214       TESTP,
 215
 216       // Several flavors of instructions with vector shuffle behaviors.
 217       PALIGN,
 218       PSHUFD,
 219       PSHUFHW,
 220       PSHUFLW,
 221       PSHUFHW_LD,
 222       PSHUFLW_LD,
 223       SHUFPD,
 224       SHUFPS,
 225       MOVDDUP,
 226       MOVSHDUP,
 227       MOVSLDUP,
 228       MOVSHDUP_LD,
 229       MOVSLDUP_LD,
 230       MOVLHPS,
 231       MOVLHPD,
 232       MOVHLPS,
 233       MOVHLPD,
 234       MOVLPS,
 235       MOVLPD,
 236       MOVSD,
 237       MOVSS,
 238       UNPCKLPS,
 239       UNPCKLPD,
 240       UNPCKHPS,
 241       UNPCKHPD,
 242       PUNPCKLBW,
 243       PUNPCKLWD,
 244       PUNPCKLDQ,
 245       PUNPCKLQDQ,
 246       PUNPCKHBW,
 247       PUNPCKHWD,
 248       PUNPCKHDQ,
 249       PUNPCKHQDQ,
 250
 251       // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
 252       // according to %al. An operator is needed so that this can be expanded
 253       // with control flow.
 254       VASTART_SAVE_XMM_REGS,
 255
 256       // WIN_ALLOCA - Windows's _chkstk call to do stack probing.
 257       WIN_ALLOCA,
 258
 259       // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
 260       // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
 261       // Atomic 64-bit binary operations.
 262       ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
 263       ATOMSUB64_DAG,
 264       ATOMOR64_DAG,
 265       ATOMXOR64_DAG,
 266       ATOMAND64_DAG,
 267       ATOMNAND64_DAG,
 268       ATOMSWAP64_DAG,
 269
 270       // Memory barrier
 271       MEMBARRIER,
 272       MFENCE,
 273       SFENCE,
 274       LFENCE,
 275
 276       // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap.
 277       LCMPXCHG_DAG,
 278       LCMPXCHG8_DAG,
 279
 280       // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
 281       VZEXT_LOAD,
 282
 283       // FNSTCW16m - Store FP control world into i16 memory.
 284       FNSTCW16m,
 285
 286       /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
 287       /// integer destination in memory and a FP reg source.  This corresponds
 288       /// to the X86::FIST*m instructions and the rounding mode change stuff. It
 289       /// has two inputs (token chain and address) and two outputs (int value
 290       /// and token chain).
 291       FP_TO_INT16_IN_MEM,
 292       FP_TO_INT32_IN_MEM,
 293       FP_TO_INT64_IN_MEM,
 294
 295       /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
 296       /// integer source in memory and FP reg result.  This corresponds to the
 297       /// X86::FILD*m instructions. It has three inputs (token chain, address,
 298       /// and source type) and two outputs (FP value and token chain). FILD_FLAG
 299       /// also produces a flag).
 300       FILD,
 301       FILD_FLAG,
 302
 303       /// FLD - This instruction implements an extending load to FP stack slots.
 304       /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
 305       /// operand, ptr to load from, and a ValueType node indicating the type
 306       /// to load to.
 307       FLD,
 308
 309       /// FST - This instruction implements a truncating store to FP stack
 310       /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
 311       /// chain operand, value to store, address, and a ValueType to store it
 312       /// as.
 313       FST,
 314
 315       /// VAARG_64 - This instruction grabs the address of the next argument
 316       /// from a va_list. (reads and modifies the va_list in memory)
 317       VAARG_64
 318
 319       // WARNING: Do not add anything in the end unless you want the node to
 320       // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
 321       // thought as target memory ops!
 322     };
 323   }
 324
 325   /// Define some predicates that are used for node matching.
 326   namespace X86 {
 327     /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
 328     /// specifies a shuffle of elements that is suitable for input to PSHUFD.
 329     bool isPSHUFDMask(ShuffleVectorSDNode *N);
 330
 331     /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
 332     /// specifies a shuffle of elements that is suitable for input to PSHUFD.
 333     bool isPSHUFHWMask(ShuffleVectorSDNode *N);
 334
 335     /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
 336     /// specifies a shuffle of elements that is suitable for input to PSHUFD.
 337     bool isPSHUFLWMask(ShuffleVectorSDNode *N);
 338
 339     /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
 340     /// specifies a shuffle of elements that is suitable for input to SHUFP*.
 341     bool isSHUFPMask(ShuffleVectorSDNode *N);
 342
 343     /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
 344     /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
 345     bool isMOVHLPSMask(ShuffleVectorSDNode *N);
 346
 347     /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
 348     /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
 349     /// <2, 3, 2, 3>
 350     bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N);
 351
 352     /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
 353     /// specifies a shuffle of elements that is suitable for MOVLP{S|D}.
 354     bool isMOVLPMask(ShuffleVectorSDNode *N);
 355
 356     /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
 357     /// specifies a shuffle of elements that is suitable for MOVHP{S|D}.
 358     /// as well as MOVLHPS.
 359     bool isMOVLHPSMask(ShuffleVectorSDNode *N);
 360
 361     /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
 362     /// specifies a shuffle of elements that is suitable for input to UNPCKL.
 363     bool isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
 364
 365     /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
 366     /// specifies a shuffle of elements that is suitable for input to UNPCKH.
 367     bool isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
 368
 369     /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
 370     /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
 371     /// <0, 0, 1, 1>
 372     bool isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N);
 373
 374     /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
 375     /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
 376     /// <2, 2, 3, 3>
 377     bool isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N);
 378
 379     /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
 380     /// specifies a shuffle of elements that is suitable for input to MOVSS,
 381     /// MOVSD, and MOVD, i.e. setting the lowest element.
 382     bool isMOVLMask(ShuffleVectorSDNode *N);
 383
 384     /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
 385     /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
 386     bool isMOVSHDUPMask(ShuffleVectorSDNode *N);
 387
 388     /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
 389     /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
 390     bool isMOVSLDUPMask(ShuffleVectorSDNode *N);
 391
 392     /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
 393     /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
 394     bool isMOVDDUPMask(ShuffleVectorSDNode *N);
 395
 396     /// isPALIGNRMask - Return true if the specified VECTOR_SHUFFLE operand
 397     /// specifies a shuffle of elements that is suitable for input to PALIGNR.
 398     bool isPALIGNRMask(ShuffleVectorSDNode *N);
 399
 400     /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
 401     /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
 402     /// instructions.
 403     unsigned getShuffleSHUFImmediate(SDNode *N);
 404
 405     /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
 406     /// the specified VECTOR_SHUFFLE mask with PSHUFHW instruction.
 407     unsigned getShufflePSHUFHWImmediate(SDNode *N);
 408
 409     /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
 410     /// the specified VECTOR_SHUFFLE mask with PSHUFLW instruction.
 411     unsigned getShufflePSHUFLWImmediate(SDNode *N);
 412
 413     /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
 414     /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
 415     unsigned getShufflePALIGNRImmediate(SDNode *N);
 416
 417     /// isZeroNode - Returns true if Elt is a constant zero or a floating point
 418     /// constant +0.0.
 419     bool isZeroNode(SDValue Elt);
 420
 421     /// isOffsetSuitableForCodeModel - Returns true of the given offset can be
 422     /// fit into displacement field of the instruction.
 423     bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
 424                                       bool hasSymbolicDisplacement = true);
 425   }
 426
 427   //===--------------------------------------------------------------------===//
 428   //  X86TargetLowering - X86 Implementation of the TargetLowering interface
 429   class X86TargetLowering : public TargetLowering {
 430   public:
 431     explicit X86TargetLowering(X86TargetMachine &TM);
 432
 433     /// getPICBaseSymbol - Return the X86-32 PIC base.
 434     MCSymbol *getPICBaseSymbol(const MachineFunction *MF, MCContext &Ctx) const;
 435
 436     virtual unsigned getJumpTableEncoding() const;
 437
 438     virtual const MCExpr *
 439     LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
 440                               const MachineBasicBlock *MBB, unsigned uid,
 441                               MCContext &Ctx) const;
 442
 443     /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
 444     /// jumptable.
 445     virtual SDValue getPICJumpTableRelocBase(SDValue Table,
 446                                              SelectionDAG &DAG) const;
 447     virtual const MCExpr *
 448     getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
 449                                  unsigned JTI, MCContext &Ctx) const;
 450
 451     /// getStackPtrReg - Return the stack pointer register we are using: either
 452     /// ESP or RSP.
 453     unsigned getStackPtrReg() const { return X86StackPtr; }
 454
 455     /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
 456     /// function arguments in the caller parameter area. For X86, aggregates
 457     /// that contains are placed at 16-byte boundaries while the rest are at
 458     /// 4-byte boundaries.
 459     virtual unsigned getByValTypeAlignment(const Type *Ty) const;
 460
 461     /// getOptimalMemOpType - Returns the target specific optimal type for load
 462     /// and store operations as a result of memset, memcpy, and memmove
 463     /// lowering. If DstAlign is zero that means it's safe to destination
 464     /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
 465     /// means there isn't a need to check it against alignment requirement,
 466     /// probably because the source does not need to be loaded. If
 467     /// 'NonScalarIntSafe' is true, that means it's safe to return a
 468     /// non-scalar-integer type, e.g. empty string source, constant, or loaded
 469     /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
 470     /// constant so it does not need to be loaded.
 471     /// It returns EVT::Other if the type should be determined using generic
 472     /// target-independent logic.
 473     virtual EVT
 474     getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
 475                         bool NonScalarIntSafe, bool MemcpyStrSrc,
 476                         MachineFunction &MF) const;
 477
 478     /// allowsUnalignedMemoryAccesses - Returns true if the target allows
 479     /// unaligned memory accesses. of the specified type.
 480     virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
 481       return true;
 482     }
 483
 484     /// LowerOperation - Provide custom lowering hooks for some operations.
 485     ///
 486     virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
 487
 488     /// ReplaceNodeResults - Replace the results of node with an illegal result
 489     /// type with new values built out of custom code.
 490     ///
 491     virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
 492                                     SelectionDAG &DAG) const;
 493
 494
 495     virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 496
 497     /// isTypeDesirableForOp - Return true if the target has native support for
 498     /// the specified value type and it is 'desirable' to use the type for the
 499     /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
 500     /// instruction encodings are longer and some i16 instructions are slow.
 501     virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
 502
 503     /// isTypeDesirable - Return true if the target has native support for the
 504     /// specified value type and it is 'desirable' to use the type. e.g. On x86
 505     /// i16 is legal, but undesirable since i16 instruction encodings are longer
 506     /// and some i16 instructions are slow.
 507     virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
 508
 509     virtual MachineBasicBlock *
 510       EmitInstrWithCustomInserter(MachineInstr *MI,
 511                                   MachineBasicBlock *MBB) const;
 512
 513
 514     /// getTargetNodeName - This method returns the name of a target specific
 515     /// DAG node.
 516     virtual const char *getTargetNodeName(unsigned Opcode) const;
 517
 518     /// getSetCCResultType - Return the ISD::SETCC ValueType
 519     virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
 520
 521     /// computeMaskedBitsForTargetNode - Determine which of the bits specified
 522     /// in Mask are known to be either zero or one and return them in the
 523     /// KnownZero/KnownOne bitsets.
 524     virtual void computeMaskedBitsForTargetNode(const SDValue Op,
 525                                                 const APInt &Mask,
 526                                                 APInt &KnownZero,
 527                                                 APInt &KnownOne,
 528                                                 const SelectionDAG &DAG,
 529                                                 unsigned Depth = 0) const;
 530
 531     // ComputeNumSignBitsForTargetNode - Determine the number of bits in the
 532     // operation that are sign bits.
 533     virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
 534                                                      unsigned Depth) const;
 535
 536     virtual bool
 537     isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
 538
 539     SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
 540
 541     virtual bool ExpandInlineAsm(CallInst *CI) const;
 542
 543     ConstraintType getConstraintType(const std::string &Constraint) const;
 544
 545     /// Examine constraint string and operand type and determine a weight value.
 546     /// The operand object must already have been set up with the operand type.
 547     virtual ConstraintWeight getSingleConstraintMatchWeight(
 548       AsmOperandInfo &info, const char *constraint) const;
 549
 550     std::vector<unsigned>
 551       getRegClassForInlineAsmConstraint(const std::string &Constraint,
 552                                         EVT VT) const;
 553
 554     virtual const char *LowerXConstraint(EVT ConstraintVT) const;
 555
 556     /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
 557     /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
 558     /// true it means one of the asm constraint of the inline asm instruction
 559     /// being processed is 'm'.
 560     virtual void LowerAsmOperandForConstraint(SDValue Op,
 561                                               char ConstraintLetter,
 562                                               std::vector<SDValue> &Ops,
 563                                               SelectionDAG &DAG) const;
 564
 565     /// getRegForInlineAsmConstraint - Given a physical register constraint
 566     /// (e.g. {edx}), return the register number and the register class for the
 567     /// register.  This should only be used for C_Register constraints.  On
 568     /// error, this returns a register number of 0.
 569     std::pair<unsigned, const TargetRegisterClass*>
 570       getRegForInlineAsmConstraint(const std::string &Constraint,
 571                                    EVT VT) const;
 572
 573     /// isLegalAddressingMode - Return true if the addressing mode represented
 574     /// by AM is legal for this target, for a load/store of the specified type.
 575     virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
 576
 577     /// isTruncateFree - Return true if it's free to truncate a value of
 578     /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
 579     /// register EAX to i16 by referencing its sub-register AX.
 580     virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const;
 581     virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
 582
 583     /// isZExtFree - Return true if any actual instruction that defines a
 584     /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
 585     /// register. This does not necessarily include registers defined in
 586     /// unknown ways, such as incoming arguments, or copies from unknown
 587     /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
 588     /// does not necessarily apply to truncate instructions. e.g. on x86-64,
 589     /// all instructions that define 32-bit values implicit zero-extend the
 590     /// result out to 64 bits.
 591     virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const;
 592     virtual bool isZExtFree(EVT VT1, EVT VT2) const;
 593
 594     /// isNarrowingProfitable - Return true if it's profitable to narrow
 595     /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
 596     /// from i32 to i8 but not from i32 to i16.
 597     virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
 598
 599     /// isFPImmLegal - Returns true if the target can instruction select the
 600     /// specified FP immediate natively. If false, the legalizer will
 601     /// materialize the FP immediate as a load from a constant pool.
 602     virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
 603
 604     /// isShuffleMaskLegal - Targets can use this to indicate that they only
 605     /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
 606     /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
 607     /// values are assumed to be legal.
 608     virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
 609                                     EVT VT) const;
 610
 611     /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
 612     /// used by Targets can use this to indicate if there is a suitable
 613     /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
 614     /// pool entry.
 615     virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
 616                                         EVT VT) const;
 617
 618     /// ShouldShrinkFPConstant - If true, then instruction selection should
 619     /// seek to shrink the FP constant of the specified type to a smaller type
 620     /// in order to save space and / or reduce runtime.
 621     virtual bool ShouldShrinkFPConstant(EVT VT) const {
 622       // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
 623       // expensive than a straight movsd. On the other hand, it's important to
 624       // shrink long double fp constant since fldt is very slow.
 625       return !X86ScalarSSEf64 || VT == MVT::f80;
 626     }
 627
 628     const X86Subtarget* getSubtarget() const {
 629       return Subtarget;
 630     }
 631
 632     /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
 633     /// computed in an SSE register, not on the X87 floating point stack.
 634     bool isScalarFPTypeInSSEReg(EVT VT) const {
 635       return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
 636       (VT == MVT::f32 && X86ScalarSSEf32);   // f32 is when SSE1
 637     }
 638
 639     /// createFastISel - This method returns a target specific FastISel object,
 640     /// or null if the target does not support "fast" ISel.
 641     virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
 642
 643     /// getFunctionAlignment - Return the Log2 alignment of this function.
 644     virtual unsigned getFunctionAlignment(const Function *F) const;
 645
 646     unsigned getRegPressureLimit(const TargetRegisterClass *RC,
 647                                  MachineFunction &MF) const;
 648
 649     /// getStackCookieLocation - Return true if the target stores stack
 650     /// protector cookies at a fixed offset in some non-standard address
 651     /// space, and populates the address space and offset as
 652     /// appropriate.
 653     virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const;
 654
 655   protected:
 656     std::pair<const TargetRegisterClass*, uint8_t>
 657     findRepresentativeClass(EVT VT) const;
 658
 659   private:
 660     /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
 661     /// make the right decision when generating code for different targets.
 662     const X86Subtarget *Subtarget;
 663     const X86RegisterInfo *RegInfo;
 664     const TargetData *TD;
 665
 666     /// X86StackPtr - X86 physical register used as stack ptr.
 667     unsigned X86StackPtr;
 668
 669     /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
 670     /// floating point ops.
 671     /// When SSE is available, use it for f32 operations.
 672     /// When SSE2 is available, use it for f64 operations.
 673     bool X86ScalarSSEf32;
 674     bool X86ScalarSSEf64;
 675
 676     /// LegalFPImmediates - A list of legal fp immediates.
 677     std::vector<APFloat> LegalFPImmediates;
 678
 679     /// addLegalFPImmediate - Indicate that this x86 target can instruction
 680     /// select the specified FP immediate natively.
 681     void addLegalFPImmediate(const APFloat& Imm) {
 682       LegalFPImmediates.push_back(Imm);
 683     }
 684
 685     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
 686                             CallingConv::ID CallConv, bool isVarArg,
 687                             const SmallVectorImpl<ISD::InputArg> &Ins,
 688                             DebugLoc dl, SelectionDAG &DAG,
 689                             SmallVectorImpl<SDValue> &InVals) const;
 690     SDValue LowerMemArgument(SDValue Chain,
 691                              CallingConv::ID CallConv,
 692                              const SmallVectorImpl<ISD::InputArg> &ArgInfo,
 693                              DebugLoc dl, SelectionDAG &DAG,
 694                              const CCValAssign &VA,  MachineFrameInfo *MFI,
 695                               unsigned i) const;
 696     SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
 697                              DebugLoc dl, SelectionDAG &DAG,
 698                              const CCValAssign &VA,
 699                              ISD::ArgFlagsTy Flags) const;
 700
 701     // Call lowering helpers.
 702
 703     /// IsEligibleForTailCallOptimization - Check whether the call is eligible
 704     /// for tail call optimization. Targets which want to do tail call
 705     /// optimization should implement this function.
 706     bool IsEligibleForTailCallOptimization(SDValue Callee,
 707                                            CallingConv::ID CalleeCC,
 708                                            bool isVarArg,
 709                                            bool isCalleeStructRet,
 710                                            bool isCallerStructRet,
 711                                     const SmallVectorImpl<ISD::OutputArg> &Outs,
 712                                     const SmallVectorImpl<SDValue> &OutVals,
 713                                     const SmallVectorImpl<ISD::InputArg> &Ins,
 714                                            SelectionDAG& DAG) const;
 715     bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
 716     SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
 717                                 SDValue Chain, bool IsTailCall, bool Is64Bit,
 718                                 int FPDiff, DebugLoc dl) const;
 719
 720     unsigned GetAlignedArgumentStackSize(unsigned StackSize,
 721                                          SelectionDAG &DAG) const;
 722
 723     std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
 724                                                bool isSigned) const;
 725
 726     SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
 727                                    SelectionDAG &DAG) const;
 728     SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
 729     SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
 730     SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
 731     SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
 732     SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
 733     SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
 734     SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
 735     SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
 736     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
 737     SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
 738     SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
 739                                int64_t Offset, SelectionDAG &DAG) const;
 740     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
 741     SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
 742     SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
 743     SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
 744     SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
 745                       SelectionDAG &DAG) const;
 746     SDValue LowerBIT_CONVERT(SDValue op, SelectionDAG &DAG) const;
 747     SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
 748     SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
 749     SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
 750     SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
 751     SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
 752     SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
 753     SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
 754     SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
 755     SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
 756     SDValue LowerToBT(SDValue And, ISD::CondCode CC,
 757                       DebugLoc dl, SelectionDAG &DAG) const;
 758     SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
 759     SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
 760     SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
 761     SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
 762     SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
 763     SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
 764     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
 765     SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
 766     SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
 767     SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
 768     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
 769     SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
 770     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
 771     SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
 772     SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
 773     SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
 774     SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
 775     SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
 776     SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
 777     SDValue LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const;
 778     SDValue LowerSHL(SDValue Op, SelectionDAG &DAG) const;
 779     SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
 780
 781     SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
 782     SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
 783     SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
 784     SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const;
 785
 786     // Utility functions to help LowerVECTOR_SHUFFLE
 787     SDValue LowerVECTOR_SHUFFLEv8i16(SDValue Op, SelectionDAG &DAG) const;
 788
 789     virtual SDValue
 790       LowerFormalArguments(SDValue Chain,
 791                            CallingConv::ID CallConv, bool isVarArg,
 792                            const SmallVectorImpl<ISD::InputArg> &Ins,
 793                            DebugLoc dl, SelectionDAG &DAG,
 794                            SmallVectorImpl<SDValue> &InVals) const;
 795     virtual SDValue
 796       LowerCall(SDValue Chain, SDValue Callee,
 797                 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
 798                 const SmallVectorImpl<ISD::OutputArg> &Outs,
 799                 const SmallVectorImpl<SDValue> &OutVals,
 800                 const SmallVectorImpl<ISD::InputArg> &Ins,
 801                 DebugLoc dl, SelectionDAG &DAG,
 802                 SmallVectorImpl<SDValue> &InVals) const;
 803
 804     virtual SDValue
 805       LowerReturn(SDValue Chain,
 806                   CallingConv::ID CallConv, bool isVarArg,
 807                   const SmallVectorImpl<ISD::OutputArg> &Outs,
 808                   const SmallVectorImpl<SDValue> &OutVals,
 809                   DebugLoc dl, SelectionDAG &DAG) const;
 810
 811     virtual bool
 812       CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
 813                      const SmallVectorImpl<ISD::OutputArg> &Outs,
 814                      LLVMContext &Context) const;
 815
 816     void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results,
 817                                  SelectionDAG &DAG, unsigned NewOp) const;
 818
 819     /// Utility function to emit string processing sse4.2 instructions
 820     /// that return in xmm0.
 821     /// This takes the instruction to expand, the associated machine basic
 822     /// block, the number of args, and whether or not the second arg is
 823     /// in memory or not.
 824     MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB,
 825                                 unsigned argNum, bool inMem) const;
 826
 827     /// Utility function to emit atomic bitwise operations (and, or, xor).
 828     /// It takes the bitwise instruction to expand, the associated machine basic
 829     /// block, and the associated X86 opcodes for reg/reg and reg/imm.
 830     MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter(
 831                                                     MachineInstr *BInstr,
 832                                                     MachineBasicBlock *BB,
 833                                                     unsigned regOpc,
 834                                                     unsigned immOpc,
 835                                                     unsigned loadOpc,
 836                                                     unsigned cxchgOpc,
 837                                                     unsigned notOpc,
 838                                                     unsigned EAXreg,
 839                                                     TargetRegisterClass *RC,
 840                                                     bool invSrc = false) const;
 841
 842     MachineBasicBlock *EmitAtomicBit6432WithCustomInserter(
 843                                                     MachineInstr *BInstr,
 844                                                     MachineBasicBlock *BB,
 845                                                     unsigned regOpcL,
 846                                                     unsigned regOpcH,
 847                                                     unsigned immOpcL,
 848                                                     unsigned immOpcH,
 849                                                     bool invSrc = false) const;
 850
 851     /// Utility function to emit atomic min and max.  It takes the min/max
 852     /// instruction to expand, the associated basic block, and the associated
 853     /// cmov opcode for moving the min or max value.
 854     MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
 855                                                           MachineBasicBlock *BB,
 856                                                         unsigned cmovOpc) const;
 857
 858     // Utility function to emit the low-level va_arg code for X86-64.
 859     MachineBasicBlock *EmitVAARG64WithCustomInserter(
 860                        MachineInstr *MI,
 861                        MachineBasicBlock *MBB) const;
 862
 863     /// Utility function to emit the xmm reg save portion of va_start.
 864     MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
 865                                                    MachineInstr *BInstr,
 866                                                    MachineBasicBlock *BB) const;
 867
 868     MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
 869                                          MachineBasicBlock *BB) const;
 870
 871     MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
 872                                               MachineBasicBlock *BB) const;
 873
 874     MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
 875                                           MachineBasicBlock *BB) const;
 876
 877     /// Emit nodes that will be selected as "test Op0,Op0", or something
 878     /// equivalent, for use with the given x86 condition code.
 879     SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
 880
 881     /// Emit nodes that will be selected as "cmp Op0,Op1", or something
 882     /// equivalent, for use with the given x86 condition code.
 883     SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
 884                     SelectionDAG &DAG) const;
 885   };
 886
 887   namespace X86 {
 888     FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
 889   }
 890 }
 891
 892 #endif    // X86ISELLOWERING_H