src/gallium/drivers/svga/svga_state_rss.c

   1 /**********************************************************
   2  * Copyright 2008-2009 VMware, Inc.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person
   5  * obtaining a copy of this software and associated documentation
   6  * files (the "Software"), to deal in the Software without
   7  * restriction, including without limitation the rights to use, copy,
   8  * modify, merge, publish, distribute, sublicense, and/or sell copies
   9  * of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be
  13  * included in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  19  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  20  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  **********************************************************/
  25
  26 #include "util/u_inlines.h"
  27 #include "pipe/p_defines.h"
  28 #include "util/u_math.h"
  29
  30 #include "svga_context.h"
  31 #include "svga_state.h"
  32 #include "svga_cmd.h"
  33
  34
  35 struct rs_queue {
  36    unsigned rs_count;
  37    SVGA3dRenderState rs[SVGA3D_RS_MAX];
  38 };
  39
  40
  41 #define EMIT_RS(svga, value, token, fail)                       \
  42 do {                                                            \
  43    if (svga->state.hw_draw.rs[SVGA3D_RS_##token] != value) {    \
  44       svga_queue_rs( &queue, SVGA3D_RS_##token, value );        \
  45       svga->state.hw_draw.rs[SVGA3D_RS_##token] = value;        \
  46    }                                                            \
  47 } while (0)
  48
  49 #define EMIT_RS_FLOAT(svga, fvalue, token, fail)                \
  50 do {                                                            \
  51    unsigned value = fui(fvalue);                                \
  52    if (svga->state.hw_draw.rs[SVGA3D_RS_##token] != value) {    \
  53       svga_queue_rs( &queue, SVGA3D_RS_##token, value );        \
  54       svga->state.hw_draw.rs[SVGA3D_RS_##token] = value;        \
  55    }                                                            \
  56 } while (0)
  57
  58
  59 static INLINE void
  60 svga_queue_rs( struct rs_queue *q,
  61                unsigned rss,
  62                unsigned value )
  63 {
  64    q->rs[q->rs_count].state = rss;
  65    q->rs[q->rs_count].uintValue = value;
  66    q->rs_count++;
  67 }
  68
  69
  70 /* Compare old and new render states and emit differences between them
  71  * to hardware.  Simplest implementation would be to emit the whole of
  72  * the "to" state.
  73  */
  74 static int emit_rss( struct svga_context *svga,
  75                      unsigned dirty )
  76 {
  77    struct rs_queue queue;
  78
  79    queue.rs_count = 0;
  80
  81    if (dirty & SVGA_NEW_BLEND) {
  82       const struct svga_blend_state *curr = svga->curr.blend;
  83
  84       EMIT_RS( svga, curr->rt[0].writemask, COLORWRITEENABLE, fail );
  85       EMIT_RS( svga, curr->rt[0].blend_enable, BLENDENABLE, fail );
  86
  87       if (curr->rt[0].blend_enable) {
  88          EMIT_RS( svga, curr->rt[0].srcblend, SRCBLEND, fail );
  89          EMIT_RS( svga, curr->rt[0].dstblend, DSTBLEND, fail );
  90          EMIT_RS( svga, curr->rt[0].blendeq, BLENDEQUATION, fail );
  91
  92          EMIT_RS( svga, curr->rt[0].separate_alpha_blend_enable,
  93                   SEPARATEALPHABLENDENABLE, fail );
  94
  95          if (curr->rt[0].separate_alpha_blend_enable) {
  96             EMIT_RS( svga, curr->rt[0].srcblend_alpha, SRCBLENDALPHA, fail );
  97             EMIT_RS( svga, curr->rt[0].dstblend_alpha, DSTBLENDALPHA, fail );
  98             EMIT_RS( svga, curr->rt[0].blendeq_alpha, BLENDEQUATIONALPHA, fail );
  99          }
 100       }
 101    }
 102
 103    if (dirty & SVGA_NEW_BLEND_COLOR) {
 104       uint32 color;
 105       uint32 r = float_to_ubyte(svga->curr.blend_color.color[0]);
 106       uint32 g = float_to_ubyte(svga->curr.blend_color.color[1]);
 107       uint32 b = float_to_ubyte(svga->curr.blend_color.color[2]);
 108       uint32 a = float_to_ubyte(svga->curr.blend_color.color[3]);
 109
 110       color = (a << 24) | (r << 16) | (g << 8) | b;
 111
 112       EMIT_RS( svga, color, BLENDCOLOR, fail );
 113    }
 114
 115    if (dirty & (SVGA_NEW_DEPTH_STENCIL | SVGA_NEW_RAST)) {
 116       const struct svga_depth_stencil_state *curr = svga->curr.depth;
 117       const struct svga_rasterizer_state *rast = svga->curr.rast;
 118
 119       if (!curr->stencil[0].enabled)
 120       {
 121          /* Stencil disabled
 122           */
 123          EMIT_RS( svga, FALSE, STENCILENABLE, fail );
 124          EMIT_RS( svga, FALSE, STENCILENABLE2SIDED, fail );
 125       }
 126       else if (curr->stencil[0].enabled && !curr->stencil[1].enabled)
 127       {
 128          /* Regular stencil
 129           */
 130          EMIT_RS( svga, TRUE, STENCILENABLE, fail );
 131          EMIT_RS( svga, FALSE, STENCILENABLE2SIDED, fail );
 132
 133          EMIT_RS( svga, curr->stencil[0].func,  STENCILFUNC, fail );
 134          EMIT_RS( svga, curr->stencil[0].fail,  STENCILFAIL, fail );
 135          EMIT_RS( svga, curr->stencil[0].zfail, STENCILZFAIL, fail );
 136          EMIT_RS( svga, curr->stencil[0].pass,  STENCILPASS, fail );
 137
 138          EMIT_RS( svga, curr->stencil_mask, STENCILMASK, fail );
 139          EMIT_RS( svga, curr->stencil_writemask, STENCILWRITEMASK, fail );
 140       }
 141       else
 142       {
 143          int cw, ccw;
 144
 145          /* Hardware frontwinding is always CW, so if ours is also CW,
 146           * then our definition of front face agrees with hardware.
 147           * Otherwise need to flip.
 148           */
 149          if (rast->templ.front_ccw) {
 150             ccw = 0;
 151             cw = 1;
 152          }
 153          else {
 154             ccw = 1;
 155             cw = 0;
 156          }
 157
 158          /* Twoside stencil
 159           */
 160          EMIT_RS( svga, TRUE, STENCILENABLE, fail );
 161          EMIT_RS( svga, TRUE, STENCILENABLE2SIDED, fail );
 162
 163          EMIT_RS( svga, curr->stencil[cw].func,  STENCILFUNC, fail );
 164          EMIT_RS( svga, curr->stencil[cw].fail,  STENCILFAIL, fail );
 165          EMIT_RS( svga, curr->stencil[cw].zfail, STENCILZFAIL, fail );
 166          EMIT_RS( svga, curr->stencil[cw].pass,  STENCILPASS, fail );
 167
 168          EMIT_RS( svga, curr->stencil[ccw].func,  CCWSTENCILFUNC, fail );
 169          EMIT_RS( svga, curr->stencil[ccw].fail,  CCWSTENCILFAIL, fail );
 170          EMIT_RS( svga, curr->stencil[ccw].zfail, CCWSTENCILZFAIL, fail );
 171          EMIT_RS( svga, curr->stencil[ccw].pass,  CCWSTENCILPASS, fail );
 172
 173          EMIT_RS( svga, curr->stencil_mask, STENCILMASK, fail );
 174          EMIT_RS( svga, curr->stencil_writemask, STENCILWRITEMASK, fail );
 175       }
 176
 177       EMIT_RS( svga, curr->zenable, ZENABLE, fail );
 178       if (curr->zenable) {
 179          EMIT_RS( svga, curr->zfunc, ZFUNC, fail );
 180          EMIT_RS( svga, curr->zwriteenable, ZWRITEENABLE, fail );
 181       }
 182
 183       EMIT_RS( svga, curr->alphatestenable, ALPHATESTENABLE, fail );
 184       if (curr->alphatestenable) {
 185          EMIT_RS( svga, curr->alphafunc, ALPHAFUNC, fail );
 186          EMIT_RS_FLOAT( svga, curr->alpharef, ALPHAREF, fail );
 187       }
 188    }
 189
 190    if (dirty & SVGA_NEW_STENCIL_REF) {
 191       EMIT_RS( svga, svga->curr.stencil_ref.ref_value[0], STENCILREF, fail );
 192    }
 193
 194    if (dirty & (SVGA_NEW_RAST | SVGA_NEW_NEED_PIPELINE))
 195    {
 196       const struct svga_rasterizer_state *curr = svga->curr.rast;
 197       unsigned cullmode = curr->cullmode;
 198
 199       /* Shademode: still need to rearrange index list to move
 200        * flat-shading PV first vertex.
 201        */
 202       EMIT_RS( svga, curr->shademode, SHADEMODE, fail );
 203
 204       /* Don't do culling while the software pipeline is active.  It
 205        * does it for us, and additionally introduces potentially
 206        * back-facing triangles.
 207        */
 208       if (svga->state.sw.need_pipeline)
 209          cullmode = SVGA3D_FACE_NONE;
 210
 211       EMIT_RS( svga, cullmode, CULLMODE, fail );
 212       EMIT_RS( svga, curr->scissortestenable, SCISSORTESTENABLE, fail );
 213       EMIT_RS( svga, curr->multisampleantialias, MULTISAMPLEANTIALIAS, fail );
 214       EMIT_RS( svga, curr->lastpixel, LASTPIXEL, fail );
 215       EMIT_RS( svga, curr->linepattern, LINEPATTERN, fail );
 216       EMIT_RS_FLOAT( svga, curr->pointsize, POINTSIZE, fail );
 217       /* XXX still need to set this? */
 218       EMIT_RS_FLOAT( svga, 0.0, POINTSIZEMIN, fail );
 219       EMIT_RS_FLOAT( svga, SVGA_MAX_POINTSIZE, POINTSIZEMAX, fail );
 220    }
 221
 222    if (dirty & (SVGA_NEW_RAST | SVGA_NEW_FRAME_BUFFER | SVGA_NEW_NEED_PIPELINE))
 223    {
 224       const struct svga_rasterizer_state *curr = svga->curr.rast;
 225       float slope = 0.0;
 226       float bias  = 0.0;
 227
 228       /* Need to modify depth bias according to bound depthbuffer
 229        * format.  Don't do hardware depthbias while the software
 230        * pipeline is active.
 231        */
 232       if (!svga->state.sw.need_pipeline &&
 233           svga->curr.framebuffer.zsbuf)
 234       {
 235          slope = curr->slopescaledepthbias;
 236          bias  = svga->curr.depthscale * curr->depthbias;
 237       }
 238
 239       EMIT_RS_FLOAT( svga, slope, SLOPESCALEDEPTHBIAS, fail );
 240       EMIT_RS_FLOAT( svga, bias, DEPTHBIAS, fail );
 241    }
 242
 243
 244    if (queue.rs_count) {
 245       SVGA3dRenderState *rs;
 246
 247       if (SVGA3D_BeginSetRenderState( svga->swc,
 248                                       &rs,
 249                                       queue.rs_count ) != PIPE_OK)
 250          goto fail;
 251
 252       memcpy( rs,
 253               queue.rs,
 254               queue.rs_count * sizeof queue.rs[0]);
 255
 256       SVGA_FIFOCommitAll( svga->swc );
 257    }
 258
 259    return 0;
 260
 261 fail:
 262    /* XXX: need to poison cached hardware state on failure to ensure
 263     * dirty state gets re-emitted.  Fix this by re-instating partial
 264     * FIFOCommit command and only updating cached hw state once the
 265     * initial allocation has succeeded.
 266     */
 267    memset(svga->state.hw_draw.rs, 0xcd, sizeof(svga->state.hw_draw.rs));
 268
 269    return PIPE_ERROR_OUT_OF_MEMORY;
 270 }
 271
 272
 273 struct svga_tracked_state svga_hw_rss =
 274 {
 275    "hw rss state",
 276
 277    (SVGA_NEW_BLEND |
 278     SVGA_NEW_BLEND_COLOR |
 279     SVGA_NEW_DEPTH_STENCIL |
 280     SVGA_NEW_STENCIL_REF |
 281     SVGA_NEW_RAST |
 282     SVGA_NEW_FRAME_BUFFER |
 283     SVGA_NEW_NEED_PIPELINE),
 284
 285    emit_rss
 286 };