sys/arch/arm/include/cpu.h

   1 #ifndef _ARM_CPU_H_
   2 #define _ARM_CPU_H_
   3
   4
   5 /* xPSR - Program Status Registers */
   6 #define PSR_T (1 << 5)  /* Thumb execution state bit */
   7 #define PSR_F (1 << 6)  /* FIQ mask bit */
   8 #define PSR_I (1 << 7)  /* IRQ mask bit */
   9 #define PSR_A (1 << 8)  /* Asynchronous abort mask bit */
  10 #define PSR_E (1 << 9)  /* Endianness execution state bit */
  11 #define PSR_J (1 << 24) /* Jazelle bit */
  12 #define PSR_Q (1 << 27) /* Cumulative saturation bit */
  13 #define PSR_V (1 << 28) /* Overflow condition flag */
  14 #define PSR_C (1 << 29) /* Carry condition flag */
  15 #define PSR_Z (1 << 30) /* Zero condition flag */
  16 #define PSR_N (1 << 31) /* Negative condition flag */
  17
  18 #define PSR_MODE_MASK 0x0000001F /* Mode field mask */
  19
  20 #define MODE_USR 0x10 /* User mode */
  21 #define MODE_FIQ 0x11 /* FIQ mode */
  22 #define MODE_IRQ 0x12 /* IRQ mode */
  23 #define MODE_SVC 0x13 /* Supervisor mode */
  24 #define MODE_MON 0x16 /* Monitor mode */
  25 #define MODE_ABT 0x17 /* Abort mode */
  26 #define MODE_HYP 0x1A /* Hyp mode */
  27 #define MODE_UND 0x1B /* Undefined mode */
  28 #define MODE_SYS 0x1F /* System mode */
  29
  30 /* SCTLR - System Control Register */
  31 #define SCTLR_M       (1 << 0)  /* MMU enable */
  32 #define SCTLR_A       (1 << 1)  /* Alignment check enable */
  33 #define SCTLR_C       (1 << 2)  /* Data and Unified Cache enable */
  34 #define SCTLR_CP15BEN (1 << 5)  /* CP15 barrier enable */
  35 #define SCTLR_SW      (1 << 10) /* SWP and SWPB enable */
  36 #define SCTLR_Z       (1 << 11) /* Branch prediction enable */
  37 #define SCTLR_I       (1 << 12) /* Instruction cache enable */
  38 #define SCTLR_V       (1 << 13) /* (High) Vectors bit */
  39 #define SCTLR_RR      (1 << 14) /* Round Robin (cache) select */
  40 #define SCTLR_HA      (1 << 17) /* Hardware Access flag enable */
  41 #define SCTLR_FI      (1 << 21) /* Fast interrupts configuration enable */
  42 #define SCTLR_VE      (1 << 24) /* Interrupt Vectors Enable */
  43 #define SCTLR_EE      (1 << 25) /* Exception Endianness */
  44 #define SCTLR_NMFI    (1 << 27) /* Non-maskable FIQ (NMFI) support */
  45 #define SCTLR_TRE     (1 << 28) /* TEX remap enable */
  46 #define SCTLR_AFE     (1 << 29) /* Access flag enable */
  47 #define SCTLR_TE      (1 << 30) /* Thumb Exception enable */
  48
  49 /* ACTLR - Auxiliary Control Register */
  50 #define A8_ACTLR_L1ALIAS    (1 << 0)  /* L1 Dcache hw alias check enable */
  51 #define A8_ACTLR_L2EN       (1 << 1)  /* L2 cache enable */
  52 #define A8_ACTLR_L1RSTDIS   (1 << 30) /* L1 hw reset disable */
  53 #define A8_ACTLR_L2RSTDIS   (1 << 31) /* L2 hw reset disable */
  54
  55 #endif /* _ARM_CPU_H_ */