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arm: make signal handlers work
[minix.git] / sys / arch / x86 / include / specialreg.h
blob7d3a34524dd3b660fd1c432f7c3d27b288d59bb6
1 /* $NetBSD: specialreg.h,v 1.59 2012/05/05 15:08:29 jym Exp $ */
2
3 /*-
4 * Copyright (c) 1991 The Regents of the University of California.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the University nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * @(#)specialreg.h 7.1 (Berkeley) 5/9/91
32 */
33
34 /*
35 * Bits in 386 special registers:
36 */
37 #define CR0_PE 0x00000001 /* Protected mode Enable */
38 #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */
39 #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */
40 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
41 #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */
42 #define CR0_PG 0x80000000 /* PaGing enable */
43
44 /*
45 * Bits in 486 special registers:
46 */
47 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
48 #define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */
49 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
50 #define CR0_NW 0x20000000 /* Not Write-through */
51 #define CR0_CD 0x40000000 /* Cache Disable */
52
53 /*
54 * Cyrix 486 DLC special registers, accessible as IO ports.
55 */
56 #define CCR0 0xc0 /* configuration control register 0 */
57 #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */
58 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
59 #define CCR0_A20M 0x04 /* enables A20M# input pin */
60 #define CCR0_KEN 0x08 /* enables KEN# input pin */
61 #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */
62 #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */
63 #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */
64 #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */
65
66 #define CCR1 0xc1 /* configuration control register 1 */
67 #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */
68 /* the remaining 7 bits of this register are reserved */
69
70 /*
71 * bits in the %cr4 control register:
72 */
73 #define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */
74 #define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */
75 #define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 */
76 #define CR4_DE 0x00000008 /* debugging extension */
77 #define CR4_PSE 0x00000010 /* large (4MB) page size enable */
78 #define CR4_PAE 0x00000020 /* physical address extension enable */
79 #define CR4_MCE 0x00000040 /* machine check enable */
80 #define CR4_PGE 0x00000080 /* page global enable */
81 #define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */
82 #define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */
83 #define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
84 #define CR4_VMXE 0x00002000 /* enable VMX operations */
85 #define CR4_SMXE 0x00004000 /* enable SMX operations */
86 #define CR4_FSGSBASE 0x00010000 /* enable *FSBASE and *GSBASE instructions */
87 #define CR4_PCIDE 0x00020000 /* enable Process Context IDentifiers */
88 #define CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */
89 #define CR4_SMEP 0x00100000 /* enable SMEP support */
90
91
92 /*
93 * CPUID "features" bits
94 */
95
96 /* Fn00000001 %edx features */
97 #define CPUID_FPU 0x00000001 /* processor has an FPU? */
98 #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */
99 #define CPUID_DE 0x00000004 /* has debugging extension */
100 #define CPUID_PSE 0x00000008 /* has page 4MB page size extension */
101 #define CPUID_TSC 0x00000010 /* has time stamp counter */
102 #define CPUID_MSR 0x00000020 /* has mode specific registers */
103 #define CPUID_PAE 0x00000040 /* has phys address extension */
104 #define CPUID_MCE 0x00000080 /* has machine check exception */
105 #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */
106 #define CPUID_APIC 0x00000200 /* has enabled APIC */
107 #define CPUID_B10 0x00000400 /* reserved, MTRR */
108 #define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */
109 #define CPUID_MTRR 0x00001000 /* has memory type range register */
110 #define CPUID_PGE 0x00002000 /* has page global extension */
111 #define CPUID_MCA 0x00004000 /* has machine check architecture */
112 #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */
113 #define CPUID_PAT 0x00010000 /* Page Attribute Table */
114 #define CPUID_PSE36 0x00020000 /* 36-bit PSE */
115 #define CPUID_PN 0x00040000 /* processor serial number */
116 #define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */
117 #define CPUID_B20 0x00100000 /* reserved */
118 #define CPUID_DS 0x00200000 /* Debug Store */
119 #define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */
120 #define CPUID_MMX 0x00800000 /* MMX supported */
121 #define CPUID_FXSR 0x01000000 /* fast FP/MMX save/restore */
122 #define CPUID_SSE 0x02000000 /* streaming SIMD extensions */
123 #define CPUID_SSE2 0x04000000 /* streaming SIMD extensions #2 */
124 #define CPUID_SS 0x08000000 /* self-snoop */
125 #define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */
126 #define CPUID_TM 0x20000000 /* thermal monitor (TCC) */
127 #define CPUID_IA64 0x40000000 /* IA-64 architecture */
128 #define CPUID_SBF 0x80000000 /* signal break on FERR */
129
130 #define CPUID_FLAGS1 "\20\1FPU\2VME\3DE\4PSE\5TSC\6MSR\7PAE\10MCE\11CX8" \
131 "\12APIC\13B10\14SEP\15MTRR\16PGE\17MCA\20CMOV" \
132 "\21PAT\22PSE36\23PN\24CFLUSH\25B20\26DS\27ACPI" \
133 "\30MMX\31FXSR\32SSE\33SSE2\34SS\35HTT\36TM" \
134 "\37IA64\40SBF"
135
136 /*
137 * Intel Digital Thermal Sensor and
138 * Power Management, Fn0000_0006 - %eax.
139 */
140 #define CPUID_DSPM_DTS 0x00000001 /* Digital Thermal Sensor */
141 #define CPUID_DSPM_IDA 0x00000002 /* Intel Dynamic Acceleration */
142 #define CPUID_DSPM_ARAT 0x00000004 /* Always Running APIC Timer */
143 #define CPUID_DSPM_PLN 0x00000010 /* Power Limit Notification */
144 #define CPUID_DSPM_CME 0x00000020 /* Clock Modulation Extension */
145 #define CPUID_DSPM_PLTM 0x00000040 /* Package Level Thermal Management */
146
147 #define CPUID_DSPM_FLAGS "\20\1DTS\2IDA\3ARAT\5PLN\6CME\7PLTM"
148
149 /*
150 * Intel Digital Thermal Sensor and
151 * Power Management, Fn0000_0006 - %ecx.
152 */
153 #define CPUID_DSPM_HWF 0x00000001 /* MSR_APERF/MSR_MPERF available */
154
155 #define CPUID_DSPM_FLAGS1 "\20\1HWF"
156
157 /* Intel Fn80000001 extended features - %edx */
158 #define CPUID_SYSCALL 0x00000800 /* SYSCALL/SYSRET */
159 #define CPUID_XD 0x00100000 /* Execute Disable (like CPUID_NOX) */
160 #define CPUID_EM64T 0x20000000 /* Intel EM64T */
161
162 #define CPUID_INTEL_EXT_FLAGS "\20\14SYSCALL/SYSRET\25XD\36EM64T"
163
164 /* Intel Fn80000001 extended features - %ecx */
165 #define CPUID_LAHF 0x00000001 /* LAHF/SAHF in IA-32e mode, 64bit sub*/
166
167 #define CPUID_INTEL_FLAGS4 "\20\1LAHF\02B02\03B03"
168
169
170 /* AMD/VIA Fn80000001 extended features - %edx */
171 /* CPUID_SYSCALL SYSCALL/SYSRET */
172 #define CPUID_MPC 0x00080000 /* Multiprocessing Capable */
173 #define CPUID_NOX 0x00100000 /* No Execute Page Protection */
174 #define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */
175 #define CPUID_FFXSR 0x02000000 /* FXSAVE/FXSTOR Extensions */
176 #define CPUID_P1GB 0x04000000 /* 1GB Large Page Support */
177 #define CPUID_RDTSCP 0x08000000 /* Read TSC Pair Instruction */
178 /* CPUID_EM64T Long mode */
179 #define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */
180 #define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */
181
182 #define CPUID_EXT_FLAGS "\20\14SYSCALL/SYSRET\24MPC\25NOX" \
183 "\27MXX\32FFXSR\33P1GB\34RDTSCP" \
184 "\36LONG\0373DNOW2\0403DNOW" \
185
186 /* AMD Fn80000001 extended features - %ecx */
187 /* CPUID_LAHF LAHF/SAHF instruction */
188 #define CPUID_CMPLEGACY 0x00000002 /* Compare Legacy */
189 #define CPUID_SVM 0x00000004 /* Secure Virtual Machine */
190 #define CPUID_EAPIC 0x00000008 /* Extended APIC space */
191 #define CPUID_ALTMOVCR0 0x00000010 /* Lock Mov Cr0 */
192 #define CPUID_LZCNT 0x00000020 /* LZCNT instruction */
193 #define CPUID_SSE4A 0x00000040 /* SSE4A instruction set */
194 #define CPUID_MISALIGNSSE 0x00000080 /* Misaligned SSE */
195 #define CPUID_3DNOWPF 0x00000100 /* 3DNow Prefetch */
196 #define CPUID_OSVW 0x00000200 /* OS visible workarounds */
197 #define CPUID_IBS 0x00000400 /* Instruction Based Sampling */
198 #define CPUID_XOP 0x00000800 /* XOP instruction set */
199 #define CPUID_SKINIT 0x00001000 /* SKINIT */
200 #define CPUID_WDT 0x00002000 /* watchdog timer support */
201 #define CPUID_LWP 0x00008000 /* Light Weight Profiling */
202 #define CPUID_FMA4 0x00010000 /* FMA4 instructions */
203 #define CPUID_NODEID 0x00080000 /* NodeID MSR available*/
204 #define CPUID_TBM 0x00200000 /* TBM instructions */
205 #define CPUID_TOPOEXT 0x00400000 /* cpuid Topology Extension */
206
207 #define CPUID_AMD_FLAGS4 "\20\1LAHF\2CMPLEGACY\3SVM\4EAPIC\5ALTMOVCR0" \
208 "\6LZCNT\7SSE4A\10MISALIGNSSE" \
209 "\0113DNOWPREFETCH\12OSVW\13IBS" \
210 "\14XOP\15SKINIT\16WDT\20LWP" \
211 "\21FMA4\22B17\23B18\24NodeID\25B20\26TBM" \
212 "\27TopoExt\30B23\31B24" \
213 "\32B25\33B25\34B26" \
214 "\35B27\36B28\37B29\40B30\41B31\42B32"
215
216 /* AMD Fn8000000a %edx features (SVM features) */
217 #define CPUID_AMD_SVM_NP 0x00000001
218 #define CPUID_AMD_SVM_LbrVirt 0x00000002
219 #define CPUID_AMD_SVM_SVML 0x00000004
220 #define CPUID_AMD_SVM_NRIPS 0x00000008
221 #define CPUID_AMD_SVM_TSCRateCtrl 0x00000010
222 #define CPUID_AMD_SVM_VMCBCleanBits 0x00000020
223 #define CPUID_AMD_SVM_FlushByASID 0x00000040
224 #define CPUID_AMD_SVM_DecodeAssist 0x00000080
225 #define CPUID_AMD_SVM_PauseFilter 0x00000400
226 #define CPUID_AMD_SVM_FLAGS "\20\1NP\2LbrVirt\3SVML\4NRIPS" \
227 "\5TSCRate\6VMCBCleanBits\7FlushByASID" \
228 "\10DecodeAssist\11B08" \
229 "\12B09\13PauseFilter" \
230 "\14B11\15B12" \
231 "\16B13\17B17\20B18\21B19"
232
233 /*
234 * AMD Advanced Power Management
235 * CPUID Fn8000_0007 %edx
236 */
237 #define CPUID_APM_TS 0x00000001 /* Temperature Sensor */
238 #define CPUID_APM_FID 0x00000002 /* Frequency ID control */
239 #define CPUID_APM_VID 0x00000004 /* Voltage ID control */
240 #define CPUID_APM_TTP 0x00000008 /* THERMTRIP (PCI F3xE4 register) */
241 #define CPUID_APM_HTC 0x00000010 /* Hardware thermal control (HTC) */
242 #define CPUID_APM_STC 0x00000020 /* Software thermal control (STC) */
243 #define CPUID_APM_100 0x00000040 /* 100MHz multiplier control */
244 #define CPUID_APM_HWP 0x00000080 /* HW P-State control */
245 #define CPUID_APM_TSC 0x00000100 /* TSC invariant */
246 #define CPUID_APM_CPB 0x00000200 /* Core performance boost */
247 #define CPUID_APM_EFF 0x00000400 /* Effective Frequency (read-only) */
248
249 #define CPUID_APM_FLAGS "\20\1TS\2FID\3VID\4TTP\5HTC\6STC\007100" \
250 "\10HWP\11TSC\12CPB\13EffFreq\14B11\15B12"
251
252 /*
253 * Centaur Extended Feature flags
254 */
255 #define CPUID_VIA_HAS_RNG 0x00000004 /* Random number generator */
256 #define CPUID_VIA_DO_RNG 0x00000008
257 #define CPUID_VIA_HAS_ACE 0x00000040 /* AES Encryption */
258 #define CPUID_VIA_DO_ACE 0x00000080
259 #define CPUID_VIA_HAS_ACE2 0x00000100 /* AES+CTR instructions */
260 #define CPUID_VIA_DO_ACE2 0x00000200
261 #define CPUID_VIA_HAS_PHE 0x00000400 /* SHA1+SHA256 HMAC */
262 #define CPUID_VIA_DO_PHE 0x00000800
263 #define CPUID_VIA_HAS_PMM 0x00001000 /* RSA Instructions */
264 #define CPUID_VIA_DO_PMM 0x00002000
265
266 #define CPUID_FLAGS_PADLOCK "\20\3RNG\7AES\11AES/CTR\13SHA1/SHA256\15RSA"
267
268 /*
269 * CPUID "features" bits in Fn00000001 %ecx
270 */
271
272 #define CPUID2_SSE3 0x00000001 /* Streaming SIMD Extensions 3 */
273 #define CPUID2_PCLMUL 0x00000002 /* PCLMULQDQ instructions */
274 #define CPUID2_DTES64 0x00000004 /* 64-bit Debug Trace */
275 #define CPUID2_MONITOR 0x00000008 /* MONITOR/MWAIT instructions */
276 #define CPUID2_DS_CPL 0x00000010 /* CPL Qualified Debug Store */
277 #define CPUID2_VMX 0x00000020 /* Virtual Machine Extensions */
278 #define CPUID2_SMX 0x00000040 /* Safer Mode Extensions */
279 #define CPUID2_EST 0x00000080 /* Enhanced SpeedStep Technology */
280 #define CPUID2_TM2 0x00000100 /* Thermal Monitor 2 */
281 #define CPUID2_SSSE3 0x00000200 /* Supplemental SSE3 */
282 #define CPUID2_CID 0x00000400 /* Context ID */
283 #define CPUID2_CX16 0x00002000 /* has CMPXCHG16B instruction */
284 #define CPUID2_xTPR 0x00004000 /* Task Priority Messages disabled? */
285 #define CPUID2_PDCM 0x00008000 /* Perf/Debug Capability MSR */
286 #define CPUID2_PCID 0x00020000 /* Process Context ID */
287 #define CPUID2_DCA 0x00040000 /* Direct Cache Access */
288 #define CPUID2_SSE41 0x00080000 /* Streaming SIMD Extensions 4.1 */
289 #define CPUID2_SSE42 0x00100000 /* Streaming SIMD Extensions 4.2 */
290 #define CPUID2_X2APIC 0x00200000 /* xAPIC Extensions */
291 #define CPUID2_POPCNT 0x00800000 /* popcount instruction available */
292 #define CPUID2_AES 0x02000000 /* AES instructions */
293 #define CPUID2_XSAVE 0x04000000 /* XSAVE instructions */
294 #define CPUID2_OSXSAVE 0x08000000 /* XGETBV/XSETBV instructions */
295 #define CPUID2_AVX 0x10000000 /* AVX instructions */
296 #define CPUID2_F16C 0x20000000 /* half precision conversion */
297 #define CPUID2_RAZ 0x80000000 /* RAZ. Indicates guest state. */
298
299 #define CPUID2_FLAGS1 "\20\1SSE3\2PCLMULQDQ\3DTES64\4MONITOR\5DS-CPL\6VMX\7SMX" \
300 "\10EST\11TM2\12SSSE3\13CID\14B11\15B12\16CX16" \
301 "\17xTPR\20PDCM\21B16\22PCID\23DCA\24SSE41\25SSE42" \
302 "\26X2APIC\27MOVBE\30POPCNT\31B24\32AES\33XSAVE" \
303 "\34OSXSAVE\35AVX\36F16C\37B30\40RAZ"
304
305 #define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 0xf)
306 #define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 0xf)
307 #define CPUID2STEPPING(cpuid) ((cpuid) & 0xf)
308
309 /* Extended family and model are defined on amd64 processors */
310 #define CPUID2EXTFAMILY(cpuid) (((cpuid) >> 20) & 0xff)
311 #define CPUID2EXTMODEL(cpuid) (((cpuid) >> 16) & 0xf)
312
313 /* Blacklists of CPUID flags - used to mask certain features */
314 #ifdef XEN
315 /* Not on Xen */
316 #define CPUID_FEAT_BLACKLIST (CPUID_PGE|CPUID_PSE|CPUID_MTRR)
317 #else
318 #define CPUID_FEAT_BLACKLIST 0
319 #endif /* XEN */
320
321 /*
322 * Model-specific registers for the i386 family
323 */
324 #define MSR_P5_MC_ADDR 0x000 /* P5 only */
325 #define MSR_P5_MC_TYPE 0x001 /* P5 only */
326 #define MSR_TSC 0x010
327 #define MSR_CESR 0x011 /* P5 only (trap on P6) */
328 #define MSR_CTR0 0x012 /* P5 only (trap on P6) */
329 #define MSR_CTR1 0x013 /* P5 only (trap on P6) */
330 #define MSR_APICBASE 0x01b
331 #define MSR_EBL_CR_POWERON 0x02a
332 #define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */
333 #define MSR_TEST_CTL 0x033
334 #define MSR_BIOS_UPDT_TRIG 0x079
335 #define MSR_BBL_CR_D0 0x088 /* PII+ only */
336 #define MSR_BBL_CR_D1 0x089 /* PII+ only */
337 #define MSR_BBL_CR_D2 0x08a /* PII+ only */
338 #define MSR_BIOS_SIGN 0x08b
339 #define MSR_PERFCTR0 0x0c1
340 #define MSR_PERFCTR1 0x0c2
341 #define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */
342 #define MSR_MPERF 0x0e7
343 #define MSR_APERF 0x0e8
344 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
345 #define MSR_MTRRcap 0x0fe
346 #define MSR_BBL_CR_ADDR 0x116 /* PII+ only */
347 #define MSR_BBL_CR_DECC 0x118 /* PII+ only */
348 #define MSR_BBL_CR_CTL 0x119 /* PII+ only */
349 #define MSR_BBL_CR_TRIG 0x11a /* PII+ only */
350 #define MSR_BBL_CR_BUSY 0x11b /* PII+ only */
351 #define MSR_BBL_CR_CTR3 0x11e /* PII+ only */
352 #define MSR_SYSENTER_CS 0x174 /* PII+ only */
353 #define MSR_SYSENTER_ESP 0x175 /* PII+ only */
354 #define MSR_SYSENTER_EIP 0x176 /* PII+ only */
355 #define MSR_MCG_CAP 0x179
356 #define MSR_MCG_STATUS 0x17a
357 #define MSR_MCG_CTL 0x17b
358 #define MSR_EVNTSEL0 0x186
359 #define MSR_EVNTSEL1 0x187
360 #define MSR_PERF_STATUS 0x198 /* Pentium M */
361 #define MSR_PERF_CTL 0x199 /* Pentium M */
362 #define MSR_THERM_CONTROL 0x19a
363 #define MSR_THERM_INTERRUPT 0x19b
364 #define MSR_THERM_STATUS 0x19c
365 #define MSR_THERM2_CTL 0x19d /* Pentium M */
366 #define MSR_MISC_ENABLE 0x1a0
367 #define MSR_TEMPERATURE_TARGET 0x1a2
368 #define MSR_DEBUGCTLMSR 0x1d9
369 #define MSR_LASTBRANCHFROMIP 0x1db
370 #define MSR_LASTBRANCHTOIP 0x1dc
371 #define MSR_LASTINTFROMIP 0x1dd
372 #define MSR_LASTINTTOIP 0x1de
373 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0
374 #define MSR_MTRRphysBase0 0x200
375 #define MSR_MTRRphysMask0 0x201
376 #define MSR_MTRRphysBase1 0x202
377 #define MSR_MTRRphysMask1 0x203
378 #define MSR_MTRRphysBase2 0x204
379 #define MSR_MTRRphysMask2 0x205
380 #define MSR_MTRRphysBase3 0x206
381 #define MSR_MTRRphysMask3 0x207
382 #define MSR_MTRRphysBase4 0x208
383 #define MSR_MTRRphysMask4 0x209
384 #define MSR_MTRRphysBase5 0x20a
385 #define MSR_MTRRphysMask5 0x20b
386 #define MSR_MTRRphysBase6 0x20c
387 #define MSR_MTRRphysMask6 0x20d
388 #define MSR_MTRRphysBase7 0x20e
389 #define MSR_MTRRphysMask7 0x20f
390 #define MSR_MTRRphysBase8 0x210
391 #define MSR_MTRRphysMask8 0x211
392 #define MSR_MTRRphysBase9 0x212
393 #define MSR_MTRRphysMask9 0x213
394 #define MSR_MTRRphysBase10 0x214
395 #define MSR_MTRRphysMask10 0x215
396 #define MSR_MTRRphysBase11 0x216
397 #define MSR_MTRRphysMask11 0x217
398 #define MSR_MTRRphysBase12 0x218
399 #define MSR_MTRRphysMask12 0x219
400 #define MSR_MTRRphysBase13 0x21a
401 #define MSR_MTRRphysMask13 0x21b
402 #define MSR_MTRRphysBase14 0x21c
403 #define MSR_MTRRphysMask14 0x21d
404 #define MSR_MTRRphysBase15 0x21e
405 #define MSR_MTRRphysMask15 0x21f
406 #define MSR_MTRRfix64K_00000 0x250
407 #define MSR_MTRRfix16K_80000 0x258
408 #define MSR_MTRRfix16K_A0000 0x259
409 #define MSR_MTRRfix4K_C0000 0x268
410 #define MSR_MTRRfix4K_C8000 0x269
411 #define MSR_MTRRfix4K_D0000 0x26a
412 #define MSR_MTRRfix4K_D8000 0x26b
413 #define MSR_MTRRfix4K_E0000 0x26c
414 #define MSR_MTRRfix4K_E8000 0x26d
415 #define MSR_MTRRfix4K_F0000 0x26e
416 #define MSR_MTRRfix4K_F8000 0x26f
417 #define MSR_CR_PAT 0x277
418 #define MSR_MTRRdefType 0x2ff
419 #define MSR_MC0_CTL 0x400
420 #define MSR_MC0_STATUS 0x401
421 #define MSR_MC0_ADDR 0x402
422 #define MSR_MC0_MISC 0x403
423 #define MSR_MC1_CTL 0x404
424 #define MSR_MC1_STATUS 0x405
425 #define MSR_MC1_ADDR 0x406
426 #define MSR_MC1_MISC 0x407
427 #define MSR_MC2_CTL 0x408
428 #define MSR_MC2_STATUS 0x409
429 #define MSR_MC2_ADDR 0x40a
430 #define MSR_MC2_MISC 0x40b
431 #define MSR_MC4_CTL 0x40c
432 #define MSR_MC4_STATUS 0x40d
433 #define MSR_MC4_ADDR 0x40e
434 #define MSR_MC4_MISC 0x40f
435 #define MSR_MC3_CTL 0x410
436 #define MSR_MC3_STATUS 0x411
437 #define MSR_MC3_ADDR 0x412
438 #define MSR_MC3_MISC 0x413
439 /* 0x480 - 0x490 VMX */
440
441 /*
442 * VIA "Nehemiah" MSRs
443 */
444 #define MSR_VIA_RNG 0x0000110b
445 #define MSR_VIA_RNG_ENABLE 0x00000040
446 #define MSR_VIA_RNG_NOISE_MASK 0x00000300
447 #define MSR_VIA_RNG_NOISE_A 0x00000000
448 #define MSR_VIA_RNG_NOISE_B 0x00000100
449 #define MSR_VIA_RNG_2NOISE 0x00000300
450 #define MSR_VIA_ACE 0x00001107
451 #define MSR_VIA_ACE_ENABLE 0x10000000
452
453 /*
454 * VIA "Eden" MSRs
455 */
456 #define MSR_VIA_FCR MSR_VIA_ACE
457
458 /*
459 * AMD K6/K7 MSRs.
460 */
461 #define MSR_K6_UWCCR 0xc0000085
462 #define MSR_K7_EVNTSEL0 0xc0010000
463 #define MSR_K7_EVNTSEL1 0xc0010001
464 #define MSR_K7_EVNTSEL2 0xc0010002
465 #define MSR_K7_EVNTSEL3 0xc0010003
466 #define MSR_K7_PERFCTR0 0xc0010004
467 #define MSR_K7_PERFCTR1 0xc0010005
468 #define MSR_K7_PERFCTR2 0xc0010006
469 #define MSR_K7_PERFCTR3 0xc0010007
470
471 /*
472 * AMD K8 (Opteron) MSRs.
473 */
474 #define MSR_SYSCFG 0xc0000010
475
476 #define MSR_EFER 0xc0000080 /* Extended feature enable */
477 #define EFER_SCE 0x00000001 /* SYSCALL extension */
478 #define EFER_LME 0x00000100 /* Long Mode Active */
479 #define EFER_LMA 0x00000400 /* Long Mode Enabled */
480 #define EFER_NXE 0x00000800 /* No-Execute Enabled */
481
482 #define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */
483 #define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */
484 #define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */
485 #define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */
486
487 #define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */
488 #define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */
489 #define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */
490
491 #define MSR_VMCR 0xc0010114 /* Virtual Machine Control Register */
492 #define VMCR_DPD 0x00000001 /* Debug port disable */
493 #define VMCR_RINIT 0x00000002 /* intercept init */
494 #define VMCR_DISA20 0x00000004 /* Disable A20 masking */
495 #define VMCR_LOCK 0x00000008 /* SVM Lock */
496 #define VMCR_SVMED 0x00000010 /* SVME Disable */
497 #define MSR_SVMLOCK 0xc0010118 /* SVM Lock key */
498
499 /*
500 * These require a 'passcode' for access. See cpufunc.h.
501 */
502 #define MSR_HWCR 0xc0010015
503 #define HWCR_TLBCACHEDIS 0x00000008
504 #define HWCR_FFDIS 0x00000040
505
506 #define MSR_NB_CFG 0xc001001f
507 #define NB_CFG_DISIOREQLOCK 0x0000000000000008ULL
508 #define NB_CFG_DISDATMSK 0x0000001000000000ULL
509 #define NB_CFG_INITAPICCPUIDLO (1ULL << 54)
510
511 #define MSR_LS_CFG 0xc0011020
512 #define LS_CFG_DIS_LS2_SQUISH 0x02000000
513
514 #define MSR_IC_CFG 0xc0011021
515 #define IC_CFG_DIS_SEQ_PREFETCH 0x00000800
516
517 #define MSR_DC_CFG 0xc0011022
518 #define DC_CFG_DIS_CNV_WC_SSO 0x00000008
519 #define DC_CFG_DIS_SMC_CHK_BUF 0x00000400
520 #define DC_CFG_ERRATA_261 0x01000000
521
522 #define MSR_BU_CFG 0xc0011023
523 #define BU_CFG_ERRATA_298 0x0000000000000002ULL
524 #define BU_CFG_ERRATA_254 0x0000000000200000ULL
525 #define BU_CFG_ERRATA_309 0x0000000000800000ULL
526 #define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL
527 #define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL
528 #define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL
529
530 #define MSR_DE_CFG 0xc0011029
531 #define DE_CFG_ERRATA_721 0x00000001
532
533 /* AMD Family10h MSRs */
534 #define MSR_OSVW_ID_LENGTH 0xc0010140
535 #define MSR_OSVW_STATUS 0xc0010141
536 #define MSR_UCODE_AMD_PATCHLEVEL 0x0000008b
537 #define MSR_UCODE_AMD_PATCHLOADER 0xc0010020
538
539 /* X86 MSRs */
540 #define MSR_RDTSCP_AUX 0xc0000103
541
542 /*
543 * Constants related to MTRRs
544 */
545 #define MTRR_N64K 8 /* numbers of fixed-size entries */
546 #define MTRR_N16K 16
547 #define MTRR_N4K 64
548
549 /*
550 * the following four 3-byte registers control the non-cacheable regions.
551 * These registers must be written as three separate bytes.
552 *
553 * NCRx+0: A31-A24 of starting address
554 * NCRx+1: A23-A16 of starting address
555 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
556 *
557 * The non-cacheable region's starting address must be aligned to the
558 * size indicated by the NCR_SIZE_xx field.
559 */
560 #define NCR1 0xc4
561 #define NCR2 0xc7
562 #define NCR3 0xca
563 #define NCR4 0xcd
564
565 #define NCR_SIZE_0K 0
566 #define NCR_SIZE_4K 1
567 #define NCR_SIZE_8K 2
568 #define NCR_SIZE_16K 3
569 #define NCR_SIZE_32K 4
570 #define NCR_SIZE_64K 5
571 #define NCR_SIZE_128K 6
572 #define NCR_SIZE_256K 7
573 #define NCR_SIZE_512K 8
574 #define NCR_SIZE_1M 9
575 #define NCR_SIZE_2M 10
576 #define NCR_SIZE_4M 11
577 #define NCR_SIZE_8M 12
578 #define NCR_SIZE_16M 13
579 #define NCR_SIZE_32M 14
580 #define NCR_SIZE_4G 15
581
582 /*
583 * Performance monitor events.
584 *
585 * Note that 586-class and 686-class CPUs have different performance
586 * monitors available, and they are accessed differently:
587 *
588 * 686-class: `rdpmc' instruction
589 * 586-class: `rdmsr' instruction, CESR MSR
590 *
591 * The descriptions of these events are too lenghy to include here.
592 * See Appendix A of "Intel Architecture Software Developer's
593 * Manual, Volume 3: System Programming" for more information.
594 */
595
596 /*
597 * 586-class CESR MSR format. Lower 16 bits is CTR0, upper 16 bits
598 * is CTR1.
599 */
600
601 #define PMC5_CESR_EVENT 0x003f
602 #define PMC5_CESR_OS 0x0040
603 #define PMC5_CESR_USR 0x0080
604 #define PMC5_CESR_E 0x0100
605 #define PMC5_CESR_P 0x0200
606
607 #define PMC5_DATA_READ 0x00
608 #define PMC5_DATA_WRITE 0x01
609 #define PMC5_DATA_TLB_MISS 0x02
610 #define PMC5_DATA_READ_MISS 0x03
611 #define PMC5_DATA_WRITE_MISS 0x04
612 #define PMC5_WRITE_M_E 0x05
613 #define PMC5_DATA_LINES_WBACK 0x06
614 #define PMC5_DATA_CACHE_SNOOP 0x07
615 #define PMC5_DATA_CACHE_SNOOP_HIT 0x08
616 #define PMC5_MEM_ACCESS_BOTH_PIPES 0x09
617 #define PMC5_BANK_CONFLICTS 0x0a
618 #define PMC5_MISALIGNED_DATA 0x0b
619 #define PMC5_INST_READ 0x0c
620 #define PMC5_INST_TLB_MISS 0x0d
621 #define PMC5_INST_CACHE_MISS 0x0e
622 #define PMC5_SEGMENT_REG_LOAD 0x0f
623 #define PMC5_BRANCHES 0x12
624 #define PMC5_BTB_HITS 0x13
625 #define PMC5_BRANCH_TAKEN 0x14
626 #define PMC5_PIPELINE_FLUSH 0x15
627 #define PMC5_INST_EXECUTED 0x16
628 #define PMC5_INST_EXECUTED_V_PIPE 0x17
629 #define PMC5_BUS_UTILIZATION 0x18
630 #define PMC5_WRITE_BACKUP_STALL 0x19
631 #define PMC5_DATA_READ_STALL 0x1a
632 #define PMC5_WRITE_E_M_STALL 0x1b
633 #define PMC5_LOCKED_BUS 0x1c
634 #define PMC5_IO_CYCLE 0x1d
635 #define PMC5_NONCACHE_MEM_READ 0x1e
636 #define PMC5_AGI_STALL 0x1f
637 #define PMC5_FLOPS 0x22
638 #define PMC5_BP0_MATCH 0x23
639 #define PMC5_BP1_MATCH 0x24
640 #define PMC5_BP2_MATCH 0x25
641 #define PMC5_BP3_MATCH 0x26
642 #define PMC5_HARDWARE_INTR 0x27
643 #define PMC5_DATA_RW 0x28
644 #define PMC5_DATA_RW_MISS 0x29
645
646 /*
647 * 686-class Event Selector MSR format.
648 */
649
650 #define PMC6_EVTSEL_EVENT 0x000000ff
651 #define PMC6_EVTSEL_UNIT 0x0000ff00
652 #define PMC6_EVTSEL_UNIT_SHIFT 8
653 #define PMC6_EVTSEL_USR (1 << 16)
654 #define PMC6_EVTSEL_OS (1 << 17)
655 #define PMC6_EVTSEL_E (1 << 18)
656 #define PMC6_EVTSEL_PC (1 << 19)
657 #define PMC6_EVTSEL_INT (1 << 20)
658 #define PMC6_EVTSEL_EN (1 << 22) /* PerfEvtSel0 only */
659 #define PMC6_EVTSEL_INV (1 << 23)
660 #define PMC6_EVTSEL_COUNTER_MASK 0xff000000
661 #define PMC6_EVTSEL_COUNTER_MASK_SHIFT 24
662
663 /* Data Cache Unit */
664 #define PMC6_DATA_MEM_REFS 0x43
665 #define PMC6_DCU_LINES_IN 0x45
666 #define PMC6_DCU_M_LINES_IN 0x46
667 #define PMC6_DCU_M_LINES_OUT 0x47
668 #define PMC6_DCU_MISS_OUTSTANDING 0x48
669
670 /* Instruction Fetch Unit */
671 #define PMC6_IFU_IFETCH 0x80
672 #define PMC6_IFU_IFETCH_MISS 0x81
673 #define PMC6_ITLB_MISS 0x85
674 #define PMC6_IFU_MEM_STALL 0x86
675 #define PMC6_ILD_STALL 0x87
676
677 /* L2 Cache */
678 #define PMC6_L2_IFETCH 0x28
679 #define PMC6_L2_LD 0x29
680 #define PMC6_L2_ST 0x2a
681 #define PMC6_L2_LINES_IN 0x24
682 #define PMC6_L2_LINES_OUT 0x26
683 #define PMC6_L2_M_LINES_INM 0x25
684 #define PMC6_L2_M_LINES_OUTM 0x27
685 #define PMC6_L2_RQSTS 0x2e
686 #define PMC6_L2_ADS 0x21
687 #define PMC6_L2_DBUS_BUSY 0x22
688 #define PMC6_L2_DBUS_BUSY_RD 0x23
689
690 /* External Bus Logic */
691 #define PMC6_BUS_DRDY_CLOCKS 0x62
692 #define PMC6_BUS_LOCK_CLOCKS 0x63
693 #define PMC6_BUS_REQ_OUTSTANDING 0x60
694 #define PMC6_BUS_TRAN_BRD 0x65
695 #define PMC6_BUS_TRAN_RFO 0x66
696 #define PMC6_BUS_TRANS_WB 0x67
697 #define PMC6_BUS_TRAN_IFETCH 0x68
698 #define PMC6_BUS_TRAN_INVAL 0x69
699 #define PMC6_BUS_TRAN_PWR 0x6a
700 #define PMC6_BUS_TRANS_P 0x6b
701 #define PMC6_BUS_TRANS_IO 0x6c
702 #define PMC6_BUS_TRAN_DEF 0x6d
703 #define PMC6_BUS_TRAN_BURST 0x6e
704 #define PMC6_BUS_TRAN_ANY 0x70
705 #define PMC6_BUS_TRAN_MEM 0x6f
706 #define PMC6_BUS_DATA_RCV 0x64
707 #define PMC6_BUS_BNR_DRV 0x61
708 #define PMC6_BUS_HIT_DRV 0x7a
709 #define PMC6_BUS_HITM_DRDV 0x7b
710 #define PMC6_BUS_SNOOP_STALL 0x7e
711
712 /* Floating Point Unit */
713 #define PMC6_FLOPS 0xc1
714 #define PMC6_FP_COMP_OPS_EXE 0x10
715 #define PMC6_FP_ASSIST 0x11
716 #define PMC6_MUL 0x12
717 #define PMC6_DIV 0x12
718 #define PMC6_CYCLES_DIV_BUSY 0x14
719
720 /* Memory Ordering */
721 #define PMC6_LD_BLOCKS 0x03
722 #define PMC6_SB_DRAINS 0x04
723 #define PMC6_MISALIGN_MEM_REF 0x05
724 #define PMC6_EMON_KNI_PREF_DISPATCHED 0x07 /* P-III only */
725 #define PMC6_EMON_KNI_PREF_MISS 0x4b /* P-III only */
726
727 /* Instruction Decoding and Retirement */
728 #define PMC6_INST_RETIRED 0xc0
729 #define PMC6_UOPS_RETIRED 0xc2
730 #define PMC6_INST_DECODED 0xd0
731 #define PMC6_EMON_KNI_INST_RETIRED 0xd8
732 #define PMC6_EMON_KNI_COMP_INST_RET 0xd9
733
734 /* Interrupts */
735 #define PMC6_HW_INT_RX 0xc8
736 #define PMC6_CYCLES_INT_MASKED 0xc6
737 #define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7
738
739 /* Branches */
740 #define PMC6_BR_INST_RETIRED 0xc4
741 #define PMC6_BR_MISS_PRED_RETIRED 0xc5
742 #define PMC6_BR_TAKEN_RETIRED 0xc9
743 #define PMC6_BR_MISS_PRED_TAKEN_RET 0xca
744 #define PMC6_BR_INST_DECODED 0xe0
745 #define PMC6_BTB_MISSES 0xe2
746 #define PMC6_BR_BOGUS 0xe4
747 #define PMC6_BACLEARS 0xe6
748
749 /* Stalls */
750 #define PMC6_RESOURCE_STALLS 0xa2
751 #define PMC6_PARTIAL_RAT_STALLS 0xd2
752
753 /* Segment Register Loads */
754 #define PMC6_SEGMENT_REG_LOADS 0x06
755
756 /* Clocks */
757 #define PMC6_CPU_CLK_UNHALTED 0x79
758
759 /* MMX Unit */
760 #define PMC6_MMX_INSTR_EXEC 0xb0 /* Celeron, P-II, P-IIX only */
761 #define PMC6_MMX_SAT_INSTR_EXEC 0xb1 /* P-II and P-III only */
762 #define PMC6_MMX_UOPS_EXEC 0xb2 /* P-II and P-III only */
763 #define PMC6_MMX_INSTR_TYPE_EXEC 0xb3 /* P-II and P-III only */
764 #define PMC6_FP_MMX_TRANS 0xcc /* P-II and P-III only */
765 #define PMC6_MMX_ASSIST 0xcd /* P-II and P-III only */
766 #define PMC6_MMX_INSTR_RET 0xc3 /* P-II only */
767
768 /* Segment Register Renaming */
769 #define PMC6_SEG_RENAME_STALLS 0xd4 /* P-II and P-III only */
770 #define PMC6_SEG_REG_RENAMES 0xd5 /* P-II and P-III only */
771 #define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */
772
773 /*
774 * AMD K7 Event Selector MSR format.
775 */
776
777 #define K7_EVTSEL_EVENT 0x000000ff
778 #define K7_EVTSEL_UNIT 0x0000ff00
779 #define K7_EVTSEL_UNIT_SHIFT 8
780 #define K7_EVTSEL_USR (1 << 16)
781 #define K7_EVTSEL_OS (1 << 17)
782 #define K7_EVTSEL_E (1 << 18)
783 #define K7_EVTSEL_PC (1 << 19)
784 #define K7_EVTSEL_INT (1 << 20)
785 #define K7_EVTSEL_EN (1 << 22)
786 #define K7_EVTSEL_INV (1 << 23)
787 #define K7_EVTSEL_COUNTER_MASK 0xff000000
788 #define K7_EVTSEL_COUNTER_MASK_SHIFT 24
789
790 /* Segment Register Loads */
791 #define K7_SEGMENT_REG_LOADS 0x20
792
793 #define K7_STORES_TO_ACTIVE_INST_STREAM 0x21
794
795 /* Data Cache Unit */
796 #define K7_DATA_CACHE_ACCESS 0x40
797 #define K7_DATA_CACHE_MISS 0x41
798 #define K7_DATA_CACHE_REFILL 0x42
799 #define K7_DATA_CACHE_REFILL_SYSTEM 0x43
800 #define K7_DATA_CACHE_WBACK 0x44
801 #define K7_L2_DTLB_HIT 0x45
802 #define K7_L2_DTLB_MISS 0x46
803 #define K7_MISALIGNED_DATA_REF 0x47
804 #define K7_SYSTEM_REQUEST 0x64
805 #define K7_SYSTEM_REQUEST_TYPE 0x65
806
807 #define K7_SNOOP_HIT 0x73
808 #define K7_SINGLE_BIT_ECC_ERROR 0x74
809 #define K7_CACHE_LINE_INVAL 0x75
810 #define K7_CYCLES_PROCESSOR_IS_RUNNING 0x76
811 #define K7_L2_REQUEST 0x79
812 #define K7_L2_REQUEST_BUSY 0x7a
813
814 /* Instruction Fetch Unit */
815 #define K7_IFU_IFETCH 0x80
816 #define K7_IFU_IFETCH_MISS 0x81
817 #define K7_IFU_REFILL_FROM_L2 0x82
818 #define K7_IFU_REFILL_FROM_SYSTEM 0x83
819 #define K7_ITLB_L1_MISS 0x84
820 #define K7_ITLB_L2_MISS 0x85
821 #define K7_SNOOP_RESYNC 0x86
822 #define K7_IFU_STALL 0x87
823
824 #define K7_RETURN_STACK_HITS 0x88
825 #define K7_RETURN_STACK_OVERFLOW 0x89
826
827 /* Retired */
828 #define K7_RETIRED_INST 0xc0
829 #define K7_RETIRED_OPS 0xc1
830 #define K7_RETIRED_BRANCHES 0xc2
831 #define K7_RETIRED_BRANCH_MISPREDICTED 0xc3
832 #define K7_RETIRED_TAKEN_BRANCH 0xc4
833 #define K7_RETIRED_TAKEN_BRANCH_MISPREDICTED 0xc5
834 #define K7_RETIRED_FAR_CONTROL_TRANSFER 0xc6
835 #define K7_RETIRED_RESYNC_BRANCH 0xc7
836 #define K7_RETIRED_NEAR_RETURNS 0xc8
837 #define K7_RETIRED_NEAR_RETURNS_MISPREDICTED 0xc9
838 #define K7_RETIRED_INDIRECT_MISPREDICTED 0xca
839
840 /* Interrupts */
841 #define K7_CYCLES_INT_MASKED 0xcd
842 #define K7_CYCLES_INT_PENDING_AND_MASKED 0xce
843 #define K7_HW_INTR_RECV 0xcf
844
845 #define K7_INSTRUCTION_DECODER_EMPTY 0xd0
846 #define K7_DISPATCH_STALLS 0xd1
847 #define K7_BRANCH_ABORTS_TO_RETIRE 0xd2
848 #define K7_SERIALIZE 0xd3
849 #define K7_SEGMENT_LOAD_STALL 0xd4
850 #define K7_ICU_FULL 0xd5
851 #define K7_RESERVATION_STATIONS_FULL 0xd6
852 #define K7_FPU_FULL 0xd7
853 #define K7_LS_FULL 0xd8
854 #define K7_ALL_QUIET_STALL 0xd9
855 #define K7_FAR_TRANSFER_OR_RESYNC_BRANCH_PENDING 0xda
856
857 #define K7_BP0_MATCH 0xdc
858 #define K7_BP1_MATCH 0xdd
859 #define K7_BP2_MATCH 0xde
860 #define K7_BP3_MATCH 0xdf
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